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Fix for RP2350

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This commit is contained in:
Jimmy
2026-02-14 23:38:20 +13:00
parent 4b06aa0841
commit a3510ab164
1 changed files with 42 additions and 46 deletions
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88
src/dma.py
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@@ -1,12 +1,13 @@
# DMA driver for Raspberry Pi Pico 2 (RP2350) only.
from machine import Pin
from rp2 import PIO, StateMachine, asm_pio
from time import sleep
import array
import uctypes
from uctypes import BF_POS, BF_LEN, UINT32, BFUINT32, struct
PIO0_BASE = 0x50200000
PIO1_BASE = 0x50300000
PIO2_BASE = 0x50400000
DMA_BASE = 0x50000000
DMA_CHAN_WIDTH = 0x40
DMA_CHAN_COUNT = 12
@@ -15,35 +16,34 @@ DMA_SIZE_BYTE = 0x0
DMA_SIZE_HALFWORD = 0x1
DMA_SIZE_WORD = 0x2
# DMA: RP2040 datasheet 2.5.7
# RP2350 DMA CTRL_TRIG bit positions
DMA_CTRL_TRIG_FIELDS = {
"AHB_ERROR": 31<<BF_POS | 1<<BF_LEN | BFUINT32,
"READ_ERROR": 30<<BF_POS | 1<<BF_LEN | BFUINT32,
"WRITE_ERROR": 29<<BF_POS | 1<<BF_LEN | BFUINT32,
"BUSY": 24<<BF_POS | 1<<BF_LEN | BFUINT32,
"SNIFF_EN": 23<<BF_POS | 1<<BF_LEN | BFUINT32,
"BSWAP": 22<<BF_POS | 1<<BF_LEN | BFUINT32,
"IRQ_QUIET": 21<<BF_POS | 1<<BF_LEN | BFUINT32,
"TREQ_SEL": 15<<BF_POS | 6<<BF_LEN | BFUINT32,
"CHAIN_TO": 11<<BF_POS | 4<<BF_LEN | BFUINT32,
"RING_SEL": 10<<BF_POS | 1<<BF_LEN | BFUINT32,
"RING_SIZE": 6<<BF_POS | 4<<BF_LEN | BFUINT32,
"INCR_WRITE": 5<<BF_POS | 1<<BF_LEN | BFUINT32,
"BUSY": 26<<BF_POS | 1<<BF_LEN | BFUINT32,
"SNIFF_EN": 25<<BF_POS | 1<<BF_LEN | BFUINT32,
"BSWAP": 24<<BF_POS | 1<<BF_LEN | BFUINT32,
"IRQ_QUIET": 23<<BF_POS | 1<<BF_LEN | BFUINT32,
"TREQ_SEL": 17<<BF_POS | 6<<BF_LEN | BFUINT32,
"CHAIN_TO": 13<<BF_POS | 4<<BF_LEN | BFUINT32,
"RING_SEL": 12<<BF_POS | 1<<BF_LEN | BFUINT32,
"RING_SIZE": 8<<BF_POS | 4<<BF_LEN | BFUINT32,
"INCR_WRITE": 6<<BF_POS | 1<<BF_LEN | BFUINT32,
"INCR_READ": 4<<BF_POS | 1<<BF_LEN | BFUINT32,
"DATA_SIZE": 2<<BF_POS | 2<<BF_LEN | BFUINT32,
"HIGH_PRIORITY":1<<BF_POS | 1<<BF_LEN | BFUINT32,
"EN": 0<<BF_POS | 1<<BF_LEN | BFUINT32
}
# Channel-specific DMA registers
DMA_CHAN_REGS = {
"READ_ADDR_REG": 0x00|UINT32,
"WRITE_ADDR_REG": 0x04|UINT32,
"TRANS_COUNT_REG": 0x08|UINT32,
"CTRL_TRIG_REG": 0x0c|UINT32,
"CTRL_TRIG": (0x0c,DMA_CTRL_TRIG_FIELDS)
"CTRL_TRIG": (0x0c, DMA_CTRL_TRIG_FIELDS)
}
# General DMA registers
DMA_REGS = {
"INTR": 0x400|UINT32,
"INTE0": 0x404|UINT32,
@@ -63,55 +63,51 @@ DMA_REGS = {
"CHAN_ABORT": 0x444|UINT32
}
DMA_CHANS = [struct(DMA_BASE + n*DMA_CHAN_WIDTH, DMA_CHAN_REGS) for n in range(0,DMA_CHAN_COUNT)]
DMA_CHANS = [struct(DMA_BASE + n*DMA_CHAN_WIDTH, DMA_CHAN_REGS) for n in range(DMA_CHAN_COUNT)]
DMA_DEVICE = struct(DMA_BASE, DMA_REGS)
DMA_CH0_AL3_TRANS_COUNT = DMA_BASE + 0x38
PIO_TX_FIFO_OFFSET = 0x10
# RP2350 DREQ: PIO0_TX=0-3, PIO0_RX=4-7, PIO1_TX=8-11, PIO1_RX=12-15, PIO2_TX=16-19
def _pio_base_and_treq(sm_num):
"""Return (PIO_BASE, TREQ_SEL) for state machine 0..11."""
if sm_num < 4:
return (PIO0_BASE, sm_num)
if sm_num < 8:
return (PIO1_BASE, sm_num + 4)
if sm_num < 12:
return (PIO2_BASE, sm_num + 8)
raise ValueError("state machine index out of range")
class PIO_DMA_Transfer():
def __init__(self, dma_channel, sm_num, block_size, transfer_count):
self.dma_chan = DMA_CHANS[dma_channel]
self.channel_number = dma_channel
if (sm_num >= 0 and sm_num < 4):
self.dma_chan.WRITE_ADDR_REG = PIO0_BASE + 0x10 + sm_num *4
self.dma_chan.CTRL_TRIG.TREQ_SEL = sm_num
elif (sm_num < 8):
self.dma_chan.WRITE_ADDR_REG = PIO1_BASE + 0x10 + (sm_num-4) *4
self.dma_chan.CTRL_TRIG.TREQ_SEL = sm_num + 4
if (block_size == 8):
pio_base, treq_sel = _pio_base_and_treq(sm_num)
sm_offset = (sm_num % 4) * 4
self.dma_chan.WRITE_ADDR_REG = pio_base + PIO_TX_FIFO_OFFSET + sm_offset
self.dma_chan.CTRL_TRIG.TREQ_SEL = treq_sel
if block_size == 8:
self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_BYTE
if (block_size == 16):
elif block_size == 16:
self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_HALFWORD
if (block_size == 32):
elif block_size == 32:
self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_WORD
self.dma_chan.TRANS_COUNT_REG = transfer_count
#Do I just always want these?
self.dma_chan.CTRL_TRIG.INCR_WRITE = 0
self.dma_chan.CTRL_TRIG.INCR_READ = 1
self.dma_chan.CTRL_TRIG.CHAIN_TO = dma_channel
def start_transfer(self, buffer):
self.dma_chan.READ_ADDR_REG = uctypes.addressof(buffer)
self.dma_chan.CTRL_TRIG.EN = 1
def transfer_count(self):
return self.dma_chan.TRANS_COUNT_REG
def busy(self):
if self.dma_chan.CTRL_TRIG.DATA_SIZE == 1:
return True
else:
return False
return bool(self.dma_chan.CTRL_TRIG_REG & (1 << 26))