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Strip library down to minimum

This commit is contained in:
jimmy 2024-01-24 08:08:35 +00:00
parent 0b3cd9e2db
commit b60f27acf6
1 changed files with 4 additions and 79 deletions
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75
dma.py
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@ -5,12 +5,6 @@ import array
import uctypes import uctypes
from uctypes import BF_POS, BF_LEN, UINT32, BFUINT32, struct from uctypes import BF_POS, BF_LEN, UINT32, BFUINT32, struct
GPIO_BASE = 0x40014000
GPIO_CHAN_WIDTH = 0x08
GPIO_PIN_COUNT = 30
PAD_BASE = 0x4001c000
PAD_PIN_WIDTH = 0x04
ADC_BASE = 0x4004c000
PIO0_BASE = 0x50200000 PIO0_BASE = 0x50200000
PIO1_BASE = 0x50300000 PIO1_BASE = 0x50300000
DMA_BASE = 0x50000000 DMA_BASE = 0x50000000
@ -69,26 +63,11 @@ DMA_REGS = {
"CHAN_ABORT": 0x444|UINT32 "CHAN_ABORT": 0x444|UINT32
} }
DREQ_PIO0_TX0, DREQ_PIO0_RX0, DREQ_PIO1_TX0 = 0, 4, 8
DREQ_PIO1_RX0, DREQ_SPI0_TX, DREQ_SPI0_RX = 12, 16, 17
DREQ_SPI1_TX, DREQ_SPI1_RX, DREQ_UART0_TX = 18, 19, 20
DREQ_UART0_RX, DREQ_UART1_TX, DREQ_UART1_RX = 21, 22, 23
DREQ_I2C0_TX, DREQ_I2C0_RX, DREQ_I2C1_TX = 32, 33, 34
DREQ_I2C1_RX, DREQ_ADC = 35, 36
DMA_CHANS = [struct(DMA_BASE + n*DMA_CHAN_WIDTH, DMA_CHAN_REGS) for n in range(0,DMA_CHAN_COUNT)] DMA_CHANS = [struct(DMA_BASE + n*DMA_CHAN_WIDTH, DMA_CHAN_REGS) for n in range(0,DMA_CHAN_COUNT)]
DMA_DEVICE = struct(DMA_BASE, DMA_REGS) DMA_DEVICE = struct(DMA_BASE, DMA_REGS)
GPIO_FUNC_SPI, GPIO_FUNC_UART, GPIO_FUNC_I2C = 1, 2, 3
GPIO_FUNC_PWM, GPIO_FUNC_SIO, GPIO_FUNC_PIO0 = 4, 5, 6
GPIO_FUNC_NULL = 0x1f
DMA_CH0_AL3_TRANS_COUNT = DMA_BASE + 0x38 DMA_CH0_AL3_TRANS_COUNT = DMA_BASE + 0x38
class PIO_DMA_Transfer(): class PIO_DMA_Transfer():
def __init__(self, dma_channel, sm_num, block_size, transfer_count): def __init__(self, dma_channel, sm_num, block_size, transfer_count):
self.dma_chan = DMA_CHANS[dma_channel] self.dma_chan = DMA_CHANS[dma_channel]
@ -127,66 +106,12 @@ class PIO_DMA_Transfer():
else: else:
return False return False
def abort_transfer(self):
pass
def chain_to(self, channel):
self.dma_chan.CTRL_TRIG.CHAIN_TO = channel
def get_number(self):
return self.channel_number
#looping transfers
#note -- see datasheet 2.5.7
#location of registers is -- AL3 transcount / read address trigger.
#Writing to these (from one DMA channel) will re-trigger a second DMA channel
#need to set write ring.
#could also set read ring?
#out_buff = array.array('L', ((x if (x<1000) else (2000-x)) for x in range(NSAMPLES)))
class DMA_Control_Block:
def __init__(self, this_chan, that_chan, read_address, transfer_count, loops):
self.dma_chan = DMA_CHANS[this_chan]
#note -- need to set this up to get the right location
#but for now just always control channel 0
self.dma_chan.WRITE_ADDR_REG = DMA_CH0_AL3_TRANS_COUNT
self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_WORD
self.dma_chan.TRANS_COUNT_REG = 2 # two transfers. One is the count, one is the read_address.
#Then pauses until the other channel chains back to this.
self.buffer = array.array('L', (x for x in range(2*loops)))
for x in range(loops):
self.buffer[2*x] = transfer_count
self.buffer[2*x+1] = read_address
self.start_address = uctypes.addressof(self.buffer)
#set up read ring
that_chan.chain_to(this_chan)
self.dma_chan.CTRL_TRIG.INCR_WRITE = 1
self.dma_chan.CTRL_TRIG.INCR_READ = 1
self.dma_chan.CTRL_TRIG.RING_SEL = 1
self.dma_chan.CTRL_TRIG.RING_SIZE = 3 # 1u<<3 bytes / 8 bytes
self.dma_chan.CTRL_TRIG.TREQ_SEL = 0x3f # unpaced transfer
def start_chain(self):
self.dma_chan.READ_ADDR_REG = self.start_address
self.dma_chan.CTRL_TRIG.EN = 1
def transfer_count(self):
return self.dma_chan.TRANS_COUNT_REG
def get_read_address(self):
return self.dma_chan.READ_ADDR_REG
def busy(self):
if self.dma_chan.CTRL_TRIG.DATA_SIZE == 1:
return True
else:
return False