Update dma.py
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dma.py
238
dma.py
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@ -1,11 +1,31 @@
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from machine import Pin
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from rp2 import PIO, StateMachine, asm_pio
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from time import sleep
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import array
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import uctypes
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from uctypes import BF_POS, BF_LEN, BFUINT32
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from uctypes import BF_POS, BF_LEN, UINT32, BFUINT32, struct
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DMA_CTRL_REG = {
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GPIO_BASE = 0x40014000
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GPIO_CHAN_WIDTH = 0x08
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GPIO_PIN_COUNT = 30
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PAD_BASE = 0x4001c000
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PAD_PIN_WIDTH = 0x04
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ADC_BASE = 0x4004c000
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PIO0_BASE = 0x50200000
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PIO1_BASE = 0x50300000
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DMA_BASE = 0x50000000
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DMA_CHAN_WIDTH = 0x40
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DMA_CHAN_COUNT = 12
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DMA_SIZE_BYTE = 0x0
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DMA_SIZE_HALFWORD = 0x1
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DMA_SIZE_WORD = 0x2
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# DMA: RP2040 datasheet 2.5.7
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DMA_CTRL_TRIG_FIELDS = {
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"AHB_ERROR": 31<<BF_POS | 1<<BF_LEN | BFUINT32,
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"READ_ERR": 30 << BF_POS | 1 << BF_LEN | BFUINT32,
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"WRITE_ERR": 29 << BF_POS | 1 << BF_LEN | BFUINT32,
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"Reserved": 25 << BF_POS | 4 << BF_LEN | BFUINT32,
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"READ_ERROR": 30<<BF_POS | 1<<BF_LEN | BFUINT32,
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"WRITE_ERROR": 29<<BF_POS | 1<<BF_LEN | BFUINT32,
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"BUSY": 24<<BF_POS | 1<<BF_LEN | BFUINT32,
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"SNIFF_EN": 23<<BF_POS | 1<<BF_LEN | BFUINT32,
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"BSWAP": 22<<BF_POS | 1<<BF_LEN | BFUINT32,
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@ -17,47 +37,183 @@ DMA_CTRL_REG = {
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"INCR_WRITE": 5<<BF_POS | 1<<BF_LEN | BFUINT32,
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"INCR_READ": 4<<BF_POS | 1<<BF_LEN | BFUINT32,
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"DATA_SIZE": 2<<BF_POS | 2<<BF_LEN | BFUINT32,
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"HIGH_PRIO": 1 << BF_POS | 1 << BF_LEN | BFUINT32,
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"EN": 0 << BF_POS | 1 << BF_LEN | BFUINT32,
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"HIGH_PRIORITY":1<<BF_POS | 1<<BF_LEN | BFUINT32,
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"EN": 0<<BF_POS | 1<<BF_LEN | BFUINT32
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}
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# Channel-specific DMA registers
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DMA_CHAN_REGS = {
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"READ_ADDR_REG": 0x00|UINT32,
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"WRITE_ADDR_REG": 0x04|UINT32,
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"TRANS_COUNT_REG": 0x08|UINT32,
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"CTRL_TRIG_REG": 0x0c|UINT32,
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"CTRL_TRIG": (0x0c,DMA_CTRL_TRIG_FIELDS)
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}
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DMA_LAYOUT = {
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"READ_ADDR": 0 | uctypes.UINT32,
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"WRITE_ADDR": 4 | uctypes.UINT32,
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"TRANS_COUNT": 8 | uctypes.UINT32,
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"CTRL_TRIG": (12, DMA_CTRL_REG),
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"CTRL_TRIG_RAW": 12 | uctypes.UINT32, # for single update of all fields
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"AL1_CTRL": 16 | uctypes.UINT32,
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# General DMA registers
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DMA_REGS = {
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"INTR": 0x400|UINT32,
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"INTE0": 0x404|UINT32,
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"INTF0": 0x408|UINT32,
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"INTS0": 0x40c|UINT32,
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"INTE1": 0x414|UINT32,
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"INTF1": 0x418|UINT32,
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"INTS1": 0x41c|UINT32,
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"TIMER0": 0x420|UINT32,
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"TIMER1": 0x424|UINT32,
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"TIMER2": 0x428|UINT32,
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"TIMER3": 0x42c|UINT32,
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"MULTI_CHAN_TRIGGER": 0x430|UINT32,
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"SNIFF_CTRL": 0x434|UINT32,
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"SNIFF_DATA": 0x438|UINT32,
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"FIFO_LEVELS": 0x440|UINT32,
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"CHAN_ABORT": 0x444|UINT32
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}
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# create the DMA channel structs (0-11)
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CHANNELS = [uctypes.struct(0x50000000 + i * 0x40, DMA_LAYOUT) for i in range(0,12)]
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DREQ_PIO0_TX0, DREQ_PIO0_RX0, DREQ_PIO1_TX0 = 0, 4, 8
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DREQ_PIO1_RX0, DREQ_SPI0_TX, DREQ_SPI0_RX = 12, 16, 17
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DREQ_SPI1_TX, DREQ_SPI1_RX, DREQ_UART0_TX = 18, 19, 20
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DREQ_UART0_RX, DREQ_UART1_TX, DREQ_UART1_RX = 21, 22, 23
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DREQ_I2C0_TX, DREQ_I2C0_RX, DREQ_I2C1_TX = 32, 33, 34
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DREQ_I2C1_RX, DREQ_ADC = 35, 36
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# init dma channels to some default values
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def init_channels():
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for i, ch in enumerate(CHANNELS):
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# no wraparound, sniff=0, swap_byte=0, irq_quiet=1
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# unpaced transfers (=0x3f). high prio=0, data_size=word, incr_r/w = true
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ch.CTRL_TRIG_RAW = 0x3f8030
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# set chain to itself, to disable chaining
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ch.CTRL_TRIG.CHAIN_TO = i
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DREQ_PIO0_TX0 , DREQ_PIO0_TX1, DREQ_PIO0_TX2, DREQ_PIO0_TX3 = 0, 1, 2, 3
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DREQ_PIO1_TX0 , DREQ_PIO1_TX1, DREQ_PIO1_TX2, DREQ_PIO1_TX3 = 8, 9, 10, 11
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# example function to show mem->mem transfer
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# dest, src can be bytearrays, size in bytes
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def memcopy(ch, dest, src, size, enable=1):
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ch.CTRL_TRIG.EN = 0
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ch.WRITE_ADDR = uctypes.addressof(dest)
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ch.READ_ADDR = uctypes.addressof(src)
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ch.TRANS_COUNT = size // (1 << ch.CTRL_TRIG.DATA_SIZE)
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ch.CTRL_TRIG.EN = enable
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DMA_CHANS = [struct(DMA_BASE + n*DMA_CHAN_WIDTH, DMA_CHAN_REGS) for n in range(0,DMA_CHAN_COUNT)]
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DMA_DEVICE = struct(DMA_BASE, DMA_REGS)
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PIO0_TX0 = PIO0_BASE + 0x010
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PIO0_TX1 = PIO0_BASE + 0x014
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PIO0_TX2 = PIO0_BASE + 0x018
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PIO0_TX3 = PIO0_BASE + 0x01c
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PIO1_TX0 = PIO1_BASE + 0x010
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PIO1_TX1 = PIO1_BASE + 0x014
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PIO1_TX2 = PIO1_BASE + 0x018
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PIO1_TX3 = PIO1_BASE + 0x01c
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GPIO_FUNC_SPI, GPIO_FUNC_UART, GPIO_FUNC_I2C = 1, 2, 3
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GPIO_FUNC_PWM, GPIO_FUNC_SIO, GPIO_FUNC_PIO0 = 4, 5, 6
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GPIO_FUNC_NULL = 0x1f
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DMA_CH0_AL3_TRANS_COUNT = DMA_BASE + 0x38
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# can be used to temporary construct the necessary DMA CTRL values
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# then copy over to actual dma channel's CTRL value in one write
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# e.g.
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# scratch.CHAIN_TO=2;
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# scratch.DATA_SIZE=2;
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# ...
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# CH0.CTRL_TRIG_RAW=scratch.CTRL_TRIG_RAW
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tmp = bytearray(uctypes.sizeof(DMA_LAYOUT))
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scratch_ctrl = uctypes.struct(uctypes.addressof(tmp), DMA_CTRL_REG)
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class PIO_DMA_Transfer():
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def __init__(self, dma_channel, sm_num, block_size, transfer_count):
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self.dma_chan = DMA_CHANS[dma_channel]
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self.channel_number = dma_channel
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if (sm_num == 0):
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self.dma_chan.WRITE_ADDR_REG = PIO0_TX0
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO0_TX0
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elif (sm_num == 1):
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self.dma_chan.WRITE_ADDR_REG = PIO0_TX1
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO0_TX1
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elif (sm_num == 2):
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self.dma_chan.WRITE_ADDR_REG = PIO0_TX2
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO0_TX2
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elif (sm_num == 3):
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self.dma_chan.WRITE_ADDR_REG = PIO0_TX3
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO0_TX3
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elif (sm_num == 4):
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self.dma_chan.WRITE_ADDR_REG = PIO1_TX0
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO1_TX0
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elif (sm_num == 5):
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self.dma_chan.WRITE_ADDR_REG = PIO1_TX1
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO1_TX1
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elif (sm_num == 6):
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self.dma_chan.WRITE_ADDR_REG = PIO1_TX2
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO1_TX2
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elif (sm_num == 7):
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self.dma_chan.WRITE_ADDR_REG = PIO1_TX3
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self.dma_chan.CTRL_TRIG.TREQ_SEL = DREQ_PIO1_TX3
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if (block_size == 8):
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self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_BYTE
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if (block_size == 16):
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self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_HALFWORD
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if (block_size == 32):
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self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_WORD
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self.dma_chan.TRANS_COUNT_REG = transfer_count
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#Do I just always want these?
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self.dma_chan.CTRL_TRIG.INCR_WRITE = 0
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self.dma_chan.CTRL_TRIG.INCR_READ = 1
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def start_transfer(self, buffer):
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self.dma_chan.READ_ADDR_REG = uctypes.addressof(buffer)
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self.dma_chan.CTRL_TRIG.EN = 1
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def transfer_count(self):
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return self.dma_chan.TRANS_COUNT_REG
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def busy(self):
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if self.dma_chan.CTRL_TRIG.DATA_SIZE == 1:
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return True
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else:
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return False
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def abort_transfer(self):
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pass
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def chain_to(self, channel):
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self.dma_chan.CTRL_TRIG.CHAIN_TO = channel
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def get_number(self):
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return self.channel_number
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#looping transfers
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#note -- see datasheet 2.5.7
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#location of registers is -- AL3 transcount / read address trigger.
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#Writing to these (from one DMA channel) will re-trigger a second DMA channel
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#need to set write ring.
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#could also set read ring?
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#out_buff = array.array('L', ((x if (x<1000) else (2000-x)) for x in range(NSAMPLES)))
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class DMA_Control_Block:
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def __init__(self, this_chan, that_chan, read_address, transfer_count, loops):
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self.dma_chan = DMA_CHANS[this_chan]
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#note -- need to set this up to get the right location
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#but for now just always control channel 0
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self.dma_chan.WRITE_ADDR_REG = DMA_CH0_AL3_TRANS_COUNT
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self.dma_chan.CTRL_TRIG.DATA_SIZE = DMA_SIZE_WORD
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self.dma_chan.TRANS_COUNT_REG = 2 # two transfers. One is the count, one is the read_address.
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#Then pauses until the other channel chains back to this.
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self.buffer = array.array('L', (x for x in range(2*loops)))
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for x in range(loops):
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self.buffer[2*x] = transfer_count
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self.buffer[2*x+1] = read_address
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self.start_address = uctypes.addressof(self.buffer)
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#set up read ring
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that_chan.chain_to(this_chan)
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self.dma_chan.CTRL_TRIG.INCR_WRITE = 1
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self.dma_chan.CTRL_TRIG.INCR_READ = 1
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self.dma_chan.CTRL_TRIG.RING_SEL = 1
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self.dma_chan.CTRL_TRIG.RING_SIZE = 3 # 1u<<3 bytes / 8 bytes
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self.dma_chan.CTRL_TRIG.TREQ_SEL = 0x3f # unpaced transfer
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def start_chain(self):
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self.dma_chan.READ_ADDR_REG = self.start_address
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self.dma_chan.CTRL_TRIG.EN = 1
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def transfer_count(self):
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return self.dma_chan.TRANS_COUNT_REG
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def get_read_address(self):
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return self.dma_chan.READ_ADDR_REG
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def busy(self):
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if self.dma_chan.CTRL_TRIG.DATA_SIZE == 1:
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return True
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else:
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return False
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