160 lines
5.6 KiB
C
160 lines
5.6 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8188E_SPEC_H__
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#define __RTL8188E_SPEC_H__
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/* ************************************************************
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* 8188E Regsiter offset definition
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* ************************************************************ */
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/* ************************************************************
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*
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* ************************************************************ */
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/* -----------------------------------------------------
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*
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* 0x0000h ~ 0x00FFh System Configuration
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*
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* ----------------------------------------------------- */
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#define REG_BB_PAD_CTRL 0x0064
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#define REG_HMEBOX_E0 0x0088
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#define REG_HMEBOX_E1 0x008A
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#define REG_HMEBOX_E2 0x008C
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#define REG_HMEBOX_E3 0x008E
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#define REG_HMEBOX_EXT_0 0x01F0
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#define REG_HMEBOX_EXT_1 0x01F4
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#define REG_HMEBOX_EXT_2 0x01F8
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#define REG_HMEBOX_EXT_3 0x01FC
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#define REG_HIMR_88E 0x00B0 /* RTL8188E */
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#define REG_HISR_88E 0x00B4 /* RTL8188E */
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#define REG_HIMRE_88E 0x00B8 /* RTL8188E */
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#define REG_HISRE_88E 0x00BC /* RTL8188E */
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#define REG_DBI_WDATA_8188E 0x0348 /* DBI Write data */
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#define REG_DBI_RDATA_8188E 0x034C /* DBI Read data */
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#define REG_DBI_ADDR_8188E 0x0350 /* DBI Address */
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#define REG_DBI_FLAG_8188E 0x0352 /* DBI Read/Write Flag */
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#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
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#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
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#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
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#define REG_MACID_NO_LINK_0 0x0484
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#define REG_MACID_NO_LINK_1 0x0488
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#define REG_MACID_PAUSE_0 0x048c
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#define REG_MACID_PAUSE_1 0x0490
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/* -----------------------------------------------------
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*
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* 0x0100h ~ 0x01FFh MACTOP General Configuration
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*
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* ----------------------------------------------------- */
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#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
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#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
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#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
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#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
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/* -----------------------------------------------------
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*
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* 0x0200h ~ 0x027Fh TXDMA Configuration
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*
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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*
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* 0x0280h ~ 0x02FFh RXDMA Configuration
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*
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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*
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* 0x0300h ~ 0x03FFh PCIe
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*
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* ----------------------------------------------------- */
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#define REG_PCIE_HRPWM_8188E 0x0361 /* PCIe RPWM */
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#define REG_PCIE_HCPWM_8188E 0x0363 /* PCIe CPWM */
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/* -----------------------------------------------------
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*
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* 0x0400h ~ 0x047Fh Protocol Configuration
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*
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* ----------------------------------------------------- */
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#ifdef CONFIG_WOWLAN
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#define REG_TXPKTBUF_IV_LOW 0x01a4
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#define REG_TXPKTBUF_IV_HIGH 0x01a8
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#endif
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/* -----------------------------------------------------
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*
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* 0x0500h ~ 0x05FFh EDCA Configuration
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*
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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*
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* 0x0600h ~ 0x07FFh WMAC Configuration
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*
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* ----------------------------------------------------- */
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#ifdef CONFIG_RF_POWER_TRIM
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#define EEPROM_RF_GAIN_OFFSET 0xC1
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#define EEPROM_RF_GAIN_VAL 0xF6
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#define EEPROM_THERMAL_OFFSET 0xF5
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#endif /*CONFIG_RF_POWER_TRIM*/
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/* ----------------------------------------------------------------------------
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* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
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* ----------------------------------------------------------------------------
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* IOL config for REG_FDHM0(Reg0x88) */
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#define CMD_INIT_LLT BIT0
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#define CMD_READ_EFUSE_MAP BIT1
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#define CMD_EFUSE_PATCH BIT2
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#define CMD_IOCONFIG BIT3
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#define CMD_INIT_LLT_ERR BIT4
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#define CMD_READ_EFUSE_MAP_ERR BIT5
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#define CMD_EFUSE_PATCH_ERR BIT6
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#define CMD_IOCONFIG_ERR BIT7
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/* -----------------------------------------------------
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*
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* Redifine register definition for compatibility
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*
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* ----------------------------------------------------- */
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/* TODO: use these definition when using REG_xxx naming rule.
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* NOTE: DO NOT Remove these definition. Use later. */
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#define ISR_88E REG_HISR_88E
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#ifdef CONFIG_PCI_HCI
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/* #define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
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#define IMR_TX_MASK (IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
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#ifdef CONFIG_CONCURRENT_MODE
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#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
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#else
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#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
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#endif
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#define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
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#endif
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/* ----------------------------------------------------------------------------
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* 8192C EEPROM/EFUSE share register definition.
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* ---------------------------------------------------------------------------- */
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#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
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#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
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#endif /* __RTL8188E_SPEC_H__ */
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