618 lines
14 KiB
C
618 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMANTDIV_H__
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#define __PHYDMANTDIV_H__
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/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
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/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
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/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
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/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
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/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
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/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
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because antenna diversity only works when BT is disable or radio off*/
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/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
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/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
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/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */
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/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */
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/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */
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/*#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
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#define ANTDIV_VERSION "4.0" /*2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */
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/* 1 ============================================================
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* 1 Definition
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* 1 ============================================================ */
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#define ANTDIV_INIT 0xff
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#define MAIN_ANT 1 /*ant A or ant Main or S1*/
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#define AUX_ANT 2 /*AntB or ant Aux or S0*/
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#define MAX_ANT 3 /* 3 for AP using*/
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#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
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#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
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/*smart antenna*/
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#define SUPPORT_RF_PATH_NUM 4
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#define SUPPORT_BEAM_PATTERN_NUM 4
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#define NUM_ANTENNA_8821A 2
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#define SUPPORT_BEAM_SET_PATTERN_NUM 16
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#define NO_FIX_TX_ANT 0
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#define FIX_TX_AT_MAIN 1
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#define FIX_AUX_AT_MAIN 2
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/* Antenna Diversty Control type */
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#define ODM_AUTO_ANT 0
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#define ODM_FIX_MAIN_ANT 1
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#define ODM_FIX_AUX_ANT 2
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#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A)
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#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
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#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
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#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
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#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
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#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D)
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#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
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#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
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#define ODM_ANTDIV_2G BIT(0)
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#define ODM_ANTDIV_5G BIT(1)
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#define ANTDIV_ON 1
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#define ANTDIV_OFF 0
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#define FAT_ON 1
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#define FAT_OFF 0
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#define TX_BY_DESC 1
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#define TX_BY_REG 0
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#define RSSI_METHOD 0
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#define EVM_METHOD 1
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#define CRC32_METHOD 2
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#define TP_METHOD 3
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#define INIT_ANTDIV_TIMMER 0
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#define CANCEL_ANTDIV_TIMMER 1
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#define RELEASE_ANTDIV_TIMMER 2
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#define CRC32_FAIL 1
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#define CRC32_OK 0
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#define evm_rssi_th_high 25
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#define evm_rssi_th_low 20
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#define NORMAL_STATE_MIAN 1
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#define NORMAL_STATE_AUX 2
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#define TRAINING_STATE 3
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#define FORCE_RSSI_DIFF 10
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#define CSI_ON 1
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#define CSI_OFF 0
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#define DIVON_CSIOFF 1
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#define DIVOFF_CSION 2
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#define BDC_DIV_TRAIN_STATE 0
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#define bdc_bfer_train_state 1
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#define BDC_DECISION_STATE 2
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#define BDC_BF_HOLD_STATE 3
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#define BDC_DIV_HOLD_STATE 4
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#define BDC_MODE_1 1
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#define BDC_MODE_2 2
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#define BDC_MODE_3 3
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#define BDC_MODE_4 4
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#define BDC_MODE_NULL 0xff
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/*SW S0S1 antenna diversity*/
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#define SWAW_STEP_INIT 0xff
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#define SWAW_STEP_PEEK 0
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#define SWAW_STEP_DETERMINE 1
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#define RSSI_CHECK_RESET_PERIOD 10
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#define RSSI_CHECK_THRESHOLD 50
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/*Hong Lin Smart antenna*/
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#define HL_SMTANT_2WIRE_DATA_LEN 24
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/* 1 ============================================================
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* 1 structure
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* 1 ============================================================ */
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struct sw_antenna_switch {
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u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
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u8 try_flag;
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s32 pre_rssi;
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u8 cur_antenna;
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u8 pre_antenna;
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u8 rssi_trying;
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u8 reset_idx;
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u8 train_time;
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u8 train_time_flag; /*base on RSSI difference between two antennas*/
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struct phydm_timer_list phydm_sw_antenna_switch_timer;
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u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
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boolean is_sw_ant_div_by_ctrl_frame;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#if USE_WORKITEM
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RT_WORK_ITEM phydm_sw_antenna_switch_workitem;
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#endif
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#endif
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/* AntDect (Before link Antenna Switch check) need to be moved*/
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u16 single_ant_counter;
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u16 dual_ant_counter;
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u16 aux_fail_detec_counter;
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u16 retry_counter;
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u8 swas_no_link_state;
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u32 swas_no_link_bk_reg948;
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boolean ANTA_ON; /*To indicate ant A is or not*/
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boolean ANTB_ON; /*To indicate ant B is on or not*/
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boolean pre_aux_fail_detec;
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boolean rssi_ant_dect_result;
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u8 ant_5g;
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u8 ant_2g;
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};
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
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struct _BF_DIV_COEX_ {
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boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
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boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
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u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
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u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
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u8 bd_ccoex_type_wbfer;
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u8 num_txbfee_client;
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u8 num_txbfer_client;
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u8 bdc_try_counter;
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u8 bdc_hold_counter;
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u8 bdc_mode;
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u8 bdc_active_mode;
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u8 BDC_state;
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u8 bdc_rx_idle_update_counter;
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u8 num_client;
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u8 pre_num_client;
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u8 num_bf_tar;
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u8 num_div_tar;
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boolean is_all_div_sta_idle;
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boolean is_all_bf_sta_idle;
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boolean bdc_try_flag;
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boolean BF_pass;
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boolean DIV_pass;
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};
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#endif
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#endif
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struct phydm_fat_struct {
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u8 bssid[6];
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u8 antsel_rx_keep_0;
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u8 antsel_rx_keep_1;
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u8 antsel_rx_keep_2;
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u8 antsel_rx_keep_3;
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u32 ant_sum_rssi[7];
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u32 ant_rssi_cnt[7];
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u32 ant_ave_rssi[7];
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u8 fat_state;
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u8 fat_state_cnt;
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u32 train_idx;
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u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
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u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
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u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u8 rx_idle_ant;
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u8 rvrt_val;
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u8 ant_div_on_off;
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boolean is_become_linked;
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u32 min_max_rssi;
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u8 idx_ant_div_counter_2g;
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u8 idx_ant_div_counter_5g;
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u8 ant_div_2g_5g;
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#ifdef ODM_EVM_ENHANCE_ANTDIV
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/*For 1SS RX phy rate*/
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u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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/*For 2SS RX phy rate*/
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u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/
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u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A2+B*/
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u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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boolean evm_method_enable;
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u8 target_ant_evm;
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u8 target_ant_crc32;
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u8 target_ant_tp;
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u8 target_ant_enhance;
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u8 pre_target_ant_enhance;
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u16 main_mpdu_ok_cnt;
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u16 aux_mpdu_ok_cnt;
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u32 crc32_ok_cnt;
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u32 crc32_fail_cnt;
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u32 main_crc32_ok_cnt;
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u32 aux_crc32_ok_cnt;
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u32 main_crc32_fail_cnt;
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u32 aux_crc32_fail_cnt;
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u32 antdiv_tp_main;
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u32 antdiv_tp_aux;
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u32 antdiv_tp_main_cnt;
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u32 antdiv_tp_aux_cnt;
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u8 pre_antdiv_rssi;
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u8 pre_antdiv_tp;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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u32 cck_ctrl_frame_cnt_main;
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u32 cck_ctrl_frame_cnt_aux;
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u32 ofdm_ctrl_frame_cnt_main;
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u32 ofdm_ctrl_frame_cnt_aux;
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u32 main_ant_ctrl_frame_sum;
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u32 aux_ant_ctrl_frame_sum;
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u32 main_ant_ctrl_frame_cnt;
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u32 aux_ant_ctrl_frame_cnt;
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#endif
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u8 b_fix_tx_ant;
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boolean fix_ant_bfee;
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boolean enable_ctrl_frame_antdiv;
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boolean use_ctrl_frame_antdiv;
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boolean *is_no_csi_feedback;
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u8 hw_antsw_occur;
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u8 *p_force_tx_ant_by_desc;
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u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/
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u8 *p_default_s0_s1;
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u8 default_s0_s1;
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};
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/* 1 ============================================================
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* 1 enumeration
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* 1 ============================================================ */
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enum fat_state /*Fast antenna training*/
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{
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FAT_BEFORE_LINK_STATE = 0,
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FAT_PREPARE_STATE = 1,
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FAT_TRAINING_STATE = 2,
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FAT_DECISION_STATE = 3
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};
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enum ant_div_type {
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NO_ANTDIV = 0xFF,
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CG_TRX_HW_ANTDIV = 0x01,
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CGCS_RX_HW_ANTDIV = 0x02,
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FIXED_HW_ANTDIV = 0x03,
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CG_TRX_SMART_ANTDIV = 0x04,
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CGCS_RX_SW_ANTDIV = 0x05,
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S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
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S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
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HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/
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HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
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};
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/* 1 ============================================================
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* 1 function prototype
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* 1 ============================================================ */
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void
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odm_stop_antenna_switch_dm(
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void *dm_void
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);
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void
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phydm_enable_antenna_diversity(
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void *dm_void
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);
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void
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odm_set_ant_config(
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void *dm_void,
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u8 ant_setting /* 0=A, 1=B, 2=C, .... */
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);
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#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
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void odm_sw_ant_div_rest_after_link(
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void *dm_void
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);
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void
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odm_ant_div_on_off(
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void *dm_void,
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u8 swch
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);
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void
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odm_tx_by_tx_desc_or_reg(
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void *dm_void,
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u8 swch
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);
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#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
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void
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phydm_antdiv_reset_statistic(
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void *dm_void,
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u32 macid
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);
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void
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odm_update_rx_idle_ant(
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void *dm_void,
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u8 ant
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);
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void
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phydm_set_antdiv_val(
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void *dm_void,
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u32 *val_buf,
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u8 val_len
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);
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#if (RTL8723B_SUPPORT == 1)
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void
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odm_update_rx_idle_ant_8723b(
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void *dm_void,
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u8 ant,
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u32 default_ant,
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u32 optional_ant
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);
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#endif
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#if (RTL8188F_SUPPORT == 1)
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void
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phydm_update_rx_idle_antenna_8188F(
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void *dm_void,
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u32 default_ant
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);
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#endif
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#if (RTL8723D_SUPPORT == 1)
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void
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phydm_set_tx_ant_pwr_8723d(
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void *dm_void,
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u8 ant
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);
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void
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odm_update_rx_idle_ant_8723d(
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void *dm_void,
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u8 ant,
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u32 default_ant,
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u32 optional_ant
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);
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#endif
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#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void
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odm_sw_antdiv_callback(
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struct phydm_timer_list *timer
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);
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void
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odm_sw_antdiv_workitem_callback(
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void *context
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);
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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void
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odm_sw_antdiv_workitem_callback(
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void *context
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);
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void
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odm_sw_antdiv_callback(
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void *function_context
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);
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#endif
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void
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odm_s0s1_sw_ant_div_by_ctrl_frame(
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void *dm_void,
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u8 step
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);
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void
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odm_antsel_statistics_of_ctrl_frame(
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void *dm_void,
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u8 antsel_tr_mux,
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u32 rx_pwdb_all
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);
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void
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odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
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void *dm_void,
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void *phy_info_void,
|
|
void *pkt_info_void
|
|
);
|
|
|
|
#endif
|
|
|
|
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
|
void
|
|
phydm_evm_sw_antdiv_init(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_evm_fast_ant_training_callback(
|
|
void *dm_void
|
|
);
|
|
#endif
|
|
|
|
void
|
|
odm_hw_ant_div(
|
|
void *dm_void
|
|
);
|
|
|
|
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
|
|
void
|
|
odm_fast_ant_training(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_fast_ant_training_callback(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_fast_ant_training_work_item_callback(
|
|
void *dm_void
|
|
);
|
|
#endif
|
|
|
|
void
|
|
odm_ant_div_init(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_ant_div(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_antsel_statistics(
|
|
void *dm_void,
|
|
void *phy_info_void,
|
|
u8 antsel_tr_mux,
|
|
u32 mac_id,
|
|
u32 utility,
|
|
u8 method,
|
|
u8 is_cck_rate
|
|
);
|
|
|
|
void
|
|
odm_process_rssi_for_ant_div(
|
|
void *dm_void,
|
|
void *phy_info_void,
|
|
void *pkt_info_void
|
|
);
|
|
|
|
|
|
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
|
void
|
|
odm_set_tx_ant_by_tx_info(
|
|
void *dm_void,
|
|
u8 *desc,
|
|
u8 mac_id
|
|
);
|
|
|
|
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
|
|
|
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
|
|
|
|
void
|
|
odm_set_tx_ant_by_tx_info(
|
|
struct rtl8192cd_priv *priv,
|
|
struct tx_desc *pdesc,
|
|
unsigned short aid
|
|
);
|
|
|
|
#if 1/*def def CONFIG_WLAN_HAL*/
|
|
void
|
|
odm_set_tx_ant_by_tx_info_hal(
|
|
struct rtl8192cd_priv *priv,
|
|
void *pdesc_data,
|
|
u16 aid
|
|
);
|
|
#endif /*#ifdef CONFIG_WLAN_HAL*/
|
|
#endif
|
|
|
|
|
|
void
|
|
odm_ant_div_config(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_ant_div_timers(
|
|
void *dm_void,
|
|
u8 state
|
|
);
|
|
|
|
void
|
|
phydm_antdiv_debug(
|
|
void *dm_void,
|
|
u32 *const dm_value,
|
|
u32 *_used,
|
|
char *output,
|
|
u32 *_out_len
|
|
);
|
|
|
|
#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
|
|
|
|
void
|
|
odm_ant_div_reset(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_antenna_diversity_init(
|
|
void *dm_void
|
|
);
|
|
|
|
void
|
|
odm_antenna_diversity(
|
|
void *dm_void
|
|
);
|
|
|
|
#endif /*#ifndef __ODMANTDIV_H__*/
|