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New upstream version 5.3.9~20191129

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This commit is contained in:
Sophie Brun
2019-12-17 17:14:15 +01:00
commit 64d530c26f
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1451
hal/phydm/rtl8188e/hal8188erateadaptive.c Normal file
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hal/phydm/rtl8188e/hal8188erateadaptive.h Normal file
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/******************************************************************************
*
* Copyright(c) Semiconductor - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_RA_H
#define __INC_RA_H
/* rate adaptive define */
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#define DM_RA_RATE_UP 1
#define DM_RA_RATE_DOWN 2
#define AP_USB_SDIO ((DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)))
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
/*
* TX report 2 format in Rx desc
* */
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr+2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr+3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr+4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr+4+1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr+4+3, 0, 8)
#endif
enum phydm_rateid_idx_88e_e { /*Copy From SD4 _RATR_TABLE_MODE*/
PHYDM_RAID_88E_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
PHYDM_RAID_88E_NG = 1, /* GN or N */
PHYDM_RAID_88E_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
PHYDM_RAID_88E_N = 3,
PHYDM_RAID_88E_GB = 4,
PHYDM_RAID_88E_G = 5,
PHYDM_RAID_88E_B = 6,
PHYDM_RAID_88E_MC = 7,
PHYDM_RAID_88E_AC_N = 8
};
/* End rate adaptive define */
void
odm_ra_support_init(
struct dm_struct *dm
);
void
odm_ra_info_init_all(
struct dm_struct *dm
);
int
odm_ra_info_init(
struct dm_struct *dm,
u32 mac_id
);
u8
odm_ra_get_sgi_8188e(
struct dm_struct *dm,
u8 mac_id
);
u8
odm_ra_get_decision_rate_8188e(
struct dm_struct *dm,
u8 mac_id
);
u8
odm_ra_get_hw_pwr_status_8188e(
struct dm_struct *dm,
u8 mac_id
);
u8
phydm_get_rate_id_88e(
void *dm_void,
u8 macid
);
void
odm_ra_update_rate_info_8188e(
struct dm_struct *dm,
u8 mac_id,
u8 rate_id,
u32 rate_mask,
u8 sgi_enable
);
void
odm_ra_set_rssi_8188e(
struct dm_struct *dm,
u8 mac_id,
u8 rssi
);
void
odm_ra_tx_rpt2_handle_8188e(
struct dm_struct *dm,
u8 *tx_rpt_buf,
u16 tx_rpt_len,
u32 mac_id_valid_entry0,
u32 mac_id_valid_entry1
);
void
odm_ra_set_tx_rpt_time(
struct dm_struct *dm,
u16 min_rpt_time
);
#endif

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hal/phydm/rtl8188e/hal8188ereg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* File Name: hal8188ereg.h
*
* Description:
*
* This file is for RTL8188E register definition.
*
*
* ************************************************************ */
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
/*
* Register Definition
* */
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_MCUFWDL_8188E 0x0080
#define REG_FW_DBG_STATUS_8188E 0x0088
#define REG_FW_DBG_CTRL_8188E 0x008F
#define REG_CR_8188E 0x0100
/*
* Bitmap Definition
* */
#define BIT_FA_RESET_8188E BIT(0)
#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */
#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */
#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */
#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */
#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
/* [0-63] */
#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */
#endif

1759
hal/phydm/rtl8188e/halhwimg8188e_bb.c Normal file
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hal/phydm/rtl8188e/halhwimg8188e_bb.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8188E_H
#define __INC_MP_BB_HW_IMG_8188E_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_agc_tab(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_phy_reg(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_phy_reg_pg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8188e/halhwimg8188e_mac.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = dm->cut_version << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
dm->package_type << 12 |
(dm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, dm->package_type);
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u32 array_mp_8188e_mac_reg[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x80000002, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000001, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000002, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0xA0000000, 0x00000000,
0x040, 0x00000000,
0xB0000000, 0x00000000,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000001,
0x432, 0x00000002,
0x433, 0x00000004,
0x434, 0x00000005,
0x435, 0x00000006,
0x436, 0x00000007,
0x437, 0x00000008,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000001,
0x43B, 0x00000002,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x480, 0x00000008,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4D3, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x63C, 0x00000008,
0x63D, 0x00000008,
0x63E, 0x0000000C,
0x63F, 0x0000000C,
0x640, 0x00000040,
0x652, 0x00000020,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
odm_read_and_config_mp_8188e_mac_reg(
struct dm_struct *dm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8188e_mac_reg) / sizeof(u32);
u32 *array = array_mp_8188e_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8188e_mac_reg\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8188e(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8188e_mac_reg(void)
{
return 70;
}
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8188e/halhwimg8188e_mac.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8188E_H
#define __INC_MP_MAC_HW_IMG_8188E_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_mac_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8188e/halhwimg8188e_rf.c Normal file
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hal/phydm/rtl8188e/halhwimg8188e_rf.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8188E_H
#define __INC_MP_RF_HW_IMG_8188E_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_radioa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_radioa(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_ap(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_ap(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_pcie(void);
/******************************************************************************
* TxPowerTrack_PCIE_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie_icut(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_pcie_icut(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_sdio(void);
/******************************************************************************
* TxPowerTrack_SDIO_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio_icut(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_sdio_icut(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_usb(void);
/******************************************************************************
* TxPowerTrack_USB_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb_icut(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpowertrack_usb_icut(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpwr_lmt(void);
/******************************************************************************
* TXPWR_LMT_88EE_M2_for_MSI.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt_88e_e_m2_for_msi(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8188e_txpwr_lmt_88ee_m2_for_msi(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8188e/phydm_regconfig8188e.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void
odm_config_rf_reg_8188e(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path RF_PATH,
u32 reg_addr
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifndef SMP_SYNC
unsigned long x;
#endif
struct rtl8192cd_priv *priv = dm->priv;
#endif
if (addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
SAVE_INT_AND_CLI(x);
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
RESTORE_INT(x);
#else
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
#endif
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void
odm_config_rf_radio_a_8188e(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data);
}
void
odm_config_rf_radio_b_8188e(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data);
}
void
odm_config_mac_8188e(
struct dm_struct *dm,
u32 addr,
u8 data
)
{
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data);
}
void
odm_config_bb_agc_8188e(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data);
}
void
odm_config_bb_phy_reg_pg_8188e(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data);
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
}
void
odm_config_bb_txpwr_lmt_8188e(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
void
odm_config_bb_phy_8188e(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
if (addr == 0xa24)
dm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data);
}
}
#endif

90
hal/phydm/rtl8188e/phydm_regconfig8188e.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void
odm_config_rf_reg_8188e(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path RF_PATH,
u32 reg_addr
);
void
odm_config_rf_radio_a_8188e(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_rf_radio_b_8188e(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_mac_8188e(
struct dm_struct *dm,
u32 addr,
u8 data
);
void
odm_config_bb_agc_8188e(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_reg_pg_8188e(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_8188e(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_txpwr_lmt_8188e(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
#endif
#endif /* end of SUPPORT */

55
hal/phydm/rtl8188e/phydm_rtl8188e.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void
odm_dig_lower_bound_88e(
struct dm_struct *dm
)
{
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
dig_t->rx_gain_range_min = (u8) dig_t->ant_div_rssi_max;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_dig_lower_bound_88e(): dig_t->ant_div_rssi_max=%d\n", dig_t->ant_div_rssi_max);
}
/* If only one Entry connected */
}
/*=============================================================
* AntDiv Before Link
===============================================================*/
void
odm_sw_ant_div_reset_before_link(
struct dm_struct *dm
)
{
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
dm_swat_table->swas_no_link_state = 0;
}
#endif

33
hal/phydm/rtl8188e/phydm_rtl8188e.h Normal file
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@@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#if (RTL8188E_SUPPORT == 1)
void
odm_dig_lower_bound_88e(
struct dm_struct *dm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#define sw_ant_div_reset_before_link odm_sw_ant_div_reset_before_link
void odm_sw_ant_div_reset_before_link(struct dm_struct *dm);
#endif
#endif
#endif

24
hal/phydm/rtl8188e/version_rtl8188e.h Normal file
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@@ -0,0 +1,24 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*RTL8188E PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8188E 20160517
#define COMMIT_BY_8188E "RF_Eason"
#define RELEASE_VERSION_8188E 70