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New upstream version 5.3.9~20191129

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This commit is contained in:
Sophie Brun
2019-12-17 17:14:15 +01:00
commit 64d530c26f
497 changed files with 379081 additions and 0 deletions
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118
hal/phydm/ap_makefile.mk Normal file
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_PHYDM_FILES :=\
phydm/phydm.o \
phydm/phydm_dig.o\
phydm/phydm_antdiv.o\
phydm/phydm_soml.o\
phydm/phydm_smt_ant.o\
phydm/phydm_pathdiv.o\
phydm/phydm_rainfo.o\
phydm/phydm_dynamictxpower.o\
phydm/phydm_adaptivity.o\
phydm/phydm_debug.o\
phydm/phydm_interface.o\
phydm/phydm_phystatus.o\
phydm/phydm_hwconfig.o\
phydm/phydm_dfs.o\
phydm/phydm_cfotracking.o\
phydm/phydm_adc_sampling.o\
phydm/phydm_ccx.o\
phydm/phydm_primary_cca.o\
phydm/phydm_cck_pd.o\
phydm/phydm_rssi_monitor.o\
phydm/phydm_auto_dbg.o\
phydm/phydm_math_lib.o\
phydm/phydm_noisemonitor.o\
phydm/phydm_api.o\
phydm/phydm_pow_train.o\
phydm/txbf/phydm_hal_txbf_api.o\
EdcaTurboCheck.o\
phydm/halrf/halrf.o\
phydm/halrf/halphyrf_ap.o\
phydm/halrf/halrf_powertracking_ap.o\
phydm/halrf/halrf_powertracking.o\
phydm/halrf/halrf_kfree.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8188e/halhwimg8188e_bb.o\
phydm/rtl8188e/halhwimg8188e_mac.o\
phydm/rtl8188e/halhwimg8188e_rf.o\
phydm/rtl8188e/phydm_regconfig8188e.o\
phydm/rtl8188e/hal8188erateadaptive.o\
phydm/rtl8188e/phydm_rtl8188e.o\
phydm/halrf/rtl8188e/halrf_8188e_ap.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
_PHYDM_FILES += \
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
phydm/rtl8192e/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
phydm/rtl8814a/halhwimg8814a_bb.o\
phydm/rtl8814a/halhwimg8814a_mac.o\
phydm/rtl8814a/halhwimg8814a_rf.o\
phydm/rtl8814a/phydm_regconfig8814a.o\
phydm/rtl8814a/phydm_rtl8814a.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/halhwimg8822b_rf.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8821c/halhwimg8821c_bb.o\
phydm/rtl8821c/halhwimg8821c_mac.o\
phydm/rtl8821c/halhwimg8821c_rf.o\
phydm/rtl8821c/phydm_regconfig8821c.o\
phydm/rtl8821c/phydm_hal_api8821c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
_PHYDM_FILES += efuse_97f/efuse.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197f/halhwimg8197f_bb.o\
phydm/rtl8197f/halhwimg8197f_mac.o\
phydm/rtl8197f/halhwimg8197f_rf.o\
phydm/rtl8197f/phydm_hal_api8197f.o\
phydm/rtl8197f/phydm_regconfig8197f.o\
phydm/rtl8197f/phydm_rtl8197f.o
endif
endif

137
hal/phydm/halhwimg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#pragma once
#ifndef __INC_HW_IMG_H
#define __INC_HW_IMG_H
/*
* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
* */
#if RT_PLATFORM == PLATFORM_LINUX
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 0
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 0
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 0
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 1
#define RTL8723S_HWIMG_SUPPORT 0
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#endif
#else /* PLATFORM_WINDOWS & MacOSX */
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 1
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 1
/* For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 1
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 1
#if defined(UNDER_CE)
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#else
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
#define RTL8723U_HWIMG_SUPPORT 1
/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
#define RTL8723S_HWIMG_SUPPORT 1
/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 1
#define RTL8188EU_HWIMG_SUPPORT 1
#define RTL8188ES_HWIMG_SUPPORT 1
#endif
#endif
#endif /* __INC_HW_IMG_H */

1305
hal/phydm/halrf/halphyrf_ap.c Normal file
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122
hal/phydm/halrf/halphyrf_ap.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#include "halrf/halrf_powertracking_ap.h"
#include "halrf/halrf_kfree.h"
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
/* refine by YuChen for 8814A */
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_all_swing get_delta_all_swing_table;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void
odm_txpowertracking_callback_thermal_meter(
void *dm_void
);
#if (RTL8192E_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_92e(
void *dm_void
);
#endif
#if (RTL8814A_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series2(
void *dm_void
);
#elif ODM_IC_11AC_SERIES_SUPPORT
void
odm_txpowertracking_callback_thermal_meter_jaguar_series(
void *dm_void
);
#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
void *dm_void
);
#endif
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /* #ifndef __HAL_PHY_RF_H__ */

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hal/phydm/halrf/halphyrf_ce.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
do {\
for (_offset = 0; _offset < _size; _offset++) { \
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
if (_offset != 0)\
_offset--;\
break;\
} \
} \
if (_offset >= _size)\
_offset = _size-1;\
} while (0)
void configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if RTL8192E_SUPPORT
if (dm->support_ic_type == ODM_RTL8192E)
configure_txpower_track_8192e(config);
#endif
#if RTL8821A_SUPPORT
if (dm->support_ic_type == ODM_RTL8821)
configure_txpower_track_8821a(config);
#endif
#if RTL8812A_SUPPORT
if (dm->support_ic_type == ODM_RTL8812)
configure_txpower_track_8812a(config);
#endif
#if RTL8188E_SUPPORT
if (dm->support_ic_type == ODM_RTL8188E)
configure_txpower_track_8188e(config);
#endif
#if RTL8723B_SUPPORT
if (dm->support_ic_type == ODM_RTL8723B)
configure_txpower_track_8723b(config);
#endif
#if RTL8814A_SUPPORT
if (dm->support_ic_type == ODM_RTL8814A)
configure_txpower_track_8814a(config);
#endif
#if RTL8703B_SUPPORT
if (dm->support_ic_type == ODM_RTL8703B)
configure_txpower_track_8703b(config);
#endif
#if RTL8188F_SUPPORT
if (dm->support_ic_type == ODM_RTL8188F)
configure_txpower_track_8188f(config);
#endif
#if RTL8723D_SUPPORT
if (dm->support_ic_type == ODM_RTL8723D)
configure_txpower_track_8723d(config);
#endif
/* JJ ADD 20161014 */
#if RTL8710B_SUPPORT
if (dm->support_ic_type == ODM_RTL8710B)
configure_txpower_track_8710b(config);
#endif
#if RTL8822B_SUPPORT
if (dm->support_ic_type == ODM_RTL8822B)
configure_txpower_track_8822b(config);
#endif
#if RTL8821C_SUPPORT
if (dm->support_ic_type == ODM_RTL8821C)
configure_txpower_track_8821c(config);
#endif
}
/* **********************************************************************
* <20121113, Kordan> This function should be called when tx_agc changed.
* Otherwise the previous compensation is gone, because we record the
* delta of temperature between two TxPowerTracking watch dogs.
*
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
* need to call this function.
* ********************************************************************** */
void
odm_clear_txpowertracking_state(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
#else
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(dm->adapter);
#endif
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
dm->rf_calibrate_info.CCK_index = 0;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->power_index_offset[p] = 0;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
cali_info->remnant_ofdm_swing_idx[p] = 0;
cali_info->kfree_offset[p] = 0;
}
cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
cali_info->remnant_cck_swing_idx = 0;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
#else
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
#endif
cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
}
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *dm_void
#else
void *adapter
#endif
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
void *adapter = dm->adapter;
#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
#endif
#endif
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
s8 diff_DPK[4] = {0};
u8 thermal_value_avg_count = 0;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
u8 power_tracking_type = 0; /* no specify type */
#else
u8 power_tracking_type = hal_data->rf_power_tracking_type;
#endif
u8 xtal_offset_eanble = 0;
s8 thermal_value_temp = 0;
struct txpwrtrack_cfg c = {0};
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
/*for 8814 add by Yu Chen*/
u8 *delta_swing_table_idx_tup_c = NULL;
u8 *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL;
u8 *delta_swing_table_idx_tdown_d = NULL;
/*for Xtal Offset by James.Tung*/
s8 *delta_swing_table_xtal_up = NULL;
s8 *delta_swing_table_xtal_down = NULL;
/* 4 2. Initilization ( 7 steps in total ) */
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
cali_info->is_txpowertracking_init = true;
/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
<Kordan> We should keep updating the control variable according to HalData.
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
cali_info->rega24 = 0x090e1317;
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (*(dm->mp_mode) == true)
cali_info->rega24 = 0x090e1317;
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n", cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
#endif
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
if (thermal_value_temp > 63)
thermal_value = 63;
else if (thermal_value_temp < 0)
thermal_value = 0;
else
thermal_value = thermal_value_temp;
/*add log by zhao he, check c80/c94/c14/ca0 value*/
if (dm->support_ic_type == ODM_RTL8723D) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8710B) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
if (!cali_info->txpowertrack_control)
return;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
if (rtlefu->eeprom_thermalmeter == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rtlefu->eeprom_thermalmeter);
return;
}
#else
if (hal_data->eeprom_thermal_meter == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
return;
}
#endif
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
if (cali_info->is_reloadtxpowerindex)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
/*4 4. Calculate average thermal meter*/
cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
cali_info->thermal_value_avg_index++;
if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg[i]) {
thermal_value_avg += cali_info->thermal_value_avg[i];
thermal_value_avg_count++;
}
}
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
cali_info->thermal_value_delta = thermal_value - rtlefu->eeprom_thermalmeter;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rtlefu->eeprom_thermalmeter);
#else
cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
#endif
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
cali_info->thermal_value_iqk = thermal_value;
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
}
for (p = RF_PATH_A; p < c.rf_path_count; p++)
diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
/*4 6. If necessary, do LCK.*/
if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
if (cali_info->thermal_value_lck == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
if (delta > 0 && cali_info->txpowertrack_control) {
/* "delta" here is used to record the absolute value of differrence. */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
delta = thermal_value > rtlefu->eeprom_thermalmeter ? (thermal_value - rtlefu->eeprom_thermalmeter) : (rtlefu->eeprom_thermalmeter - thermal_value);
#else
delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
#endif
#else
delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
#endif
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
if (thermal_value > rtlefu->eeprom_thermalmeter) {
#else
if (thermal_value > hal_data->eeprom_thermal_meter) {
#endif
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
#endif
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
}
} else {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
}
}
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset[p] = 0;
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
cali_info->bb_swing_idx_cck = cali_info->CCK_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
/*************Print BB Swing base and index Offset*************/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
/*4 7.1 Handle boundary conditions of index.*/
if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
else if (cali_info->OFDM_index[p] <= OFDM_min_index)
cali_info->OFDM_index[p] = OFDM_min_index;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"\n\n========================================================================================================\n");
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
cali_info->CCK_index = c.swing_table_size_cck - 1;
else if (cali_info->CCK_index <= 0)
cali_info->CCK_index = 0;
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->power_index_offset[p] = 0;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
if ((dm->support_ic_type & ODM_RTL8814A)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
if (power_tracking_type == 0) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (power_tracking_type == 1) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
} else if (power_tracking_type == 2) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
} else if (power_tracking_type == 3) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
}
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
cali_info->power_index_offset[RF_PATH_B] != 0 ||
cali_info->power_index_offset[RF_PATH_C] != 0 ||
cali_info->power_index_offset[RF_PATH_D] != 0) &&
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) {
#else
cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
#endif
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
/* */
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
/* to increase TX power. Otherwise, EVM will be bad. */
/* */
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
if (thermal_value > cali_info->thermal_value) {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
#endif
}
} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
#endif
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
if (thermal_value > rtlefu->eeprom_thermalmeter)
#else
if (thermal_value > hal_data->eeprom_thermal_meter)
#endif
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
#endif
{
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
#endif
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
} else {
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
#endif
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
}
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
}
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) {
#else
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
if (thermal_value > rtlefu->eeprom_thermalmeter) {
#else
if (thermal_value > hal_data->eeprom_thermal_meter) {
#endif
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
#endif
(*c.odm_txxtaltrack_set_xtal)(dm);
} else {
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
#else
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
#endif
(*c.odm_txxtaltrack_set_xtal)(dm);
}
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
/* Wait sacn to do IQK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
if (!cali_info->is_iqk_in_progress)
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
}
}
if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
cali_info->tx_powercount = 0;
}
/* 3============================================================
* 3 IQ Calibration
* 3============================================================ */
void
odm_reset_iqk_result(
void *dm_void
)
{
return;
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
{
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
};
u8 place = chnl;
if (chnl > 14) {
for (place = 14; place < sizeof(channel_all); place++) {
if (channel_all[place] == chnl)
return place - 13;
}
}
return 0;
}
#endif
void
odm_iq_calibrate(
struct dm_struct *dm
)
{
void *adapter = dm->adapter;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (*dm->is_fcs_mode_enable)
return;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
if (IS_HARDWARE_TYPE_8812AU(adapter))
return;
#endif
if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
dm->pre_channel = *dm->channel;
dm->linked_interval = 0;
}
if (dm->linked_interval < 3)
dm->linked_interval++;
if (dm->linked_interval == 2)
halrf_iqk_trigger(dm, false);
} else
dm->linked_interval = 0;
}
void phydm_rf_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_init(dm);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_clear_txpowertracking_state(dm);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814A)
phy_iq_calibrate_8814a_init(dm);
#endif
#endif
}
void phydm_rf_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_txpowertracking_check(dm);
/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/
/*odm_iq_calibrate(dm);*/
#endif
}

124
hal/phydm/halrf/halphyrf_ce.h Normal file
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@@ -0,0 +1,124 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#include "halrf/halrf_kfree.h"
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#include "halrf/halrf_powertracking_ce.h"
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
typedef void(*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void
odm_clear_txpowertracking_state(
void *dm_void
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void *dm_void
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void *dm
#else
void *adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /* #ifndef __HAL_PHY_RF_H__ */

817
hal/phydm/halrf/halphyrf_win.c Normal file
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@@ -0,0 +1,817 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
do {\
for (_offset = 0; _offset < _size; _offset++) { \
\
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
\
if (_offset != 0)\
_offset--;\
break;\
} \
} \
if (_offset >= _size)\
_offset = _size-1;\
} while (0)
void configure_txpower_track(
struct dm_struct *dm,
struct txpwrtrack_cfg *config
)
{
#if RTL8192E_SUPPORT
if (dm->support_ic_type == ODM_RTL8192E)
configure_txpower_track_8192e(config);
#endif
#if RTL8821A_SUPPORT
if (dm->support_ic_type == ODM_RTL8821)
configure_txpower_track_8821a(config);
#endif
#if RTL8812A_SUPPORT
if (dm->support_ic_type == ODM_RTL8812)
configure_txpower_track_8812a(config);
#endif
#if RTL8188E_SUPPORT
if (dm->support_ic_type == ODM_RTL8188E)
configure_txpower_track_8188e(config);
#endif
#if RTL8188F_SUPPORT
if (dm->support_ic_type == ODM_RTL8188F)
configure_txpower_track_8188f(config);
#endif
#if RTL8723B_SUPPORT
if (dm->support_ic_type == ODM_RTL8723B)
configure_txpower_track_8723b(config);
#endif
#if RTL8814A_SUPPORT
if (dm->support_ic_type == ODM_RTL8814A)
configure_txpower_track_8814a(config);
#endif
#if RTL8703B_SUPPORT
if (dm->support_ic_type == ODM_RTL8703B)
configure_txpower_track_8703b(config);
#endif
#if RTL8822B_SUPPORT
if (dm->support_ic_type == ODM_RTL8822B)
configure_txpower_track_8822b(config);
#endif
#if RTL8723D_SUPPORT
if (dm->support_ic_type == ODM_RTL8723D)
configure_txpower_track_8723d(config);
#endif
/* JJ ADD 20161014 */
#if RTL8710B_SUPPORT
if (dm->support_ic_type == ODM_RTL8710B)
configure_txpower_track_8710b(config);
#endif
#if RTL8821C_SUPPORT
if (dm->support_ic_type == ODM_RTL8821C)
configure_txpower_track_8821c(config);
#endif
}
/* **********************************************************************
* <20121113, Kordan> This function should be called when tx_agc changed.
* Otherwise the previous compensation is gone, because we record the
* delta of temperature between two TxPowerTracking watch dogs.
*
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
* need to call this function.
* ********************************************************************** */
void
odm_clear_txpowertracking_state(
struct dm_struct *dm
)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
cali_info->CCK_index = 0;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->power_index_offset[p] = 0;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
cali_info->remnant_ofdm_swing_idx[p] = 0;
cali_info->kfree_offset[p] = 0;
}
cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
cali_info->remnant_cck_swing_idx = 0;
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
}
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm
#else
void *adapter
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = &hal_data->DM_OutSrc;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct dm_struct *dm = &hal_data->odmpriv;
#endif
#endif
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
s8 diff_DPK[4] = {0};
u8 thermal_value_avg_count = 0;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
u8 power_tracking_type = hal_data->RfPowerTrackingType;
u8 xtal_offset_eanble = 0;
s8 thermal_value_temp = 0;
struct txpwrtrack_cfg c;
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
/*for 8814 add by Yu Chen*/
u8 *delta_swing_table_idx_tup_c = NULL;
u8 *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL;
u8 *delta_swing_table_idx_tdown_d = NULL;
/*for Xtal Offset by James.Tung*/
s8 *delta_swing_table_xtal_up = NULL;
s8 *delta_swing_table_xtal_down = NULL;
/* 4 2. Initilization ( 7 steps in total ) */
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
cali_info->is_txpowertracking_init = true;
/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
<Kordan> We should keep updating the control variable according to HalData.
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
cali_info->rega24 = 0x090e1317;
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (*(dm->mp_mode) == true)
cali_info->rega24 = 0x090e1317;
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
if (thermal_value_temp > 63)
thermal_value = 63;
else if (thermal_value_temp < 0)
thermal_value = 0;
else
thermal_value = thermal_value_temp;
/*add log by zhao he, check c80/c94/c14/ca0 value*/
if (dm->support_ic_type == ODM_RTL8723D) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8710B) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
if (!cali_info->txpowertrack_control)
return;
if (hal_data->eeprom_thermal_meter == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
return;
}
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
if (cali_info->is_reloadtxpowerindex)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
/*4 4. Calculate average thermal meter*/
cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
cali_info->thermal_value_avg_index++;
if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg[i]) {
thermal_value_avg += cali_info->thermal_value_avg[i];
thermal_value_avg_count++;
}
}
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
cali_info->thermal_value_iqk = thermal_value;
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
}
for (p = RF_PATH_A; p < c.rf_path_count; p++)
diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
/*4 6. If necessary, do LCK.*/
if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
if (cali_info->thermal_value_lck == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
}
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
if (delta > 0 && cali_info->txpowertrack_control) {
/* "delta" here is used to record the absolute value of differrence. */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
#else
delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
#endif
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (thermal_value > hal_data->eeprom_thermal_meter) {
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
#endif
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
if (cali_info->xtal_offset_last == cali_info->xtal_offset)
xtal_offset_eanble = 0;
else
xtal_offset_eanble = 1;
}
} else {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
if (cali_info->xtal_offset_last == cali_info->xtal_offset)
xtal_offset_eanble = 0;
else
xtal_offset_eanble = 1;
}
}
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset[p] = 0;
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
cali_info->bb_swing_idx_cck = cali_info->CCK_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
/*************Print BB Swing base and index Offset*************/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
/*4 7.1 Handle boundary conditions of index.*/
if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
else if (cali_info->OFDM_index[p] <= OFDM_min_index)
cali_info->OFDM_index[p] = OFDM_min_index;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"\n\n========================================================================================================\n");
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
cali_info->CCK_index = c.swing_table_size_cck - 1;
else if (cali_info->CCK_index <= 0)
cali_info->CCK_index = 0;
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->power_index_offset[p] = 0;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
if ((dm->support_ic_type & ODM_RTL8814A)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
if (power_tracking_type == 0) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (power_tracking_type == 1) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
} else if (power_tracking_type == 2) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
} else if (power_tracking_type == 3) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
}
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
cali_info->power_index_offset[RF_PATH_B] != 0 ||
cali_info->power_index_offset[RF_PATH_C] != 0 ||
cali_info->power_index_offset[RF_PATH_D] != 0) &&
cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
/* */
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
/* to increase TX power. Otherwise, EVM will be bad. */
/* */
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
if (thermal_value > cali_info->thermal_value) {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
}
} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (thermal_value > hal_data->eeprom_thermal_meter)
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
#endif
{
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
}
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
}
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (thermal_value > hal_data->eeprom_thermal_meter) {
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
(*c.odm_txxtaltrack_set_xtal)(dm);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
(*c.odm_txxtaltrack_set_xtal)(dm);
}
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
/* Wait sacn to do IQK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
if (!cali_info->is_iqk_in_progress)
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
}
}
if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
cali_info->tx_powercount = 0;
}
/* 3============================================================
* 3 IQ Calibration
* 3============================================================ */
void
odm_reset_iqk_result(
struct dm_struct *dm
)
{
return;
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
{
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
};
u8 place = chnl;
if (chnl > 14) {
for (place = 14; place < sizeof(channel_all); place++) {
if (channel_all[place] == chnl)
return place - 13;
}
}
return 0;
}
#endif
void
odm_iq_calibrate(
struct dm_struct *dm
)
{
void *adapter = dm->adapter;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (*dm->is_fcs_mode_enable)
return;
#endif
if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE"));
if (*dm->channel != dm->pre_channel) {
dm->pre_channel = *dm->channel;
dm->linked_interval = 0;
}
if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))
dm->linked_interval++;
if (dm->linked_interval == 2)
PHY_IQCalibrate((PADAPTER)adapter, false);
} else
dm->linked_interval = 0;
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE"));
}
void phydm_rf_init(struct dm_struct *dm)
{
odm_txpowertracking_init(dm);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_clear_txpowertracking_state(dm);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814A)
phy_iq_calibrate_8814a_init(dm);
#endif
#endif
}
void phydm_rf_watchdog(struct dm_struct *dm)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_txpowertracking_check(dm);
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_iq_calibrate(dm);
#endif
}

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hal/phydm/halrf/halphyrf_win.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#if (RTL8814A_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8814a/halrf_iqk_8814a.h"
#else
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#endif
#if (RTL8822B_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8822b/halrf_iqk_8822b.h"
#include "../../MAC/Halmac_type.h"
#else
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#include "../mac/Halmac_type.h"
#endif
#endif
#if RT_PLATFORM == PLATFORM_MACOSX
#include "halrf_powertracking_win.h"
#include "halrf_kfree.h"
#include "halrf_txgapcal.h"
#else
#include "halrf/halrf_powertracking_win.h"
#include "halrf/halrf_kfree.h"
#include "halrf/halrf_txgapcal.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8821c/halrf_iqk_8821c.h"
#else
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#endif
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void(*func_lck)(void *);
typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
typedef void (*func_set_xtal)(void *);
typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
func_all_swing get_delta_all_swing_table;
};
void
configure_txpower_track(
struct dm_struct *dm,
struct txpwrtrack_cfg *config
);
void
odm_clear_txpowertracking_state(
struct dm_struct *dm
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm
#else
void *adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
struct dm_struct *dm
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void odm_iq_calibrate(struct dm_struct *dm);
void phydm_rf_init(struct dm_struct *dm);
void phydm_rf_watchdog(struct dm_struct *dm);
#endif /* #ifndef __HAL_PHY_RF_H__ */

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hal/phydm/halrf/halrf.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_H__
#define _HALRF_H__
/*============================================================*/
/*include files*/
/*============================================================*/
#include "halrf/halrf_psd.h"
/*============================================================*/
/*Definition */
/*============================================================*/
/*IQK version*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#define IQK_VERSION_8188E "0x14"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
#define IQK_VERSION_8188E "0x01"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define IQK_VERSION_8188E "0x01"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#endif
#define IQK_VERSION_8814A "0x0f"
#define IQK_VERSION_8188F "0x01"
#define IQK_VERSION_8197F "0x01"
#define IQK_VERSION_8703B "0x05"
#define IQK_VERSION_8710B "0x01"
#define IQK_VERSION_8723D "0x02"
#define IQK_VERSION_8822B "0x2f"
#define IQK_VERSION_8821C "0x23"
/*LCK version*/
#define LCK_VERSION_8188E "0x01"
#define LCK_VERSION_8192E "0x01"
#define LCK_VERSION_8723B "0x01"
#define LCK_VERSION_8812A "0x01"
#define LCK_VERSION_8821A "0x01"
#define LCK_VERSION_8814A "0x01"
#define LCK_VERSION_8188F "0x01"
#define LCK_VERSION_8197F "0x01"
#define LCK_VERSION_8703B "0x01"
#define LCK_VERSION_8710B "0x01"
#define LCK_VERSION_8723D "0x01"
#define LCK_VERSION_8822B "0x01"
#define LCK_VERSION_8821C "0x01"
/*power tracking version*/
#define POWERTRACKING_VERSION_8188E "0x01"
#define POWERTRACKING_VERSION_8192E "0x01"
#define POWERTRACKING_VERSION_8723B "0x01"
#define POWERTRACKING_VERSION_8812A "0x01"
#define POWERTRACKING_VERSION_8821A "0x01"
#define POWERTRACKING_VERSION_8814A "0x01"
#define POWERTRACKING_VERSION_8188F "0x01"
#define POWERTRACKING_VERSION_8197F "0x01"
#define POWERTRACKING_VERSION_8703B "0x01"
#define POWERTRACKING_VERSION_8710B "0x01"
#define POWERTRACKING_VERSION_8723D "0x01"
#define POWERTRACKING_VERSION_8822B "0x01"
#define POWERTRACKING_VERSION_8821C "0x01"
/*DPK tracking version*/
#define DPK_VERSION_8188E "NONE"
#define DPK_VERSION_8192E "NONE"
#define DPK_VERSION_8723B "NONE"
#define DPK_VERSION_8812A "NONE"
#define DPK_VERSION_8821A "NONE"
#define DPK_VERSION_8814A "NONE"
#define DPK_VERSION_8188F "NONE"
#define DPK_VERSION_8197F "NONE"
#define DPK_VERSION_8703B "NONE"
#define DPK_VERSION_8710B "NONE"
#define DPK_VERSION_8723D "NONE"
#define DPK_VERSION_8822B "NONE"
#define DPK_VERSION_8821C "NONE"
/*Kfree tracking version*/
#define KFREE_VERSION_8188E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8192E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8723B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8812A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8821A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8814A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8188F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8197F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8703B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8710B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8723D (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8822B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8821C (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
/*PA Bias Calibration version*/
#define PABIASK_VERSION_8188E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8192E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8723B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8812A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8821A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8814A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8188F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8197F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8703B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8710B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8723D (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8822B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8821C (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define HALRF_IQK_VER (dm->support_ic_type == ODM_RTL8188E)? IQK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? IQK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? IQK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? IQK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? IQK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? IQK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? IQK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? IQK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? IQK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? IQK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? IQK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? IQK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? IQK_VERSION_8821C :"unknown"
#define HALRF_LCK_VER (dm->support_ic_type == ODM_RTL8188E)? LCK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? LCK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? LCK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? LCK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? LCK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? LCK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? LCK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? LCK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? LCK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? LCK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? LCK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? LCK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? LCK_VERSION_8821C :"unknown"
#define HALRF_POWRTRACKING_VER (dm->support_ic_type == ODM_RTL8188E)? POWERTRACKING_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? POWERTRACKING_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? POWERTRACKING_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? POWERTRACKING_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? POWERTRACKING_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? POWERTRACKING_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? POWERTRACKING_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? POWERTRACKING_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? POWERTRACKING_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? POWERTRACKING_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? POWERTRACKING_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? POWERTRACKING_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? POWERTRACKING_VERSION_8821C :"unknown"
#define HALRF_DPK_VER (dm->support_ic_type == ODM_RTL8188E)? DPK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? DPK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? DPK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? DPK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? DPK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? DPK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? DPK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? DPK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? DPK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? DPK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? DPK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? DPK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? DPK_VERSION_8821C :"unknown"
#define HALRF_KFREE_VER (dm->support_ic_type == ODM_RTL8188E)? KFREE_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? KFREE_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? KFREE_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? KFREE_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? KFREE_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? KFREE_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? KFREE_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? KFREE_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? KFREE_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? KFREE_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? KFREE_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? KFREE_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? KFREE_VERSION_8821C :"unknown"
#define HALRF_PABIASK_VER (dm->support_ic_type == ODM_RTL8188E)? PABIASK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? PABIASK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? PABIASK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? PABIASK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? PABIASK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? PABIASK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? PABIASK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? PABIASK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? PABIASK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? PABIASK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? PABIASK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? PABIASK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? PABIASK_VERSION_8821C :"unknown"
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
/*===========================================================*/
/*AGC RX High Power mode*/
/*===========================================================*/
#define lna_low_gain_1 0x64
#define lna_low_gain_2 0x5A
#define lna_low_gain_3 0x58
/*============================================================*/
/* enumeration */
/*============================================================*/
enum halrf_ability {
HAL_RF_TX_PWR_TRACK = BIT(0),
HAL_RF_IQK = BIT(1),
HAL_RF_LCK = BIT(2),
HAL_RF_DPK = BIT(3),
HAL_RF_TXGAPK = BIT(4)
};
enum halrf_cmninfo_init {
HALRF_CMNINFO_ABILITY = 0,
HALRF_CMNINFO_DPK_EN = 1,
HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
HALRF_CMNINFO_FW_VER,
HALRF_CMNINFO_RFK_FORBIDDEN,
HALRF_CMNINFO_IQK_SEGMENT,
HALRF_CMNINFO_RATE_INDEX,
HALRF_CMNINFO_MP_PSD_POINT,
HALRF_CMNINFO_MP_PSD_START_POINT,
HALRF_CMNINFO_MP_PSD_STOP_POINT,
HALRF_CMNINFO_MP_PSD_AVERAGE
};
enum halrf_cmninfo_hook {
HALRF_CMNINFO_CON_TX,
HALRF_CMNINFO_SINGLE_TONE,
HALRF_CMNINFO_CARRIER_SUPPRESSION,
HALRF_CMNINFO_MP_RATE_INDEX
};
enum phydm_lna_set {
phydm_lna_disable = 0,
phydm_lna_enable = 1,
};
/*============================================================*/
/* structure */
/*============================================================*/
struct _hal_rf_ {
/*hook*/
u8 *test1;
/*update*/
u32 rf_supportability;
u8 eeprom_thermal;
u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
boolean dpk_done;
u32 fw_ver;
boolean *is_con_tx;
boolean *is_single_tone;
boolean *is_carrier_suppresion;
u8 *mp_rate_index;
u32 p_rate_index;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data halrf_psd_data;
#endif
};
/*============================================================*/
/* function prototype */
/*============================================================*/
void halrf_basic_profile(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
void halrf_iqk_info_dump(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
);
void
halrf_iqk_hwtx_check(
void *dm_void,
boolean is_check
);
#endif
u8
halrf_match_iqk_version(
void *dm_void
);
void
halrf_support_ability_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len
);
void
halrf_cmn_info_init(
void *dm_void,
enum halrf_cmninfo_init cmn_info,
u32 value
);
void
halrf_cmn_info_hook(
void *dm_void,
u32 cmn_info,
void *value
);
void
halrf_cmn_info_set(
void *dm_void,
u32 cmn_info,
u64 value
);
u64
halrf_cmn_info_get(
void *dm_void,
u32 cmn_info
);
void
halrf_watchdog(
void *dm_void
);
void
halrf_supportability_init(
void *dm_void
);
void
halrf_init(
void *dm_void
);
void
halrf_iqk_trigger(
void *dm_void,
boolean is_recovery
);
void
halrf_segment_iqk_trigger(
void *dm_void,
boolean clear,
boolean segment_iqk
);
void
halrf_lck_trigger(
void *dm_void
);
void
halrf_iqk_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_get_iqk_cfir(
void *dm_void,
u8 idx,
u8 path,
boolean debug
);
void
halrf_iqk_xym_read(
void *dm_void,
u8 path,
u8 xym_type
);
void
halrf_rf_lna_setting(
void *dm_void,
enum phydm_lna_set type
);
void
halrf_do_imr_test(
void *dm_void,
u8 data
);
u32
halrf_psd_log2base(
u32 val
);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
void halrf_iqk_dbg(void *dm_void);
#endif
#endif

43
hal/phydm/halrf/halrf_features.h Normal file
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@@ -0,0 +1,43 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_FEATURES_H__
#define __HALRF_FEATURES
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define CONFIG_HALRF_POWERTRACKING 1
#endif
#endif

85
hal/phydm/halrf/halrf_iqk.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMIQK_H__
#define __PHYDMIQK_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOK_delay 1
#define WBIQK_delay 10
#define TX_IQK 0
#define RX_IQK 1
#define TXIQK 0
#define RXIQK1 1
#define RXIQK2 2
#define kcount_limit_80m 2
#define kcount_limit_others 4
#define rxiqk_gs_limit 10
#define NUM 4
/*---------------------------End Define Parameters-------------------------------*/
struct dm_iqk_info {
boolean lok_fail[NUM];
boolean iqk_fail[2][NUM];
u32 iqc_matrix[2][NUM];
u8 iqk_times;
u32 rf_reg18;
u32 lna_idx;
u8 rxiqk_step;
u8 tmp1bcc;
u8 kcount;
u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
boolean rfk_forbidden;
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
u32 iqk_channel[2];
boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
u32 iqk_cfir_real[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ /*channel index = 2 is just for debug*/
u32 iqk_cfir_imag[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ /*channel index = 2 is just for debug*/
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
u8 rxiqk_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
u32 lok_idac[2][4]; /*channel / path*/
u16 rxiqk_agc[2][4]; /*channel / path*/
u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
u32 txgap_result[8]; /*txagpK result */
u32 tmp_gntwl;
boolean is_btg;
boolean isbnd;
boolean is_reload;
boolean segment_iqk;
boolean is_hwtx;
boolean xym_read;
boolean trximr_enable;
u32 rx_xym[2][10];
u32 tx_xym[2][10];
u32 gs1_xym[2][6];
u32 gs2_xym[2][6];
u32 rxk1_xym[2][6];
#endif
};
#endif

883
hal/phydm/halrf/halrf_kfree.c Normal file
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@@ -0,0 +1,883 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*============================================================*/
/*include files*/
/*============================================================*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
/*This is a phydm API*/
void
phydm_set_kfree_to_rf_8814a(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
boolean is_odd;
if ((data % 2) != 0) { /*odd->positive*/
data = data - 1;
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
is_odd = true;
} else { /*even->negative*/
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
is_odd = false;
}
PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd);
switch (data) {
case 0:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
cali_info->kfree_offset[e_rf_path] = 0;
break;
case 2:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
cali_info->kfree_offset[e_rf_path] = 0;
break;
case 4:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
cali_info->kfree_offset[e_rf_path] = 1;
break;
case 6:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
cali_info->kfree_offset[e_rf_path] = 1;
break;
case 8:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
cali_info->kfree_offset[e_rf_path] = 2;
break;
case 10:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
cali_info->kfree_offset[e_rf_path] = 2;
break;
case 12:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
cali_info->kfree_offset[e_rf_path] = 3;
break;
case 14:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
cali_info->kfree_offset[e_rf_path] = 3;
break;
case 16:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
cali_info->kfree_offset[e_rf_path] = 4;
break;
case 18:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
cali_info->kfree_offset[e_rf_path] = 4;
break;
case 20:
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5);
cali_info->kfree_offset[e_rf_path] = 5;
break;
default:
break;
}
if (is_odd == false) {
/*that means Kfree offset is negative, we need to record it.*/
cali_info->kfree_offset[e_rf_path] = (-1) * cali_info->kfree_offset[e_rf_path];
PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]);
} else
PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]);
}
//
//
//
void
phydm_get_thermal_trim_offset_8821c(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
u8 pg_therm = 0xff;
odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false);
if (pg_therm != 0xff) {
pg_therm = pg_therm & 0x1f;
if ((pg_therm & BIT(0)) == 0)
power_trim_info->thermal = (-1 * (pg_therm >> 1));
else
power_trim_info->thermal = (pg_therm >> 1);
power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
}
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal trim flag:0x%02x\n", power_trim_info->flag);
if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal:%d\n", power_trim_info->thermal);
}
void
phydm_get_power_trim_offset_8821c(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
u8 pg_power = 0xff, i;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET_8821C, &pg_power, false);
if (pg_power != 0xff) {
power_trim_info->bb_gain[0][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false);
power_trim_info->bb_gain[1][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false);
power_trim_info->bb_gain[2][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false);
power_trim_info->bb_gain[3][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false);
power_trim_info->bb_gain[4][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false);
power_trim_info->bb_gain[5][0] = pg_power;
power_trim_info->flag = power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
}
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power trim flag:0x%02x\n", power_trim_info->flag);
if (power_trim_info->flag & KFREE_FLAG_ON) {
for (i = 0; i < KFREE_BAND_NUM; i++)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power_trim_data->bb_gain[%d][0]=0x%X\n", i, power_trim_info->bb_gain[i][0]);
}
}
void
phydm_set_kfree_to_rf_8821c(
void *dm_void,
u8 e_rf_path,
boolean wlg_btg,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 wlg, btg;
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1);
odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1);
if (wlg_btg == true) {
wlg = data & 0xf;
btg = (data & 0xf0) >> 4;
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1));
odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (btg & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1));
} else {
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
}
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)))
);
}
void
phydm_clear_kfree_to_rf_8821c(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1);
odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1));
odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1));
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 0);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 0);
odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 0);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)))
);
}
void
phydm_get_thermal_trim_offset_8822b(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
u8 pg_therm = 0xff;
#if 0
u32 thermal_trim_enable = 0xff;
odm_efuse_logical_map_read(dm, 1, 0xc8, &thermal_trim_enable);
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", thermal_trim_enable);
thermal_trim_enable = (thermal_trim_enable & BIT(5)) >> 5;
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim Enable:%d\n", thermal_trim_enable);
if ((cali_info->reg_rf_kfree_enable == 0 && thermal_trim_enable == 1) ||
cali_info->reg_rf_kfree_enable == 1) {
#endif
odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET, &pg_therm, false);
if (pg_therm != 0xff) {
pg_therm = pg_therm & 0x1f;
if ((pg_therm & BIT(0)) == 0)
power_trim_info->thermal = (-1 * (pg_therm >> 1));
else
power_trim_info->thermal = (pg_therm >> 1);
power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
}
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim flag:0x%02x\n", power_trim_info->flag);
if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal:%d\n", power_trim_info->thermal);
#if 0
} else
return;
#endif
}
void
phydm_get_power_trim_offset_8822b(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 pg_power = 0xff, i, j;
#if 0
u32 power_trim_enable = 0xff;
odm_efuse_logical_map_read(dm, 1, 0xc8, &power_trim_enable);
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", power_trim_enable);
power_trim_enable = (power_trim_enable & BIT(4)) >> 4;
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim Enable:%d\n", power_trim_enable);
if ((cali_info->reg_rf_kfree_enable == 0 && power_trim_enable == 1) ||
cali_info->reg_rf_kfree_enable == 1) {
#endif
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
if (pg_power != 0xff) {
/*Path A*/
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
/*Path B*/
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
power_trim_info->flag |= KFREE_FLAG_ON_2G;
power_trim_info->flag |= KFREE_FLAG_ON;
}
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false);
if (pg_power != 0xff) {
/*Path A*/
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false);
power_trim_info->bb_gain[1][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET, &pg_power, false);
power_trim_info->bb_gain[2][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET, &pg_power, false);
power_trim_info->bb_gain[3][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET, &pg_power, false);
power_trim_info->bb_gain[4][0] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET, &pg_power, false);
power_trim_info->bb_gain[5][0] = pg_power;
/*Path B*/
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[1][1] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[2][1] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[3][1] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[4][1] = pg_power;
odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXB_OFFSET, &pg_power, false);
power_trim_info->bb_gain[5][1] = pg_power;
power_trim_info->flag |= KFREE_FLAG_ON_5G;
power_trim_info->flag |= KFREE_FLAG_ON;
}
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim flag:0x%02x\n", power_trim_info->flag);
if (!(power_trim_info->flag & KFREE_FLAG_ON))
return;
for (i = 0; i < KFREE_BAND_NUM; i++) {
for (j = 0; j < 2; j++)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]);
}
#if 0
} else
return;
#endif
}
void
phydm_set_pa_bias_to_rf_8822b(
void *dm_void,
u8 e_rf_path,
s8 tx_pa_bias
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, 0x51, RFREGOFFSETMASK);
rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, 0x52, RFREGOFFSETMASK);
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
rf_reg_51, rf_reg_52, e_rf_path);
/*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
/*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
(((rf_reg_52 & 0x18000) >> 15) << 3) |
((rf_reg_52 & 0xf) << 5) |
(((rf_reg_51 & 0x78) >> 3) << 9) |
(((rf_reg_52 & 0x2000) >> 13) << 13);
PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g original tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n",
tx_pa_bias, rf_reg_3f, e_rf_path);
tx_pa_bias = (s8)((rf_reg_3f & (BIT(12) | BIT(11) | BIT(10) | BIT(9))) >> 9) + tx_pa_bias;
if (tx_pa_bias < 0)
tx_pa_bias = 0;
else if (tx_pa_bias > 7)
tx_pa_bias = 7;
rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g offset efuse 0x3d5 0x3d6 tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n",
tx_pa_bias, rf_reg_3f, e_rf_path);
odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x1);
odm_set_rf_reg(dm, e_rf_path, 0x33, RFREGOFFSETMASK, 0x0);
odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(0), 0x1);
odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(1), 0x1);
odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
odm_set_rf_reg(dm, e_rf_path, 0x33, (BIT(1) | BIT(0)), 0x3);
odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x0);
PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
odm_get_rf_reg(dm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9))), e_rf_path);
}
void
phydm_get_pa_bias_offset_8822b(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
u8 pg_pa_bias = 0xff, e_rf_path = 0;
s8 tx_pa_bias[2] = {0};
odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false);
if (pg_pa_bias != 0xff) {
/*paht a*/
odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false);
pg_pa_bias = pg_pa_bias & 0xf;
if ((pg_pa_bias & BIT(0)) == 0)
tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
else
tx_pa_bias[0] = (pg_pa_bias >> 1);
/*paht b*/
odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXB_OFFSET, &pg_pa_bias, false);
pg_pa_bias = pg_pa_bias & 0xf;
if ((pg_pa_bias & BIT(0)) == 0)
tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
else
tx_pa_bias[1] = (pg_pa_bias >> 1);
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx_patha_pa_bias:%d tx_pathb_pa_bias:%d\n", tx_pa_bias[0], tx_pa_bias[1]);
for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path, tx_pa_bias[e_rf_path]);
power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
}
else
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
}
void
phydm_set_kfree_to_rf_8822b(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
e_rf_path
);
}
void
phydm_clear_kfree_to_rf_8822b(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0);
odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 0);
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(7), 0);
PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
e_rf_path
);
}
void
phydm_get_thermal_trim_offset_8710b(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data);
u8 pg_therm = 0xff;
odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
if (pg_therm != 0xff) {
pg_therm = pg_therm & 0x1f;
if ((pg_therm & BIT(0)) == 0)
power_trim_info->thermal = (-1 * (pg_therm >> 1));
else
power_trim_info->thermal = (pg_therm >> 1);
power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
}
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal trim flag:0x%02x\n", power_trim_info->flag));
if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal:%d\n", power_trim_info->thermal));
}
void
phydm_get_power_trim_offset_8710b(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data);
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 pg_power = 0xff;
odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
if (pg_power != 0xff) {
/*Path A*/
odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
power_trim_info->flag |= KFREE_FLAG_ON_2G;
power_trim_info->flag |= KFREE_FLAG_ON;
}
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power trim flag:0x%02x\n", power_trim_info->flag));
if (power_trim_info->flag & KFREE_FLAG_ON)
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0]));
}
void
phydm_set_kfree_to_rf_8710b(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15)), ((data & 0xf) >> 1));
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD,
("[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
e_rf_path
));
}
void
phydm_clear_kfree_to_rf_8710b(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD,
("[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
e_rf_path
));
}
void
phydm_set_kfree_to_rf(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_RTL8814A)
phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
if ((dm->support_ic_type & ODM_RTL8821C) && (*dm->band_type == ODM_BAND_2_4G))
phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
else if (dm->support_ic_type & ODM_RTL8821C)
phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
if (dm->support_ic_type & ODM_RTL8822B)
phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
if (dm->support_ic_type & ODM_RTL8710B)
phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
}
void
phydm_clear_kfree_to_rf(
void *dm_void,
u8 e_rf_path,
u8 data
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_RTL8822B)
phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
if (dm->support_ic_type & ODM_RTL8821C)
phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
if (dm->support_ic_type & ODM_RTL8710B)
phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
}
void
phydm_get_thermal_trim_offset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
#endif
if (dm->support_ic_type & ODM_RTL8821C)
phydm_get_thermal_trim_offset_8821c(dm_void);
else if (dm->support_ic_type & ODM_RTL8822B)
phydm_get_thermal_trim_offset_8822b(dm_void);
else if (dm->support_ic_type & ODM_RTL8710B)
phydm_get_thermal_trim_offset_8710b(dm_void);
}
void
phydm_get_power_trim_offset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN) // 2017 MH DM Should use the same code.s
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
#endif
if (dm->support_ic_type & ODM_RTL8821C)
phydm_get_power_trim_offset_8821c(dm_void);
else if (dm->support_ic_type & ODM_RTL8822B)
phydm_get_power_trim_offset_8822b(dm_void);
else if (dm->support_ic_type & ODM_RTL8710B)
phydm_get_power_trim_offset_8710b(dm_void);
}
void
phydm_get_pa_bias_offset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
#endif
if (dm->support_ic_type & ODM_RTL8822B)
phydm_get_pa_bias_offset_8822b(dm_void);
}
s8
phydm_get_thermal_offset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
return power_trim_info->thermal;
else
return 0;
}
void
phydm_config_kfree(
void *dm_void,
u8 channel_to_sw
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
u8 rfpath = 0, max_rf_path = 0;
u8 channel_idx = 0, i, j;
if (dm->support_ic_type & ODM_RTL8814A)
max_rf_path = 4; /*0~3*/
else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
max_rf_path = 2; /*0~1*/
else if (dm->support_ic_type & (ODM_RTL8821C| ODM_RTL8710B))
max_rf_path = 1;
PHYDM_DBG(dm, ODM_COMP_MP, "===>[kfree] phy_ConfigKFree()\n");
if (cali_info->reg_rf_kfree_enable == 2) {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n");
return;
} else if (cali_info->reg_rf_kfree_enable == 1 || cali_info->reg_rf_kfree_enable == 0) {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n");
/*Make sure the targetval is defined*/
if (!(power_trim_info->flag & KFREE_FLAG_ON)) {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n");
return;
}
/*if kfree_table[0] == 0xff, means no Kfree*/
if (dm->support_ic_type &ODM_RTL8710B)
ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0]));
else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B |ODM_RTL8821C | ODM_RTL8814A)){
for (i = 0; i < KFREE_BAND_NUM; i++) {
for (j = 0; j < max_rf_path; j++)
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]);
}
}
if (*dm->band_type == ODM_BAND_2_4G && power_trim_info->flag & KFREE_FLAG_ON_2G) {
if (channel_to_sw >= 1 && channel_to_sw <= 14)
channel_idx = PHYDM_2G;
for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
}
} else if (*dm->band_type == ODM_BAND_5G && power_trim_info->flag & KFREE_FLAG_ON_5G) {
if (channel_to_sw >= 36 && channel_to_sw <= 48)
channel_idx = PHYDM_5GLB1;
if (channel_to_sw >= 52 && channel_to_sw <= 64)
channel_idx = PHYDM_5GLB2;
if (channel_to_sw >= 100 && channel_to_sw <= 120)
channel_idx = PHYDM_5GMB1;
if (channel_to_sw >= 122 && channel_to_sw <= 144)
channel_idx = PHYDM_5GMB2;
if (channel_to_sw >= 149 && channel_to_sw <= 177)
channel_idx = PHYDM_5GHB;
for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
}
} else {
PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] Set default Register\n");
for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++)
phydm_clear_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
}
}
PHYDM_DBG(dm, ODM_COMP_MP, "<===[kfree] phy_ConfigKFree()\n");
}

142
hal/phydm/halrf/halrf_kfree.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMKFREE_H__
#define __PHYDKFREE_H__
#define KFREE_VERSION "1.0"
#define KFREE_BAND_NUM 6
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
#define BB_GAIN_NUM 6
#endif
#define KFREE_FLAG_ON BIT(0)
#define KFREE_FLAG_THERMAL_K_ON BIT(1)
#define KFREE_FLAG_ON_2G BIT(2)
#define KFREE_FLAG_ON_5G BIT(3)
#define PA_BIAS_FLAG_ON BIT(4)
#define PPG_THERMAL_OFFSET_8821C 0x1EF
#define PPG_BB_GAIN_2G_TXAB_OFFSET_8821C 0x1EE
#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC
#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C 0x1E8
#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C 0x1E4
#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C 0x1E0
#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C 0x1DC
#define PPG_THERMAL_OFFSET 0x3EF
#define PPG_BB_GAIN_2G_TXAB_OFFSET 0x3EE
#define PPG_BB_GAIN_2G_TXCD_OFFSET 0x3ED
#define PPG_BB_GAIN_5GL1_TXA_OFFSET 0x3EC
#define PPG_BB_GAIN_5GL1_TXB_OFFSET 0x3EB
#define PPG_BB_GAIN_5GL1_TXC_OFFSET 0x3EA
#define PPG_BB_GAIN_5GL1_TXD_OFFSET 0x3E9
#define PPG_BB_GAIN_5GL2_TXA_OFFSET 0x3E8
#define PPG_BB_GAIN_5GL2_TXB_OFFSET 0x3E7
#define PPG_BB_GAIN_5GL2_TXC_OFFSET 0x3E6
#define PPG_BB_GAIN_5GL2_TXD_OFFSET 0x3E5
#define PPG_BB_GAIN_5GM1_TXA_OFFSET 0x3E4
#define PPG_BB_GAIN_5GM1_TXB_OFFSET 0x3E3
#define PPG_BB_GAIN_5GM1_TXC_OFFSET 0x3E2
#define PPG_BB_GAIN_5GM1_TXD_OFFSET 0x3E1
#define PPG_BB_GAIN_5GM2_TXA_OFFSET 0x3E0
#define PPG_BB_GAIN_5GM2_TXB_OFFSET 0x3DF
#define PPG_BB_GAIN_5GM2_TXC_OFFSET 0x3DE
#define PPG_BB_GAIN_5GM2_TXD_OFFSET 0x3DD
#define PPG_BB_GAIN_5GH1_TXA_OFFSET 0x3DC
#define PPG_BB_GAIN_5GH1_TXB_OFFSET 0x3DB
#define PPG_BB_GAIN_5GH1_TXC_OFFSET 0x3DA
#define PPG_BB_GAIN_5GH1_TXD_OFFSET 0x3D9
#define PPG_PA_BIAS_2G_TXA_OFFSET 0x3D5
#define PPG_PA_BIAS_2G_TXB_OFFSET 0x3D6
struct odm_power_trim_data {
u8 flag;
u8 pa_bias_flag;
s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
s8 thermal;
};
enum phydm_kfree_channeltosw {
PHYDM_2G = 0,
PHYDM_5GLB1 = 1,
PHYDM_5GLB2 = 2,
PHYDM_5GMB1 = 3,
PHYDM_5GMB2 = 4,
PHYDM_5GHB = 5,
};
void
phydm_get_thermal_trim_offset(
void *dm_void
);
void
phydm_get_power_trim_offset(
void *dm_void
);
void
phydm_get_pa_bias_offset(
void *dm_void
);
s8
phydm_get_thermal_offset(
void *dm_void
);
void
phydm_clear_kfree_to_rf(
void *dm_void,
u8 e_rf_path,
u8 data
);
void
phydm_config_kfree(
void *dm_void,
u8 channel_to_sw
);
#endif

159
hal/phydm/halrf/halrf_powertracking.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
boolean
odm_check_power_status(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
PADAPTER adapter = (PADAPTER)dm->adapter;
RT_RF_POWER_STATE rt_state;
MGNT_INFO *mgnt_info = &adapter->MgntInfo;
/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
if (mgnt_info->init_adpt_in_progress == true) {
PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return true, due to initadapter\n");
return true;
}
/* */
/* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
/* */
adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return false, due to %d/%d/%d\n",
adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state);
return false;
}
#endif
return true;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
halrf_update_pwr_track(
void *dm_void,
u8 rate
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
u8 path_idx = 0;
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
dm->tx_rate = rate;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
#if USE_WORKITEM
odm_schedule_work_item(&dm->ra_rpt_workitem);
#else
if (dm->support_ic_type == ODM_RTL8821) {
#if (RTL8821A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8812) {
for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
#if (RTL8812A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
#endif
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
#if (RTL8723B_SUPPORT == 1)
odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8192E) {
for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
#if (RTL8192E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
#endif
}
} else if (dm->support_ic_type == ODM_RTL8188E) {
#if (RTL8188E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
#endif
}
#endif
#else
odm_schedule_work_item(&dm->ra_rpt_workitem);
#endif
#endif
}
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
halrf_update_init_rate_work_item_callback(
void *context
)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
u8 p = 0;
if (dm->support_ic_type == ODM_RTL8821) {
odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
/**/
} else if (dm->support_ic_type == ODM_RTL8812) {
for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/
odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
/**/
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
/**/
} else if (dm->support_ic_type == ODM_RTL8192E) {
for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/
odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
/**/
}
} else if (dm->support_ic_type == ODM_RTL8188E) {
odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
/**/
}
}
#endif

50
hal/phydm/halrf/halrf_powertracking.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_POWER_TRACKING_H__
#define __HALRF_POWER_TRACKING_H__
boolean
odm_check_power_status(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
halrf_update_pwr_track(
void *dm_void,
u8 rate
);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
halrf_update_init_rate_work_item_callback(
void *context
);
#endif
#endif

1158
hal/phydm/halrf/halrf_powertracking_ap.c Normal file
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345
hal/phydm/halrf/halrf_powertracking_ap.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
#define ODM_IC_11AC_SERIES_SUPPORT 1
#else
#define ODM_IC_11AC_SERIES_SUPPORT 0
#endif
#else
#define ODM_IC_11AC_SERIES_SUPPORT 1
#endif
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 3
#define MAX_RF_PATH 4
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define AVG_THERMAL_NUM 8
#define iqk_matrix_reg_num 8
/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#if !defined(_OUTSRC_COEXIST)
#define OFDM_TABLE_SIZE_92D 43
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
/* #define OFDM_TABLE_SIZE_92E 54 */
/* #define CCK_TABLE_SIZE_92E 54 */
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
#endif
#define ODM_OFDM_TABLE_SIZE 37
#define ODM_CCK_TABLE_SIZE 33
/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
* extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
* extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
#ifdef CONFIG_WLAN_HAL_8192EE
#define OFDM_TABLE_SIZE_92E 54
#define CCK_TABLE_SIZE_92E 54
extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
#endif
#define OFDM_TABLE_SIZE_8812 43
#define AVG_THERMAL_NUM_8812 4
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
#elif(ODM_IC_11AC_SERIES_SUPPORT)
extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
#endif
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[1][iqk_matrix_reg_num];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
/* u8 is_txpowertracking; */
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_dpk_enable;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset;
s8 delta_power_index;
s8 delta_power_index_last;
boolean is_tx_power_changed;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u64 iqk_start_time;
u64 iqk_total_progressing_time;
u64 iqk_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
u32 tx_lok[2];
};
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
#endif

761
hal/phydm/halrf/halrf_powertracking_ce.c Normal file
View File

@@ -0,0 +1,761 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*============================================================ */
/* include files */
/*============================================================ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* ************************************************************
* Global var
* ************************************************************ */
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
0x7f8001fe, /* 0, +6.0dB */
0x788001e2, /* 1, +5.5dB */
0x71c001c7, /* 2, +5.0dB*/
0x6b8001ae, /* 3, +4.5dB*/
0x65400195, /* 4, +4.0dB*/
0x5fc0017f, /* 5, +3.5dB*/
0x5a400169, /* 6, +3.0dB*/
0x55400155, /* 7, +2.5dB*/
0x50800142, /* 8, +2.0dB*/
0x4c000130, /* 9, +1.5dB*/
0x47c0011f, /* 10, +1.0dB*/
0x43c0010f, /* 11, +0.5dB*/
0x40000100, /* 12, +0dB*/
0x3c8000f2, /* 13, -0.5dB*/
0x390000e4, /* 14, -1.0dB*/
0x35c000d7, /* 15, -1.5dB*/
0x32c000cb, /* 16, -2.0dB*/
0x300000c0, /* 17, -2.5dB*/
0x2d4000b5, /* 18, -3.0dB*/
0x2ac000ab, /* 19, -3.5dB*/
0x288000a2, /* 20, -4.0dB*/
0x26000098, /* 21, -4.5dB*/
0x24000090, /* 22, -5.0dB*/
0x22000088, /* 23, -5.5dB*/
0x20000080, /* 24, -6.0dB*/
0x1e400079, /* 25, -6.5dB*/
0x1c800072, /* 26, -7.0dB*/
0x1b00006c, /* 27. -7.5dB*/
0x19800066, /* 28, -8.0dB*/
0x18000060, /* 29, -8.5dB*/
0x16c0005b, /* 30, -9.0dB*/
0x15800056, /* 31, -9.5dB*/
0x14400051, /* 32, -10.0dB*/
0x1300004c, /* 33, -10.5dB*/
0x12000048, /* 34, -11.0dB*/
0x11000044, /* 35, -11.5dB*/
0x10000040, /* 36, -12.0dB*/
};
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
};
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
};
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
0x0b40002d, /* 0, -15.0dB */
0x0c000030, /* 1, -14.5dB*/
0x0cc00033, /* 2, -14.0dB*/
0x0d800036, /* 3, -13.5dB*/
0x0e400039, /* 4, -13.0dB */
0x0f00003c, /* 5, -12.5dB*/
0x10000040, /* 6, -12.0dB*/
0x11000044, /* 7, -11.5dB*/
0x12000048, /* 8, -11.0dB*/
0x1300004c, /* 9, -10.5dB*/
0x14400051, /* 10, -10.0dB*/
0x15800056, /* 11, -9.5dB*/
0x16c0005b, /* 12, -9.0dB*/
0x18000060, /* 13, -8.5dB*/
0x19800066, /* 14, -8.0dB*/
0x1b00006c, /* 15, -7.5dB*/
0x1c800072, /* 16, -7.0dB*/
0x1e400079, /* 17, -6.5dB*/
0x20000080, /* 18, -6.0dB*/
0x22000088, /* 19, -5.5dB*/
0x24000090, /* 20, -5.0dB*/
0x26000098, /* 21, -4.5dB*/
0x288000a2, /* 22, -4.0dB*/
0x2ac000ab, /* 23, -3.5dB*/
0x2d4000b5, /* 24, -3.0dB*/
0x300000c0, /* 25, -2.5dB*/
0x32c000cb, /* 26, -2.0dB*/
0x35c000d7, /* 27, -1.5dB*/
0x390000e4, /* 28, -1.0dB*/
0x3c8000f2, /* 29, -0.5dB*/
0x40000100, /* 30, +0dB*/
0x43c0010f, /* 31, +0.5dB*/
0x47c0011f, /* 32, +1.0dB*/
0x4c000130, /* 33, +1.5dB*/
0x50800142, /* 34, +2.0dB*/
0x55400155, /* 35, +2.5dB*/
0x5a400169, /* 36, +3.0dB*/
0x5fc0017f, /* 37, +3.5dB*/
0x65400195, /* 38, +4.0dB*/
0x6b8001ae, /* 39, +4.5dB*/
0x71c001c7, /* 40, +5.0dB*/
0x788001e2, /* 41, +5.5dB*/
0x7f8001fe /* 42, +6.0dB*/
};
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
};
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
};
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
/* JJ ADD 20161014 */
u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB*/
0x088, /* 1, -11.5dB*/
0x090, /* 2, -11.0dB*/
0x099, /* 3, -10.5dB*/
0x0A2, /* 4, -10.0dB*/
0x0AC, /* 5, -9.5dB*/
0x0B6, /* 6, -9.0dB*/
0x0C0, /*7, -8.5dB*/
0x0CC, /* 8, -8.0dB*/
0x0D8, /* 9, -7.5dB*/
0x0E5, /* 10, -7.0dB*/
0x0F2, /* 11, -6.5dB*/
0x101, /* 12, -6.0dB*/
0x110, /* 13, -5.5dB*/
0x120, /* 14, -5.0dB*/
0x131, /* 15, -4.5dB*/
0x143, /* 16, -4.0dB*/
0x156, /* 17, -3.5dB*/
0x16A, /* 18, -3.0dB*/
0x180, /* 19, -2.5dB*/
0x197, /* 20, -2.0dB*/
0x1AF, /* 21, -1.5dB*/
0x1C8, /* 22, -1.0dB*/
0x1E3, /* 23, -0.5dB*/
0x200, /* 24, +0 dB*/
0x21E, /* 25, +0.5dB*/
0x23E, /* 26, +1.0dB*/
0x261, /* 27, +1.5dB*/
0x285,/* 28, +2.0dB*/
0x2AB, /* 29, +2.5dB*/
0x2D3, /*30, +3.0dB*/
0x2FE, /* 31, +3.5dB*/
0x32B, /* 32, +4.0dB*/
0x35C, /* 33, +4.5dB*/
0x38E, /* 34, +5.0dB*/
0x3C4, /* 35, +5.5dB*/
0x3FE /* 36, +6.0dB */
};
void
odm_txpowertracking_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
return;
#endif
odm_txpowertracking_thermal_meter_init(dm);
}
u8
get_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
#endif
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B
|| dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B
) {
bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
swing_table = ofdm_swing_table_new;
swing_table_size = OFDM_TABLE_SIZE;
} else {
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
if (dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8821) {
bb_swing = phy_get_tx_bb_swing_8812a(adapter, hal_data->current_band_type, RF_PATH_A);
swing_table = tx_scaling_table_jaguar;
swing_table_size = TXSCALE_TABLE_SIZE;
} else
#endif
{
bb_swing = 0;
swing_table = ofdm_swing_table;
swing_table_size = OFDM_TABLE_SIZE;
}
}
for (i = 0; i < swing_table_size; ++i) {
u32 table_value = swing_table[i];
if (table_value >= 0x100000)
table_value >>= 22;
if (bb_swing == table_value)
break;
}
return i;
}
u8
get_cck_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_cck_swing;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
break;
}
} else if (dm->support_ic_type == ODM_RTL8703B) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
}
return i;
}
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 default_swing_index = get_swing_index(dm);
u8 default_cck_swing_index = get_cck_swing_index(dm);
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
if (*dm->mp_mode == false)
hal_data->txpowertrack_control = true;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
#else
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
#endif
cali_info->is_txpowertracking = true;
cali_info->tx_powercount = 0;
cali_info->is_txpowertracking_init = false;
if (*dm->mp_mode == false)
cali_info->txpowertrack_control = true;
else
cali_info->txpowertrack_control = false;
if (*dm->mp_mode == false)
cali_info->txpowertrack_control = true;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#ifdef RTL8188E_SUPPORT
{
cali_info->is_txpowertracking = true;
cali_info->tx_powercount = 0;
cali_info->is_txpowertracking_init = false;
cali_info->txpowertrack_control = true;
}
#endif
#endif
/* dm->rf_calibrate_info.txpowertrack_control = true; */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
cali_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter;
cali_info->thermal_value_lck = rtlefu->eeprom_thermalmeter;
#else
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter;
#endif
if (cali_info->default_bb_swing_index_flag != true) {
/*The index of "0 dB" in SwingTable.*/
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
} else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 20; /*CCK:-6dB*/
} else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
} else if (dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
} else {
cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
cali_info->default_cck_index = 24;
}
cali_info->default_bb_swing_index_flag = true;
}
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->CCK_index = cali_info->default_cck_index;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->power_index_offset[p] = 0;
}
cali_info->modify_tx_agc_value_ofdm = 0;
cali_info->modify_tx_agc_value_cck = 0;
cali_info->tm_trigger = 0;
}
void
odm_txpowertracking_check(
void *dm_void
)
{
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
at the same time. In the stage2/3, we need to prive universal interface and merge all
HW dynamic mechanism. */
struct dm_struct *dm = (struct dm_struct *)dm_void;
switch (dm->support_platform) {
case ODM_WIN:
odm_txpowertracking_check_mp(dm);
break;
case ODM_CE:
odm_txpowertracking_check_ce(dm);
break;
case ODM_AP:
odm_txpowertracking_check_ap(dm);
break;
default:
break;
}
}
void
odm_txpowertracking_check_ce(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *adapter = dm->adapter;
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
if (!dm->rf_calibrate_info.tm_trigger) {
if (dm->support_ic_type &
(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B))
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
else
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
dm->rf_calibrate_info.tm_trigger = 1;
return;
} else {
odm_txpowertracking_callback_thermal_meter(dm);
dm->rf_calibrate_info.tm_trigger = 0;
}
#endif
}
void
odm_txpowertracking_check_mp(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
if (odm_check_power_status(adapter) == false) {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
return;
}
odm_txpowertracking_thermal_meter_check(adapter);
#endif
}
void
odm_txpowertracking_check_ap(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rtl8192cd_priv *priv = dm->priv;
return;
#endif
}

348
hal/phydm/halrf/halrf_powertracking_ce.h Normal file
View File

@@ -0,0 +1,348 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define iqk_matrix_reg_num 8
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#endif
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
#endif
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* <James> IQK time measurement */
u64 iqk_start_time;
u64 iqk_progressing_time;
u64 iqk_total_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
#endif

806
hal/phydm/halrf/halrf_powertracking_win.c Normal file
View File

@@ -0,0 +1,806 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*============================================================ */
/* include files */
/*============================================================ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* ************************************************************
* Global var
* ************************************************************ */
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
0x7f8001fe, /* 0, +6.0dB */
0x788001e2, /* 1, +5.5dB */
0x71c001c7, /* 2, +5.0dB */
0x6b8001ae, /* 3, +4.5dB */
0x65400195, /* 4, +4.0dB */
0x5fc0017f, /* 5, +3.5dB */
0x5a400169, /* 6, +3.0dB */
0x55400155, /* 7, +2.5dB */
0x50800142, /* 8, +2.0dB */
0x4c000130, /* 9, +1.5dB */
0x47c0011f, /* 10, +1.0dB */
0x43c0010f, /* 11, +0.5dB */
0x40000100, /* 12, +0dB */
0x3c8000f2, /* 13, -0.5dB */
0x390000e4, /* 14, -1.0dB */
0x35c000d7, /* 15, -1.5dB */
0x32c000cb, /* 16, -2.0dB */
0x300000c0, /* 17, -2.5dB */
0x2d4000b5, /* 18, -3.0dB */
0x2ac000ab, /* 19, -3.5dB */
0x288000a2, /* 20, -4.0dB */
0x26000098, /* 21, -4.5dB */
0x24000090, /* 22, -5.0dB */
0x22000088, /* 23, -5.5dB */
0x20000080, /* 24, -6.0dB */
0x1e400079, /* 25, -6.5dB */
0x1c800072, /* 26, -7.0dB */
0x1b00006c, /* 27. -7.5dB */
0x19800066, /* 28, -8.0dB */
0x18000060, /* 29, -8.5dB */
0x16c0005b, /* 30, -9.0dB */
0x15800056, /* 31, -9.5dB */
0x14400051, /* 32, -10.0dB */
0x1300004c, /* 33, -10.5dB */
0x12000048, /* 34, -11.0dB */
0x11000044, /* 35, -11.5dB */
0x10000040, /* 36, -12.0dB */
};
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
};
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
};
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
0x0b40002d, /* 0, -15.0dB */
0x0c000030, /* 1, -14.5dB */
0x0cc00033, /* 2, -14.0dB */
0x0d800036, /* 3, -13.5dB */
0x0e400039, /* 4, -13.0dB */
0x0f00003c, /* 5, -12.5dB */
0x10000040, /* 6, -12.0dB */
0x11000044, /* 7, -11.5dB */
0x12000048, /* 8, -11.0dB */
0x1300004c, /* 9, -10.5dB */
0x14400051, /* 10, -10.0dB */
0x15800056, /* 11, -9.5dB */
0x16c0005b, /* 12, -9.0dB */
0x18000060, /* 13, -8.5dB */
0x19800066, /* 14, -8.0dB */
0x1b00006c, /* 15, -7.5dB */
0x1c800072, /* 16, -7.0dB */
0x1e400079, /* 17, -6.5dB */
0x20000080, /* 18, -6.0dB */
0x22000088, /* 19, -5.5dB */
0x24000090, /* 20, -5.0dB */
0x26000098, /* 21, -4.5dB */
0x288000a2, /* 22, -4.0dB */
0x2ac000ab, /* 23, -3.5dB */
0x2d4000b5, /* 24, -3.0dB */
0x300000c0, /* 25, -2.5dB */
0x32c000cb, /* 26, -2.0dB */
0x35c000d7, /* 27, -1.5dB */
0x390000e4, /* 28, -1.0dB */
0x3c8000f2, /* 29, -0.5dB */
0x40000100, /* 30, +0dB */
0x43c0010f, /* 31, +0.5dB */
0x47c0011f, /* 32, +1.0dB */
0x4c000130, /* 33, +1.5dB */
0x50800142, /* 34, +2.0dB */
0x55400155, /* 35, +2.5dB */
0x5a400169, /* 36, +3.0dB */
0x5fc0017f, /* 37, +3.5dB */
0x65400195, /* 38, +4.0dB */
0x6b8001ae, /* 39, +4.5dB */
0x71c001c7, /* 40, +5.0dB */
0x788001e2, /* 41, +5.5dB */
0x7f8001fe /* 42, +6.0dB */
};
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
};
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
};
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
0x0CD,
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
/* JJ ADD 20161014 */
u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263, /*19*/
0x287, /*20*/
0x2AE, /*21*/
0x2D6, /*22*/
0x301, /*23*/
0x32F, /*24*/
0x35F, /*25*/
0x392, /*26*/
0x3C9, /*27*/
0x402, /*28*/
0x43F, /*29*/
0x47F, /*30*/
0x4C3, /*31*/
0x50C, /*32*/
0x558, /*33*/
0x5A9, /*34*/
0x5FF, /*35*/
0x65A, /*36*/
0x6BA,
0x720,
0x78C,
0x7FF,
};
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB */
0x088, /* 1, -11.5dB */
0x090, /* 2, -11.0dB */
0x099, /* 3, -10.5dB */
0x0A2, /* 4, -10.0dB */
0x0AC, /* 5, -9.5dB */
0x0B6, /* 6, -9.0dB */
0x0C0, /* 7, -8.5dB */
0x0CC, /* 8, -8.0dB */
0x0D8, /* 9, -7.5dB */
0x0E5, /* 10, -7.0dB */
0x0F2, /* 11, -6.5dB */
0x101, /* 12, -6.0dB */
0x110, /* 13, -5.5dB */
0x120, /* 14, -5.0dB */
0x131, /* 15, -4.5dB */
0x143, /* 16, -4.0dB */
0x156, /* 17, -3.5dB */
0x16A, /* 18, -3.0dB */
0x180, /* 19, -2.5dB */
0x197, /* 20, -2.0dB */
0x1AF, /* 21, -1.5dB */
0x1C8, /* 22, -1.0dB */
0x1E3, /* 23, -0.5dB */
0x200, /* 24, +0 dB */
0x21E, /* 25, +0.5dB */
0x23E, /* 26, +1.0dB */
0x261, /* 27, +1.5dB */
0x285, /* 28, +2.0dB */
0x2AB, /* 29, +2.5dB */
0x2D3, /* 30, +3.0dB */
0x2FE, /* 31, +3.5dB */
0x32B, /* 32, +4.0dB */
0x35C, /* 33, +4.5dB */
0x38E, /* 34, +5.0dB */
0x3C4, /* 35, +5.5dB */
0x3FE /* 36, +6.0dB */
};
void
odm_txpowertracking_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
return;
#endif
odm_txpowertracking_thermal_meter_init(dm);
}
u8
get_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {
bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
swing_table = ofdm_swing_table_new;
swing_table_size = OFDM_TABLE_SIZE;
} else {
bb_swing = PHY_GetTxBBSwing_8812A((PADAPTER)adapter, hal_data->CurrentBandType, RF_PATH_A);
swing_table = tx_scaling_table_jaguar;
swing_table_size = TXSCALE_TABLE_SIZE;
}
for (i = 0; i < swing_table_size; ++i) {
u32 table_value = swing_table[i];
if (table_value >= 0x100000)
table_value >>= 22;
if (bb_swing == table_value)
break;
}
return i;
}
u8
get_cck_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_cck_swing;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
break;
}
} else if (dm->support_ic_type == ODM_RTL8703B) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
}
return i;
}
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 default_swing_index = get_swing_index(dm);
u8 default_cck_swing_index = get_cck_swing_index(dm);
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
u8 p = 0;
if (*(dm->mp_mode) == false)
cali_info->txpowertrack_control = true;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef CONFIG_RTL8188E
{
cali_info->is_txpowertracking = true;
cali_info->tx_powercount = 0;
cali_info->is_txpowertracking_init = false;
if (*(dm->mp_mode) == false)
cali_info->txpowertrack_control = true;
MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
}
#else
{
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_priv *pdmpriv = &hal_data->dmpriv;
pdmpriv->is_txpowertracking = true;
pdmpriv->tx_powercount = 0;
pdmpriv->is_txpowertracking_init = false;
if (*(dm->mp_mode) == false)
pdmpriv->txpowertrack_control = true;
MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
}
#endif
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#ifdef RTL8188E_SUPPORT
{
cali_info->is_txpowertracking = true;
cali_info->tx_powercount = 0;
cali_info->is_txpowertracking_init = false;
cali_info->txpowertrack_control = true;
}
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (MP_DRIVER == 1)
cali_info->txpowertrack_control = false;
#else
cali_info->txpowertrack_control = true;
#endif
#else
cali_info->txpowertrack_control = true;
#endif
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter;
if (cali_info->default_bb_swing_index_flag != true) {
/*The index of "0 dB" in SwingTable.*/
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
} else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 20; /*CCK:-6dB*/
} else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
/* JJ ADD 20161014 */
} else if (dm->support_ic_type == ODM_RTL8710B) {
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
} else {
cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
cali_info->default_cck_index = 24;
}
cali_info->default_bb_swing_index_flag = true;
}
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->CCK_index = cali_info->default_cck_index;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->power_index_offset[p] = 0;
cali_info->kfree_offset[p] = 0;
}
cali_info->modify_tx_agc_value_ofdm = 0;
cali_info->modify_tx_agc_value_cck = 0;
cali_info->tm_trigger = 0;
}
void
odm_txpowertracking_check(
void *dm_void
)
{
#if 0
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
/* HW dynamic mechanism. */
#endif
struct dm_struct *dm = (struct dm_struct *)dm_void;
switch (dm->support_platform) {
case ODM_WIN:
odm_txpowertracking_check_mp(dm);
break;
case ODM_CE:
odm_txpowertracking_check_ce(dm);
break;
case ODM_AP:
odm_txpowertracking_check_ap(dm);
break;
default:
break;
}
}
void
odm_txpowertracking_check_ce(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &(dm->rf_table);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *adapter = dm->adapter;
#if ((RTL8188F_SUPPORT == 1))
rtl8192c_odm_check_txpowertracking(adapter);
#endif
#if (RTL8188E_SUPPORT == 1)
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
if (!cali_info->tm_trigger) {
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
cali_info->tm_trigger = 1;
return;
} else {
/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
odm_txpowertracking_callback_thermal_meter_8188e(adapter);
cali_info->tm_trigger = 0;
}
#endif
#endif
}
void
odm_txpowertracking_check_mp(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
if (*dm->is_fcs_mode_enable)
return;
if (odm_check_power_status(dm) == false) {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n"));
return;
}
if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
return;
odm_txpowertracking_thermal_meter_check(adapter);
#endif
}
void
odm_txpowertracking_check_ap(
void *dm_void
)
{
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_txpowertracking_direct_call(
void *adapter
)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
odm_txpowertracking_callback_thermal_meter(adapter);
}
void
odm_txpowertracking_thermal_meter_check(
void *adapter
)
{
static u8 tm_trigger = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(pHalData->DM_OutSrc);
struct _hal_rf_ *rf = &(dm->rf_table);
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n"));
return;
}
if (!tm_trigger) {
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
else
PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
tm_trigger = 1;
return;
} else {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
odm_txpowertracking_direct_call(adapter);
tm_trigger = 0;
}
}
#endif

299
hal/phydm/halrf/halrf_powertracking_win.h Normal file
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@@ -0,0 +1,299 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define TXSCALE_TABLE_SIZE 37
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_8723D 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 3
#define MAX_RF_PATH 4
#define CCK_TABLE_SIZE_88F 21
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define dm_check_txpowertracking odm_txpowertracking_check
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#define AVG_THERMAL_NUM 8
#define iqk_matrix_reg_num 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
/* u8 is_txpowertracking; */
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
u8 thermal_value_dpk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u64 iqk_start_time;
u64 iqk_total_progressing_time;
u64 iqk_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
#endif

321
hal/phydm/halrf/halrf_psd.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
//============================================================
// include files
//============================================================
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if 0
u32 _sqrt(u64 n)
{
u64 ans = 0, q = 0;
s64 i;
/*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/
for (i = 8 * 8 - 2; i > -1; i = i - 2) {
q = (q << 2) | ((n & (3 << i)) >> i);
if (q >= ((ans << 2) | 1))
{
q = q - ((ans << 2) | 1);
ans = (ans << 1) | 1;
}
else
ans = ans << 1;
}
DbgPrint("ans=0x%x\n", ans);
return (u32)ans;
}
#endif
u64 _sqrt(u64 x)
{
u64 i = 0;
u64 j = x / 2 + 1;
while (i <= j) {
u64 mid = (i + j) / 2;
u64 sq = mid * mid;
if (sq == x)
return mid;
else if (sq < x)
i = mid + 1;
else
j = mid - 1;
}
return j;
}
u32
halrf_get_psd_data(
struct dm_struct *dm,
u32 point
)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (psd->average == 0)
delay_time = 100;
else
delay_time = 0;
#else
if (psd->average == 0)
delay_time = 1000;
else
delay_time = 100;
#endif
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
psd_reg = 0x910;
psd_report = 0xf44;
} else {
psd_reg = 0x808;
psd_report = 0x8b4;
}
if (dm->support_ic_type & ODM_RTL8710B) {
psd_point = 0xeffffc00;
psd_start = 0x10000000;
} else {
psd_point = 0xffbffc00;
psd_start = 0x00400000;
}
psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
psd_val &= psd_point;
psd_val |= point;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
psd_val |= psd_start;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
psd_val &= MASKL3BYTES;
psd_val = psd_val / 32;
} else
psd_val &= MASKLWORD;
return psd_val;
}
void
halrf_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average
)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp;
u64 data_tatal = 0, data_temp[64] = {0};
psd->buf_size = 256;
if (average == 0)
average_tmp = 1;
else
average_tmp = average;
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
psd_reg = 0x910;
else
psd_reg = 0x808;
#if 0
dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
if (dm->support_ic_type & ODM_RTL8710B)
avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
else
avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
if (average != 0)
{
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
}
#if 0
if (avg_temp == 0)
avg = 1;
else if (avg_temp == 1)
avg = 8;
else if (avg_temp == 2)
avg = 16;
else if (avg_temp == 3)
avg = 32;
#endif
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
point_temp = i;
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_psd_data(dm, point_temp);
data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
#if 0
if ((k % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", data_temp[k]);
#endif
}
/*dbg_print("\n");*/
data_tatal = ((data_tatal * 100) / average_tmp);
psd->psd_data[j] = (u32)_sqrt(data_tatal);
i++;
j++;
}
#if 0
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", psd->psd_data[i]);
}
dbg_print("\n\n");
#endif
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
}
enum rt_status
halrf_psd_init(
struct dm_struct *dm
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
psd->psd_progress = 0;
}
return ret_status;
}
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
return ret_status;
}
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
psd->point = point;
psd->start_point = start_point;
psd->stop_point = stop_point;
psd->average = average;
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
psd->psd_progress = 0;
}
return ret_status;
}
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/

60
hal/phydm/halrf/halrf_psd.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_PSD_H__
#define __HALRF_PSD_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data {
u32 point;
u32 start_point;
u32 stop_point;
u32 average;
u32 buf_size;
u32 psd_data[256];
u32 psd_progress;
};
enum rt_status
halrf_psd_init (
struct dm_struct *dm
);
enum rt_status
halrf_psd_query (
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size
);
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size
);
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
#endif /*#ifndef __HALRF_PSD_H__*/

303
hal/phydm/halrf/halrf_txgapcal.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void odm_bub_sort(pu4Byte data, u4Byte n)
{
int i, j, temp, sp;
for (i = n - 1;i >= 0;i--) {
sp = 1;
for (j = 0;j < i;j++) {
if (data[j] < data[j + 1]) {
temp = data[j];
data[j] = data[j + 1];
data[j + 1] = temp;
sp = 0;
}
}
if (sp == 1)
break;
}
}
#if (RTL8197F_SUPPORT == 1)
u4Byte
odm_tx_gain_gap_psd_8197f(
void *dm_void,
u1Byte rf_path,
u4Byte rf56
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte i, j;
u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
{0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
{0x38008c2c, 0x10008c2c}};
u4Byte psd_report_addr[2] = {0xea0, 0xec0};
odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00e02);
ODM_delay_us(100);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x0);
odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
while(rf56 != (odm_get_rf_reg(dm, rf_path, 0x56, 0xfff)))
odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44FFBB44);
odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x00400040);
odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005403);
odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000804e4);
odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04203400);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x80800000);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
odm_set_bb_reg(dm, 0xe40, 0xffffffff, 0x81007C00);
odm_set_bb_reg(dm, 0xe44, 0xffffffff, 0x81004800);
odm_set_bb_reg(dm, 0xe4c, 0xffffffff, 0x0046a8d0);
for (i = 0; i < psd_avg_time; i++) {
for(j = 0; j < 1000 ; j++) {
odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xfa005800);
odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xf8005800);
while(!odm_get_bb_reg(dm, 0xeac, psd_finish_bit[rf_path])); /*wait finish bit*/
if (!odm_get_bb_reg(dm, 0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
if (psd_vaule[i] > 0xffff)
break;
}
}
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), j, psd_vaule[i]);
}
odm_bub_sort(psd_vaule, psd_avg_time);
psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44BBBB44);
odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x80408040);
odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005433);
odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000004e4);
odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04003400);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x00000000);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), psd_vaule_temp);
odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00602);
return psd_vaule_temp;
}
void
odm_tx_gain_gap_calibration_8197f(
void *dm_void
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
u4Byte psd_gap, rf56_current_temp[2][11];
s4Byte rf33[2][11];
memset(rf33, 0x0, sizeof(rf33));
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
ODM_delay_us(100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf0_idx_current = 3 * (rf0_idx - 1) + 1;
odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_current);
ODM_delay_us(100);
rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
rf56_current = rf56_current_temp[rf_path][rf0_idx];
rf0_idx_next = 3 * rf0_idx + 1;
odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_next);
ODM_delay_us(100);
rf56_next= odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
rf_path, rf0_idx, rf56_current, rf_path, rf0_idx, rf56_next);
if ((rf56_current >> 5) == (rf56_next >> 5)) {
delta_gain_gap[rf_path][rf0_idx] = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
rf_path, rf0_idx, (rf56_next >> 5), rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
continue;
}
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
rf_path, rf0_idx, (rf56_current >> 5), rf_path, rf0_idx, (rf56_next >> 5));
for (i = 0; i < delta_gain_retry; i++) {
psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
psd_gap = psd_value_next / (psd_value_current / 1000);
#if 0
if (psd_gap > 1413)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1122)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
#endif
if (psd_gap > 1445)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1096)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
if (i == 0)
delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
psd_value_current, psd_value_next, psd_gap, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
if ((i == 0) && (delta_gain_gap[rf_path][rf0_idx] == 0))
break;
if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
delta_gain_gap[rf_path][rf0_idx] = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
break;
} else {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
}
}
}
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
ODM_delay_us(100);
}
/*odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
for (i = rf0_idx; i <= 10; i++)
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
if (rf33[rf_path][rf0_idx] >= 0x1d)
rf33[rf_path][rf0_idx] = 0x1d;
else if (rf33[rf_path][rf0_idx] <= 0x2)
rf33[rf_path][rf0_idx] = 0x2;
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n", rf_path, rf0_idx, rf56_current_temp[rf_path][rf0_idx], rf_path, rf0_idx, rf33[rf_path][rf0_idx]);
odm_set_rf_reg(dm, rf_path, 0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
}
odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00000);
}
}
#endif
void
odm_tx_gain_gap_calibration(
void *dm_void
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
#if (RTL8197F_SUPPORT == 1)
if (dm->SupportICType & ODM_RTL8197F)
odm_tx_gain_gap_calibration_8197f(dm_void);
#endif
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
void
odm_tx_gain_gap_calibration(
void *dm_void
);

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "../halphyrf_ap.h"
void configure_txpower_track_8188e(
struct txpwrtrack_cfg *config
);
void do_iqk_8188e(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
struct dm_struct *dm,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
struct dm_struct *dm,
boolean is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
struct dm_struct *dm
);
/*
* AP calibrate
* */
void
phy_ap_calibrate_8188e(
struct dm_struct *dm,
s8 delta);
void
_phy_save_adda_registers(
struct dm_struct *dm,
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
struct dm_struct *dm,
u32 *adda_reg,
boolean is_path_a_on,
boolean is2T
);
void
_phy_mac_setting_calibration(
struct dm_struct *dm,
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
struct dm_struct *dm
);
void
halrf_rf_lna_setting_8188e(
struct dm_struct *dm,
enum phydm_lna_set type
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "../halphyrf_ce.h"
void configure_txpower_track_8188e(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8188e(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8188e(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
void *dm_void,
boolean is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
void *dm_void
);
void
_phy_save_adda_registers(
struct dm_struct *dm,
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
struct dm_struct *dm,
u32 *adda_reg,
boolean is_path_a_on,
boolean is2T
);
void
_phy_mac_setting_calibration(
struct dm_struct *dm,
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
struct dm_struct *dm
);
void
halrf_rf_lna_setting_8188e(
struct dm_struct *dm,
enum phydm_lna_set type
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 15 /* ms */
#define IQK_DELAY_TIME_8723B 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#if RT_PLATFORM == PLATFORM_MACOSX
#include "halphyrf_win.h"
#else
#include "halrf/halphyrf_win.h"
#endif
void configure_txpower_track_8188e(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8188e(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8188e(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
void *dm_void,
boolean is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
void *dm_void
);
/*
* AP calibrate
* */
#if 0
void
phy_ap_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
s8 delta);
void
phy_digital_predistortion_8188e(void *adapter);
#endif
#define phy_dp_calibrate_8821a phy_dp_calibrate_8812a
void
_phy_save_adda_registers(
struct dm_struct *dm,
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
struct dm_struct *dm,
u32 *adda_reg,
boolean is_path_a_on,
boolean is2T
);
void
_phy_mac_setting_calibration(
struct dm_struct *dm,
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
struct dm_struct *dm
);
void phy_set_rf_path_switch_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
boolean is_main
);
void
halrf_rf_lna_setting_8188e(
struct dm_struct *dm,
enum phydm_lna_set type
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/

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EXTRA_CFLAGS += -I$(src)/hal/phydm
_PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_antdiv.o\
hal/phydm/phydm_soml.o\
hal/phydm/phydm_smt_ant.o\
hal/phydm/phydm_antdect.o\
hal/phydm/phydm_interface.o\
hal/phydm/phydm_phystatus.o\
hal/phydm/phydm_hwconfig.o\
hal/phydm/phydm.o\
hal/phydm/phydm_dig.o\
hal/phydm/phydm_pathdiv.o\
hal/phydm/phydm_rainfo.o\
hal/phydm/phydm_dynamictxpower.o\
hal/phydm/phydm_adaptivity.o\
hal/phydm/phydm_cfotracking.o\
hal/phydm/phydm_noisemonitor.o\
hal/phydm/phydm_beamforming.o\
hal/phydm/phydm_dfs.o\
hal/phydm/txbf/halcomtxbf.o\
hal/phydm/txbf/haltxbfinterface.o\
hal/phydm/txbf/phydm_hal_txbf_api.o\
hal/phydm/phydm_adc_sampling.o\
hal/phydm/phydm_ccx.o\
hal/phydm/phydm_psd.o\
hal/phydm/phydm_primary_cca.o\
hal/phydm/phydm_cck_pd.o\
hal/phydm/phydm_rssi_monitor.o\
hal/phydm/phydm_auto_dbg.o\
hal/phydm/phydm_math_lib.o\
hal/phydm/phydm_api.o\
hal/phydm/phydm_pow_train.o\
hal/phydm/halrf/halrf.o\
hal/phydm/halrf/halphyrf_ce.o\
hal/phydm/halrf/halrf_powertracking_ce.o\
hal/phydm/halrf/halrf_powertracking.o\
hal/phydm/halrf/halrf_kfree.o
ifeq ($(CONFIG_RTL8188E), y)
RTL871X = rtl8188e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
hal/phydm/$(RTL871X)/phydm_rtl8188e.o
endif
ifeq ($(CONFIG_RTL8192E), y)
RTL871X = rtl8192e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
hal/phydm/$(RTL871X)/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_RTL8812A), y)
RTL871X = rtl8812a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8821A), y)
RTL871X = rtl8821a
_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
hal/phydm/rtl8821a/halhwimg8821a_bb.o\
hal/phydm/rtl8821a/halhwimg8821a_rf.o\
hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
hal/phydm/rtl8821a/phydm_regconfig8821a.o\
hal/phydm/rtl8821a/phydm_rtl8821a.o\
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8723B), y)
RTL871X = rtl8723b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8723b.o
endif
ifeq ($(CONFIG_RTL8814A), y)
RTL871X = rtl8814a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
hal/phydm/txbf/haltxbf8814a.o
endif
ifeq ($(CONFIG_RTL8723C), y)
RTL871X = rtl8703b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
endif
ifeq ($(CONFIG_RTL8723D), y)
RTL871X = rtl8723d
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
endif
ifeq ($(CONFIG_RTL8188F), y)
RTL871X = rtl8188f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
hal/phydm/$(RTL871X)/phydm_rtl8188f.o
endif
ifeq ($(CONFIG_RTL8822B), y)
RTL871X = rtl8822b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
hal/phydm/$(RTL871X)/phydm_rtl8822b.o
_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
endif
ifeq ($(CONFIG_RTL8821C), y)
RTL871X = rtl8821c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
/* For phydm_auto_channel_select_setting_ap() */
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
struct acs_info {
boolean is_force_acs_result;
u8 clean_channel_2g;
u8 clean_channel_5g;
u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 acs_step;
/* NHM count 0-11 */
u8 nhm_cnt[14][11];
/* AC-Series, for storing previous setting */
u32 reg0x990;
u32 reg0x994;
u32 reg0x998;
u32 reg0x99c;
u8 reg0x9a0; /* u8 */
/* N-Series, for storing previous setting */
u32 reg0x890;
u32 reg0x894;
u32 reg0x898;
u32 reg0x89c;
u8 reg0xe28; /* u8 */
#endif
};
void
odm_auto_channel_select_init(
void *dm_void
);
void
odm_auto_channel_select_reset(
void *dm_void
);
void
odm_auto_channel_select(
void *dm_void,
u8 channel
);
u8
odm_get_auto_channel_select_result(
void *dm_void,
u8 band
);
boolean
phydm_acs_check(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void
phydm_auto_channel_select_setting_ap(
void *dm_void,
u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
u32 acs_step
);
void
phydm_get_nhm_statistics_ap(
void *dm_void,
u32 idx, /* @ 2G, Real channel number = idx+1 */
u32 acs_step
);
#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
#endif /* #ifndef __PHYDMACS_H__ */

1005
hal/phydm/phydm_adaptivity.c Normal file
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217
hal/phydm/phydm_adaptivity.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.5.7" /*20170627 changed by Kevin, move adapt_igi_up from phydm.h to phydm_adaptivity.h*/
#define pwdb_upper_bound 7
#define dfir_loss 7
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
enum phydm_regulation_type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
};
#endif
enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
};
enum phydm_set_lna {
phydm_disable_lna = 0,
phydm_enable_lna = 1,
};
enum phydm_trx_mux_type {
phydm_shutdown = 0,
phydm_standby_mode = 1,
phydm_tx_mode = 2,
phydm_rx_mode = 3
};
enum phydm_mac_edcca_type {
phydm_ignore_edcca = 0,
phydm_dont_ignore_edcca = 1
};
enum phydm_adaptivity_mode {
PHYDM_ADAPT_MSG = 0,
PHYDM_ADAPT_DEBUG = 1,
PHYDM_ADAPT_RESUME = 2,
PHYDM_EDCCA_TH_PAUSE = 3,
PHYDM_EDCCA_RESUME = 4
};
struct phydm_adaptivity_struct {
s8 th_l2h_ini_backup;
s8 th_edcca_hl_diff_backup;
s8 igi_base;
u8 igi_target;
s8 h2l_lb;
s8 l2h_lb;
boolean is_check;
boolean dynamic_link_adaptivity;
u8 ap_num_th;
u8 adajust_igi_level;
s8 backup_l2h;
s8 backup_h2l;
boolean is_stop_edcca;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_WORK_ITEM phydm_pause_edcca_work_item;
RT_WORK_ITEM phydm_resume_edcca_work_item;
#endif
u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
u8 debug_mode;
s8 th_l2h_ini_debug;
u16 igi_up_bound_lmt_cnt; /*When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
u16 igi_up_bound_lmt_val; /*max value of igi_up_bound_lmt_cnt*/
boolean igi_lmt_en;
u8 adapt_igi_up;
s8 rvrt_val[2];
s8 th_l2h;
s8 th_h2l;
};
void
phydm_pause_edcca(
void *dm_void,
boolean is_pasue_edcca
);
void
phydm_check_environment(
void *dm_void
);
void
phydm_mac_edcca_state(
void *dm_void,
enum phydm_mac_edcca_type state
);
void
phydm_set_edcca_threshold(
void *dm_void,
s8 H2L,
s8 L2H
);
void
phydm_set_trx_mux(
void *dm_void,
enum phydm_trx_mux_type tx_mode,
enum phydm_trx_mux_type rx_mode
);
void
phydm_search_pwdb_lower_bound(
void *dm_void
);
void
phydm_adaptivity_info_init(
void *dm_void,
enum phydm_adapinfo cmn_info,
u32 value
);
void
phydm_adaptivity_init(
void *dm_void
);
void
phydm_adaptivity(
void *dm_void
);
void
phydm_set_edcca_threshold_api(
void *dm_void,
u8 IGI
);
void
phydm_pause_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
#else
void *dm_void
#endif
);
void
phydm_resume_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
#else
void *dm_void
#endif
);
void
phydm_adaptivity_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_set_l2h_th_ini(
void *dm_void
);
void
phydm_set_forgetting_factor(
void *dm_void
);
void
phydm_set_pwdb_mode(
void *dm_void
);
void
phydm_set_edcca_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
#include "rtl8197f/Hal8197FPhyReg.h"
#include "WlanHAL/HalMac88XX/halmac_reg2.h"
#else
#include "WlanHAL/HalHeader/HalComReg.h"
#endif
#endif
#if (PHYDM_LA_MODE_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if WPP_SOFTWARE_TRACE
#include "phydm_adc_sampling.tmh"
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
boolean
phydm_la_buffer_allocate(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
#endif
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
boolean ret = true;
pr_debug("[LA mode BufferAllocate]\n");
if (adc_smp_buf->length == 0) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
if (PlatformAllocateMemoryWithZero(adapter, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS)
ret = false;
#else
odm_allocate_memory(dm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size);
if (!adc_smp_buf->octet)
ret = false;
#endif
if (ret)
adc_smp_buf->length = adc_smp_buf->buffer_size;
}
return ret;
}
#endif
void
phydm_la_get_tx_pkt_buf(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 i = 0, value32, data_l = 0, data_h = 0;
u32 addr, finish_addr;
u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/
boolean is_round_up;
static u32 page = 0xFF;
u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
u8 backup_dma = 0;
odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
odm_write_1byte(dm, 0x0106, 0x69);
pr_debug("GetTxPktBuf\n");
value32 = odm_read_4byte(dm, 0x7c0);
is_round_up = (boolean)((value32 & BIT(31)) >> 31);
finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8197F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197F) {
odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
/*Stop DMA*/
backup_dma = odm_get_mac_reg(dm, 0x300, MASKLWORD);
odm_set_mac_reg(dm, 0x300, 0x7fff, 0x7fff);
/*move LA mode content from IMEM to TxPktBuffer
Source : OCPBASE_IMEM 0x00000000
Destination : OCPBASE_TXBUF 0x18780000
Length : 64K*/
GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
}
#endif
#endif
if (is_round_up) {
addr = (finish_addr + 1) << 3;
pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32);
smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 8Byte (64bit)*/
} else {
addr = adc_smp_buf->start_pos;
addr_8byte = addr >> 3;
if (addr_8byte > finish_addr)
smp_number = addr_8byte - finish_addr;
else
smp_number = finish_addr - addr_8byte;
pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number);
}
/*
dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32);
dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size);
*/
if (dm->support_ic_type & ODM_RTL8197F) {
for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/
if ((addr & 0xfff) == 0)
odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + (addr >> 12));
data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD);
data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
pr_debug("%08x%08x\n", data_h, data_l);
}
} else {
i = 0;
while (addr != (finish_addr << 3)) {
if (page != (addr >> 12)) {
/*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/
page = (addr >> 12);
}
odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
/*pDataL = 0x8000+(addr&0xfff);*/
data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD);
data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
adc_smp_buf->octet[i] = data_h;
adc_smp_buf->octet[i + 1] = data_l;
#endif
#if DBG /*WIN driver check build*/
pr_debug("%08x%08x\n", data_h, data_l);
#else /*WIN driver free build*/
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
#endif
#endif
i = i + 2;
if ((addr + 8) >= end_addr)
addr = adc_smp_buf->start_pos;
else
addr = addr + 8;
smp_cnt++;
if (smp_cnt >= (smp_number - 1))
break;
}
pr_debug("smp_cnt = ((%d))\n", smp_cnt);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt));
#endif
}
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8197F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197F)
odm_set_mac_reg(dm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/
#endif
#endif
}
void
phydm_la_mode_set_mac_iq_dump(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u32 reg_value;
odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
adc_smp->is_bb_trigger = 0;
odm_set_mac_reg(dm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/
odm_set_mac_reg(dm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/
pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port);
/*[Set MAC Debug Port]*/
odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel);
odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
} else {
adc_smp->is_bb_trigger = 1;
odm_set_mac_reg(dm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/
if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
odm_set_mac_reg(dm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/
odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel);
if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
odm_set_mac_reg(dm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/
}
}
reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
pr_debug("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value));
#endif
}
void
phydm_adc_smp_start(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 tmp_u1b;
u8 while_cnt = 0;
u8 polling_ok = false, target_polling_bit;
phydm_la_mode_bb_setting(dm);
phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
if (dm->support_ic_type & ODM_RTL8197F)
odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
else { /*for 8814A and 8822B?*/
odm_write_1byte(dm, 0x8b4, 0x80);
/* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
}
phydm_la_mode_set_mac_iq_dump(dm);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
watchdog_stop(dm->priv);
#endif
target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/
tmp_u1b = odm_read_1byte(dm, 0x7c0);
if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
break;
} else if (tmp_u1b & target_polling_bit) {
ODM_delay_ms(100);
while_cnt = while_cnt + 1;
continue;
} else {
pr_debug("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit);
polling_ok = true;
break;
}
} while (while_cnt < 20);
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
if (polling_ok)
phydm_la_get_tx_pkt_buf(dm);
else
pr_debug("[Polling timeout]\n");
}
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
watchdog_resume(dm->priv);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
#endif
pr_debug("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count));
#endif
adc_smp_stop(dm);
if (adc_smp->la_count == 0) {
pr_debug("LA Dump finished ---------->\n\n\n");
phydm_release_bb_dbg_port(dm);
if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B))
odm_set_bb_reg(dm, 0x95c, BIT(23), 0);
} else {
adc_smp->la_count--;
pr_debug("LA Dump more ---------->\n\n\n");
adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
}
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void
adc_smp_work_item_callback(
void *context
)
{
void *adapter = (void *)context;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
pr_debug("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state);
phydm_adc_smp_start(dm);
}
#endif
void
adc_smp_set(
void *dm_void,
u8 trig_mode,
u32 trig_sig_sel,
u8 dma_data_sig_sel,
u32 trigger_time,
u16 polling_time
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean is_set_success = true;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
adc_smp->la_trig_mode = trig_mode;
adc_smp->la_trig_sig_sel = trig_sig_sel;
adc_smp->la_dma_type = dma_data_sig_sel;
adc_smp->la_trigger_time = trigger_time;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
is_set_success = false;
else if (adc_smp->adc_smp_buf.length == 0)
is_set_success = phydm_la_buffer_allocate(dm);
#endif
if (is_set_success) {
adc_smp->adc_smp_state = ADCSMP_STATE_SET;
pr_debug("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
pr_debug("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index);
if (adc_smp->la_work_item_index != 0) {
odm_schedule_work_item(&adc_smp->adc_smp_work_item_1);
adc_smp->la_work_item_index = 0;
} else {
odm_schedule_work_item(&adc_smp->adc_smp_work_item);
adc_smp->la_work_item_index = 1;
}
#else
phydm_adc_smp_start(dm);
#endif
} else
pr_debug("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state);
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
enum rt_status
adc_smp_query(
void *dm_void,
ULONG information_buffer_length,
void *information_buffer,
PULONG bytes_written
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
pr_debug("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state);
if (information_buffer_length != adc_smp_buf->buffer_size) {
*bytes_written = 0;
ret_status = RT_STATUS_RESOURCE;
} else if (adc_smp_buf->length != adc_smp_buf->buffer_size) {
*bytes_written = 0;
ret_status = RT_STATUS_RESOURCE;
} else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
*bytes_written = 0;
ret_status = RT_STATUS_PENDING;
} else {
odm_move_memory(dm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size);
*bytes_written = adc_smp_buf->buffer_size;
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
}
pr_debug("Return status %d\n", ret_status);
return ret_status;
}
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void
adc_smp_query(
void *dm_void,
void *output,
u32 out_len,
u32 *pused
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 used = *pused;
u32 i;
/* struct timespec t; */
/* rtw_get_current_timespec(&t); */
pr_debug("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state);
for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"%08x%08x\n", adc_smp_buf->octet[i],
adc_smp_buf->octet[i + 1]);
}
PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
/* PDM_SNPF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */
*pused = used;
}
s32
adc_smp_get_sample_counts(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
return (adc_smp_buf->length >> 2) - 2;
}
s32
adc_smp_query_single_data(
void *dm_void,
void *output,
u32 out_len,
u32 index
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 used = 0;
/* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */
if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Error: la data is not ready yet ...\n");
return -1;
}
if (index < ((adc_smp_buf->length >> 2) - 2)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"%08x%08x\n",
adc_smp_buf->octet[index],
adc_smp_buf->octet[index + 1]);
}
return 0;
}
#endif
void
adc_smp_stop(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
pr_debug("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state);
}
void
adc_smp_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
if (dm->support_ic_type & ODM_RTL8814A) {
adc_smp_buf->start_pos = 0x30000;
adc_smp_buf->buffer_size = 0x10000;
} else if (dm->support_ic_type & ODM_RTL8822B) {
adc_smp_buf->start_pos = 0x20000;
adc_smp_buf->buffer_size = 0x20000;
} else if (dm->support_ic_type & ODM_RTL8197F) {
adc_smp_buf->start_pos = 0x00000;
adc_smp_buf->buffer_size = 0x10000;
} else if (dm->support_ic_type & ODM_RTL8821C) {
adc_smp_buf->start_pos = 0x8000;
adc_smp_buf->buffer_size = 0x8000;
}
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
adc_smp_de_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
adc_smp_stop(dm);
if (adc_smp_buf->length != 0x0) {
odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
adc_smp_buf->length = 0x0;
}
}
#endif
void
phydm_la_mode_bb_setting(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 trig_mode = adc_smp->la_trig_mode;
u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
u32 dbg_port = adc_smp->la_dbg_port;
u8 is_trigger_edge = adc_smp->la_trigger_edge;
u8 sampling_rate = adc_smp->la_smp_rate;
u8 la_dma_type = adc_smp->la_dma_type;
u32 dbg_port_header_sel = 0;
pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type));
#endif
if (trig_mode == PHYDM_MAC_TRIG)
trig_sig_sel = 0; /*ignore this setting*/
/*set BB debug port*/
if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, dbg_port)) {
pr_debug("Set dbg_port((0x%x)) success\n", dbg_port);
}
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
if (trig_mode == PHYDM_ADC_RF0_TRIG)
dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/
else if (trig_mode == PHYDM_ADC_RF1_TRIG)
dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/
else if ((trig_mode == PHYDM_ADC_BB_TRIG) || (trig_mode == PHYDM_ADC_MAC_TRIG)) {
if (adc_smp->la_mac_mask_or_hdr_sel <= 0xf) {
dbg_port_header_sel = adc_smp->la_mac_mask_or_hdr_sel;
} else {
dbg_port_header_sel = 0;
}
}
phydm_bb_dbg_port_header_sel(dm, dbg_port_header_sel);
odm_set_bb_reg(dm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/
odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/
odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
/* (0:) '80MHz'
(1:) '40MHz'
(2:) '20MHz'
(3:) '10MHz'
(4:) '5MHz'
(5:) '2.5MHz'
(6:) '1.25MHz'
(7:) '160MHz (for BW160 ic)'
*/
if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B)) {
odm_set_bb_reg(dm, 0x95c, BIT(23), 1);
}
} else {
odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/
odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
/* (0:) '80MHz'
(1:) '40MHz'
(2:) '20MHz'
(3:) '10MHz'
(4:) '5MHz'
(5:) '2.5MHz'
(6:) '1.25MHz'
(7:) '160MHz (for BW160 ic)'
*/
}
}
void
phydm_la_mode_set_trigger_time(
void *dm_void,
u32 trigger_time_mu_sec
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 trigger_time_unit_num;
u32 time_unit = 0;
if (trigger_time_mu_sec < 128) {
time_unit = 0; /*unit: 1mu sec*/
} else if (trigger_time_mu_sec < 256) {
time_unit = 1; /*unit: 2mu sec*/
} else if (trigger_time_mu_sec < 512) {
time_unit = 2; /*unit: 4mu sec*/
} else if (trigger_time_mu_sec < 1024) {
time_unit = 3; /*unit: 8mu sec*/
} else if (trigger_time_mu_sec < 2048) {
time_unit = 4; /*unit: 16mu sec*/
} else if (trigger_time_mu_sec < 4096) {
time_unit = 5; /*unit: 32mu sec*/
} else if (trigger_time_mu_sec < 8192) {
time_unit = 6; /*unit: 64mu sec*/
}
trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit));
#endif
odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
}
void
phydm_lamode_trigger_setting(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 trig_mode, dma_data_sig_sel;
u32 trig_sig_sel;
boolean is_enable_la_mode;
u32 trigger_time_mu_sec;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
is_enable_la_mode = (boolean)var1[0];
/*dbg_print("echo cmd input_num = %d\n", input_num);*/
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used,
out_len - used,
"{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
/**/
} else if ((is_enable_la_mode == 1)) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
trig_mode = (u8)var1[1];
if (trig_mode == PHYDM_MAC_TRIG)
PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
else
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
trig_sig_sel = var1[2];
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
dma_data_sig_sel = (u8)var1[3];
trigger_time_mu_sec = var1[4]; /*unit: us*/
adc_smp->la_mac_mask_or_hdr_sel = var1[5];
adc_smp->la_dbg_port = var1[6];
adc_smp->la_trigger_edge = (u8) var1[7];
adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
adc_smp->la_count = var1[9];
pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]));
#endif
PDM_SNPF(out_len, used, output + used,
out_len - used,
"a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
trig_mode, trig_sig_sel,
dma_data_sig_sel);
PDM_SNPF(out_len, used, output + used,
out_len - used,
"e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
trigger_time_mu_sec,
adc_smp->la_mac_mask_or_hdr_sel,
adc_smp->la_dbg_port);
PDM_SNPF(out_len, used, output + used,
out_len - used,
"h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
adc_smp->la_trigger_edge,
(80 >> adc_smp->la_smp_rate),
adc_smp->la_count);
adc_smp_set(dm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0);
} else {
adc_smp_stop(dm);
PDM_SNPF(out_len, used, output + used,
out_len - used, "Disable LA mode\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/

172
hal/phydm/phydm_adc_sampling.h Normal file
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@@ -0,0 +1,172 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_ADCSMP_H
#define __INC_ADCSMP_H
#define DYNAMIC_LA_MODE "2.0" /*2017.02.06 Dino */
#if (PHYDM_LA_MODE_SUPPORT == 1)
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
};
enum rt_adcsmp_trig_sel {
PHYDM_ADC_BB_TRIG = 0,
PHYDM_ADC_MAC_TRIG = 1,
PHYDM_ADC_RF0_TRIG = 2,
PHYDM_ADC_RF1_TRIG = 3,
PHYDM_MAC_TRIG = 4
};
enum rt_adcsmp_trig_sig_sel {
ADCSMP_TRIG_CRCOK = 0,
ADCSMP_TRIG_CRCFAIL = 1,
ADCSMP_TRIG_CCA = 2,
ADCSMP_TRIG_REG = 3
};
enum rt_adcsmp_state {
ADCSMP_STATE_IDLE = 0,
ADCSMP_STATE_SET = 1,
ADCSMP_STATE_QUERY = 2
};
struct rt_adcsmp {
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
u32 la_mac_mask_or_hdr_sel; /*1.BB mode: for debug port header sel; 2.MAC mode: for reference mask*/
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u8 is_bb_trigger;
u8 la_work_item_index;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM adc_smp_work_item;
RT_WORK_ITEM adc_smp_work_item_1;
#endif
};
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void
adc_smp_work_item_callback(
void *context
);
#endif
void
adc_smp_set(
void *dm_void,
u8 trig_mode,
u32 trig_sig_sel,
u8 dma_data_sig_sel,
u32 trigger_time,
u16 polling_time
);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
enum rt_status
adc_smp_query(
void *dm_void,
ULONG information_buffer_length,
void *information_buffer,
PULONG bytes_written
);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void
adc_smp_query(
void *dm_void,
void *output,
u32 out_len,
u32 *pused
);
s32
adc_smp_get_sample_counts(
void *dm_void
);
s32
adc_smp_query_single_data(
void *dm_void,
void *output,
u32 out_len,
u32 index
);
#endif
void
adc_smp_stop(
void *dm_void
);
void
adc_smp_init(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
adc_smp_de_init(
void *dm_void
);
#endif
void
phydm_la_mode_bb_setting(
void *dm_void
);
void
phydm_la_mode_set_trigger_time(
void *dm_void,
u32 trigger_time_mu_sec
);
void
phydm_lamode_trigger_setting(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
#endif

843
hal/phydm/phydm_antdect.c Normal file
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@@ -0,0 +1,843 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
#if (defined(CONFIG_ANT_DETECTION))
/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
* IS_ANT_DETECT_SUPPORT_RSSI(adapter)
* IS_ANT_DETECT_SUPPORT_PSD(adapter) */
/* 1 [1. Single Tone method] =================================================== */
/*
* Description:
* Set Single/Dual Antenna default setting for products that do not do detection in advance.
*
* Added by Joseph, 2012.03.22
* */
void
odm_single_dual_antenna_default_setting(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
void *adapter = dm->adapter;
u8 bt_ant_num = BT_GetPgAntNum(adapter);
/* Set default antenna A and B status */
if (bt_ant_num == 2) {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = true;
} else if (bt_ant_num == 1) {
/* Set antenna A as default */
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = false;
} else
RT_ASSERT(false, ("Incorrect antenna number!!\n"));
}
/* 2 8723A ANT DETECT
*
* Description:
* Implement IQK single tone for RF DPK loopback and BB PSD scanning.
* This function is cooperated with BB team Neil.
*
* Added by Roger, 2011.12.15
* */
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
u32 current_channel, rf_loop_reg;
u8 n;
u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
boolean is_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection()============>\n");
if (!(dm->support_ic_type & ODM_RTL8723B))
return is_result;
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
return is_result;
/* 1 Backup Current RF/BB Settings */
current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK);
if (dm->support_ic_type & ODM_RTL8723B) {
reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
}
ODM_delay_us(10);
/* Store A path Register 88c, c08, 874, c50 */
reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
/* Store AFE Registers */
if (dm->support_ic_type & ODM_RTL8723B)
afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
/* Set PSD 128 pts */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */
/* To SET CH1 to do */
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */
/* AFE all on step */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
/* 3 wire Disable */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
/* BB IQK setting */
odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
/* IQK setting tone@ 4.34Mhz */
odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
/* Page B init */
odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
if (dm->support_ic_type & ODM_RTL8723B) {
odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
}
odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
/* IQK Single tone start */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
ODM_delay_us(10000);
/* PSD report of antenna A */
PSD_report_tmp = 0x0;
for (n = 0; n < 2; n++) {
PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
if (PSD_report_tmp > ant_a_report)
ant_a_report = PSD_report_tmp;
}
/* change to Antenna B */
if (dm->support_ic_type & ODM_RTL8723B) {
/* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
}
ODM_delay_us(10);
/* PSD report of antenna B */
PSD_report_tmp = 0x0;
for (n = 0; n < 2; n++) {
PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
if (PSD_report_tmp > ant_b_report)
ant_b_report = PSD_report_tmp;
}
/* Close IQK Single Tone function */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
/* 1 Return to antanna A */
if (dm->support_ic_type & ODM_RTL8723B) {
/* external DPDT */
odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
/* internal S0/S1 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
}
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
odm_set_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg);
/* Reload AFE Registers */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
if (dm->support_ic_type & ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, ant_a_report);
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, ant_b_report);
/* 2 Test ant B based on ant A is ON */
if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) {
u8 TH1 = 2, TH2 = 6;
if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Dual Antenna\n");
} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
dm_swat_table->ANTA_ON = false;
dm_swat_table->ANTB_ON = false;
is_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Need to check again\n");
} else {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Single Antenna\n");
}
dm->ant_detected_info.is_ant_detected = true;
dm->ant_detected_info.db_for_ant_a = ant_a_report;
dm->ant_detected_info.db_for_ant_b = ant_b_report;
dm->ant_detected_info.db_for_ant_o = ant_0_report;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
is_result = false;
}
}
return is_result;
}
/* 1 [2. Scan AP RSSI method] ================================================== */
boolean
odm_sw_ant_div_check_before_link(
void *dm_void
)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
//PMGNT_INFO mgnt_info = &adapter->MgntInfo;
PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
s8 score = 0;
PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
u8 power_target_L = 9, power_target_H = 16;
u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
u16 index, counter = 0;
static u8 scan_channel;
u32 tmp_swas_no_link_bk_reg948;
PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
/* if(HP id) */
{
if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV, "8723B RSSI-based Antenna Detection is done\n");
return false;
}
if (dm->support_ic_type == ODM_RTL8723B) {
if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
}
}
if (dm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */
/* The ODM structure is not initialized. */
return false;
}
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
return false;
else
PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n",
mgnt_info->RFChangeInProgress, hal_data->eRFPowerState);
dm_swat_table->swas_no_link_state = 0;
return false;
} else
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", dm_swat_table->swas_no_link_state);
/* 1 Run AntDiv mechanism "Before Link" part. */
if (dm_swat_table->swas_no_link_state == 0) {
/* 1 Prepare to do Scan again to check current antenna state. */
/* Set check state to next step. */
dm_swat_table->swas_no_link_state = 1;
/* Copy Current Scan list. */
mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
/* Go back to scan function again. */
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Scan one more time\n");
mgnt_info->ScanStep = 0;
mgnt_info->bScanAntDetect = true;
scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
else
odm_update_rx_idle_ant(dm, MAIN_ANT);
if (scan_channel == 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
} else {
dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
return false;
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
} else if (dm->support_ic_type & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
if ((dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) {
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
dm_swat_table->cur_antenna = AUX_ANT;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV, "Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948);
return false;
}
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX");
}
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* dm_swat_table->swas_no_link_state == 1 */
/* 1 ScanComple() is called after antenna swiched. */
/* 1 Check scan result and determine which antenna is going */
/* 1 to be used. */
PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", mgnt_info->tmpNumBssDesc); /* debug for Dino */
for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* Antenna 1 */
p_test_bss_desc = &mgnt_info->bssDesc[index]; /* Antenna 2 */
if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n");
continue;
}
if (dm->support_ic_type != ODM_RTL8723B) {
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score++\n");
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score++;
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score--\n");
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score--;
} else {
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
}
}
}
} else { /* 8723B */
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
counter++;
tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
if (tmp_power_diff > max_power_diff)
max_power_diff = tmp_power_diff;
if (tmp_power_diff < min_power_diff)
min_power_diff = tmp_power_diff;
/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
counter++;
tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
if (tmp_power_diff > max_power_diff)
max_power_diff = tmp_power_diff;
if (tmp_power_diff < min_power_diff)
min_power_diff = tmp_power_diff;
} else { /* Pow(Ant1) = Pow(Ant2) */
if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
counter++;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
min_power_diff = 0;
}
} else
PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
}
}
}
}
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (mgnt_info->NumBssDesc != 0 && score < 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
} else {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
else
odm_update_rx_idle_ant(dm, MAIN_ANT);
}
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
} else {
dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
if (counter == 0) {
if (dm->dm_swat_table.pre_aux_fail_detec == false) {
dm->dm_swat_table.pre_aux_fail_detec = true;
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n");
/* 3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* pre_aux_fail_detec == true */
/* 2 [ Single Antenna ] */
dm->dm_swat_table.pre_aux_fail_detec = false;
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
dm->dm_swat_table.aux_fail_detec_counter++;
} else {
dm->dm_swat_table.pre_aux_fail_detec = false;
if (counter == 3) {
avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
} else if (counter >= 4) {
avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
} else { /* counter==1,2 */
avg_power_diff = power_diff / counter;
PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
}
/* 2 [ Retry ] */
if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) {
dm->dm_swat_table.retry_counter++;
if (dm->dm_swat_table.retry_counter <= 3) {
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff);
/* 3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else {
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
}
/* 2 [ Dual Antenna ] */
else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
dm->dm_swat_table.dual_ant_counter++;
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
/* 3 [ Init antenna diversity ] */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* 2 [ Single Antenna ] */
else if (avg_power_diff > power_target_H) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
/* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
dm->dm_swat_table.single_ant_counter++;
}
}
/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
PHYDM_DBG(dm, DBG_ANT_DIV, "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
dm->dm_swat_table.dual_ant_counter, dm->dm_swat_table.single_ant_counter, dm->dm_swat_table.retry_counter, dm->dm_swat_table.aux_fail_detec_counter);
/* 2 recover the antenna setting */
if (dm->dm_swat_table.ANTB_ON == false)
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
PHYDM_DBG(dm, DBG_ANT_DIV, "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", dm->dm_swat_table.rssi_ant_dect_result, dm_swat_table->swas_no_link_bk_reg948);
}
/* Check state reset to default and wait for next time. */
dm_swat_table->swas_no_link_state = 0;
mgnt_info->bScanAntDetect = false;
return false;
}
#else
return false;
#endif
return false;
}
/* 1 [3. PSD method] ========================================================== */
void
odm_single_dual_antenna_detection_psd(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 channel_ori;
u8 initial_gain = 0x36;
u8 tone_idx;
u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
u16 tone_idx_2[4] = {8, 24, 40, 56};
u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
/* u8 tone_lenth_1=4, tone_lenth_2=2; */
/* u16 tone_idx_1[4]={88, 120, 24, 56}; */
/* u16 tone_idx_2[2]={ 24, 56}; */
/* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
u32 PSD_power_threshold;
u32 main_psd_result = 0, aux_psd_result = 0;
u32 regc50, reg948, regb2c, regc14, reg908;
u32 i = 0, test_num = 8;
if (dm->support_ic_type != ODM_RTL8723B)
return;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection_psd()============>\n");
/* 2 [ Backup Current RF/BB Settings ] */
channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
regc14 = odm_get_bb_reg(dm, 0xc14, MASKDWORD);
reg908 = odm_get_bb_reg(dm, 0x908, MASKDWORD);
/* 2 [ setting for doing PSD function (CH4)] */
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
/* PHYTXON while loop */
odm_set_bb_reg(dm, 0x908, MASKDWORD, 0x803);
while (odm_get_bb_reg(dm, 0xdf4, BIT(6))) {
i++;
if (i > 1000000) {
PHYDM_DBG(dm, DBG_ANT_DIV, "Wait in %s() more than %d times!\n", __FUNCTION__, i);
break;
}
}
odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
ODM_delay_us(3000);
/* 2 [ Doing PSD Function in (CH4)] */
/* Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_idx] += PSD_report_temp;
}
}
/* Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_idx] += PSD_report_temp;
}
}
/* 2 [ Doing PSD Function in (CH8)] */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
ODM_delay_us(3000);
odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
ODM_delay_us(3000);
/* Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* 2 [ Calculate Result ] */
PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]);
main_psd_result += psd_report_main[tone_idx];
if (psd_report_main[tone_idx] > max_psd_report_main)
max_psd_report_main = psd_report_main[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", max_psd_report_main);
PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]);
aux_psd_result += psd_report_aux[tone_idx];
if (psd_report_aux[tone_idx] > max_psd_report_aux)
max_psd_report_aux = psd_report_aux[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", max_psd_report_aux);
/* main_psd_result=main_psd_result-max_psd_report_main; */
/* aux_psd_result=aux_psd_result-max_psd_report_aux; */
PSD_power_threshold = (main_psd_result * 7) >> 3;
PHYDM_DBG(dm, DBG_ANT_DIV, "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold);
/* 3 [ Dual Antenna ] */
if (aux_psd_result >= PSD_power_threshold) {
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
/* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
/* Init antenna diversity */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* 3 [ Single Antenna ] */
else {
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
/* 2 [ Recover all parameters ] */
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
odm_set_bb_reg(dm, 0xc50, 0x7f, regc50);
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
odm_set_bb_reg(dm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
odm_set_bb_reg(dm, 0x908, MASKDWORD, reg908);
return;
}
#endif
void
odm_sw_ant_detect_init(
void *dm_void
)
{
#if (defined(CONFIG_ANT_DETECTION))
#if (RTL8723B_SUPPORT == 1)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
if (dm->support_ic_type != ODM_RTL8723B)
return;
/* dm_swat_table->pre_antenna = MAIN_ANT; */
/* dm_swat_table->cur_antenna = MAIN_ANT; */
dm_swat_table->swas_no_link_state = 0;
dm_swat_table->pre_aux_fail_detec = false;
dm_swat_table->swas_no_link_bk_reg948 = 0xff;
#ifdef CONFIG_PSD_TOOL
phydm_psd_init(dm);
#endif
#endif
#endif
}

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hal/phydm/phydm_antdect.h Normal file
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@@ -0,0 +1,100 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
#if (defined(CONFIG_ANT_DETECTION))
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
/* ANT Test */
#define ANTTESTALL 0x00 /*ant A or B will be Testing*/
#define ANTTESTA 0x01 /*ant A will be Testing*/
#define ANTTESTB 0x02 /*ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
struct _ANT_DETECTED_INFO {
boolean is_ant_detected;
u32 db_for_ant_a;
u32 db_for_ant_b;
u32 db_for_ant_o;
};
enum dm_swas {
antenna_a = 1,
antenna_b = 2,
antenna_max = 3,
};
/* 1 [1. Single Tone method] =================================================== */
void
odm_single_dual_antenna_default_setting(
void *dm_void
);
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode
);
/* 1 [2. Scan AP RSSI method] ================================================== */
#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
boolean
odm_sw_ant_div_check_before_link(
void *dm_void
);
/* 1 [3. PSD method] ========================================================== */
void
odm_single_dual_antenna_detection_psd(
void *dm_void
);
#endif
void
odm_sw_ant_detect_init(
void *dm_void
);
#endif

4702
hal/phydm/phydm_antdiv.c Normal file
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617
hal/phydm/phydm_antdiv.h Normal file
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@@ -0,0 +1,617 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
because antenna diversity only works when BT is disable or radio off*/
/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */
/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */
/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */
/*#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
#define ANTDIV_VERSION "4.0" /*2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*ant A or ant Main or S1*/
#define AUX_ANT 2 /*AntB or ant Aux or S0*/
#define MAX_ANT 3 /* 3 for AP using*/
#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
#define NUM_ANTENNA_8821A 2
#define SUPPORT_BEAM_SET_PATTERN_NUM 16
#define NO_FIX_TX_ANT 0
#define FIX_TX_AT_MAIN 1
#define FIX_AUX_AT_MAIN 2
/* Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_ANTDIV_2G BIT(0)
#define ODM_ANTDIV_5G BIT(1)
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define TX_BY_REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define TP_METHOD 3
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define evm_rssi_th_high 25
#define evm_rssi_th_low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define bdc_bfer_train_state 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
/*SW S0S1 antenna diversity*/
#define SWAW_STEP_INIT 0xff
#define SWAW_STEP_PEEK 0
#define SWAW_STEP_DETERMINE 1
#define RSSI_CHECK_RESET_PERIOD 10
#define RSSI_CHECK_THRESHOLD 50
/*Hong Lin Smart antenna*/
#define HL_SMTANT_2WIRE_DATA_LEN 24
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct sw_antenna_switch {
u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
u8 try_flag;
s32 pre_rssi;
u8 cur_antenna;
u8 pre_antenna;
u8 rssi_trying;
u8 reset_idx;
u8 train_time;
u8 train_time_flag; /*base on RSSI difference between two antennas*/
struct phydm_timer_list phydm_sw_antenna_switch_timer;
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
boolean is_sw_ant_div_by_ctrl_frame;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM phydm_sw_antenna_switch_workitem;
#endif
#endif
/* AntDect (Before link Antenna Switch check) need to be moved*/
u16 single_ant_counter;
u16 dual_ant_counter;
u16 aux_fail_detec_counter;
u16 retry_counter;
u8 swas_no_link_state;
u32 swas_no_link_bk_reg948;
boolean ANTA_ON; /*To indicate ant A is or not*/
boolean ANTB_ON; /*To indicate ant B is on or not*/
boolean pre_aux_fail_detec;
boolean rssi_ant_dect_result;
u8 ant_5g;
u8 ant_2g;
};
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
struct _BF_DIV_COEX_ {
boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u8 bd_ccoex_type_wbfer;
u8 num_txbfee_client;
u8 num_txbfer_client;
u8 bdc_try_counter;
u8 bdc_hold_counter;
u8 bdc_mode;
u8 bdc_active_mode;
u8 BDC_state;
u8 bdc_rx_idle_update_counter;
u8 num_client;
u8 pre_num_client;
u8 num_bf_tar;
u8 num_div_tar;
boolean is_all_div_sta_idle;
boolean is_all_bf_sta_idle;
boolean bdc_try_flag;
boolean BF_pass;
boolean DIV_pass;
};
#endif
#endif
struct phydm_fat_struct {
u8 bssid[6];
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u8 antsel_rx_keep_3;
u32 ant_sum_rssi[7];
u32 ant_rssi_cnt[7];
u32 ant_ave_rssi[7];
u8 fat_state;
u8 fat_state_cnt;
u32 train_idx;
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
u8 rvrt_val;
u8 ant_div_on_off;
boolean is_become_linked;
u32 min_max_rssi;
u8 idx_ant_div_counter_2g;
u8 idx_ant_div_counter_5g;
u8 ant_div_2g_5g;
#ifdef ODM_EVM_ENHANCE_ANTDIV
/*For 1SS RX phy rate*/
u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
/*For 2SS RX phy rate*/
u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/
u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A2+B*/
u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
boolean evm_method_enable;
u8 target_ant_evm;
u8 target_ant_crc32;
u8 target_ant_tp;
u8 target_ant_enhance;
u8 pre_target_ant_enhance;
u16 main_mpdu_ok_cnt;
u16 aux_mpdu_ok_cnt;
u32 crc32_ok_cnt;
u32 crc32_fail_cnt;
u32 main_crc32_ok_cnt;
u32 aux_crc32_ok_cnt;
u32 main_crc32_fail_cnt;
u32 aux_crc32_fail_cnt;
u32 antdiv_tp_main;
u32 antdiv_tp_aux;
u32 antdiv_tp_main_cnt;
u32 antdiv_tp_aux_cnt;
u8 pre_antdiv_rssi;
u8 pre_antdiv_tp;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u32 cck_ctrl_frame_cnt_main;
u32 cck_ctrl_frame_cnt_aux;
u32 ofdm_ctrl_frame_cnt_main;
u32 ofdm_ctrl_frame_cnt_aux;
u32 main_ant_ctrl_frame_sum;
u32 aux_ant_ctrl_frame_sum;
u32 main_ant_ctrl_frame_cnt;
u32 aux_ant_ctrl_frame_cnt;
#endif
u8 b_fix_tx_ant;
boolean fix_ant_bfee;
boolean enable_ctrl_frame_antdiv;
boolean use_ctrl_frame_antdiv;
boolean *is_no_csi_feedback;
u8 hw_antsw_occur;
u8 *p_force_tx_ant_by_desc;
u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/
u8 *p_default_s0_s1;
u8 default_s0_s1;
};
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
enum fat_state /*Fast antenna training*/
{
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
FAT_TRAINING_STATE = 2,
FAT_DECISION_STATE = 3
};
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/
HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
};
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
odm_stop_antenna_switch_dm(
void *dm_void
);
void
phydm_enable_antenna_diversity(
void *dm_void
);
void
odm_set_ant_config(
void *dm_void,
u8 ant_setting /* 0=A, 1=B, 2=C, .... */
);
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
void odm_sw_ant_div_rest_after_link(
void *dm_void
);
void
odm_ant_div_on_off(
void *dm_void,
u8 swch
);
void
odm_tx_by_tx_desc_or_reg(
void *dm_void,
u8 swch
);
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
void
phydm_antdiv_reset_statistic(
void *dm_void,
u32 macid
);
void
odm_update_rx_idle_ant(
void *dm_void,
u8 ant
);
void
phydm_set_antdiv_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
#if (RTL8723B_SUPPORT == 1)
void
odm_update_rx_idle_ant_8723b(
void *dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
);
#endif
#if (RTL8188F_SUPPORT == 1)
void
phydm_update_rx_idle_antenna_8188F(
void *dm_void,
u32 default_ant
);
#endif
#if (RTL8723D_SUPPORT == 1)
void
phydm_set_tx_ant_pwr_8723d(
void *dm_void,
u8 ant
);
void
odm_update_rx_idle_ant_8723d(
void *dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
);
#endif
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_sw_antdiv_callback(
struct phydm_timer_list *timer
);
void
odm_sw_antdiv_workitem_callback(
void *context
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
odm_sw_antdiv_workitem_callback(
void *context
);
void
odm_sw_antdiv_callback(
void *function_context
);
#endif
void
odm_s0s1_sw_ant_div_by_ctrl_frame(
void *dm_void,
u8 step
);
void
odm_antsel_statistics_of_ctrl_frame(
void *dm_void,
u8 antsel_tr_mux,
u32 rx_pwdb_all
);
void
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
void
phydm_evm_sw_antdiv_init(
void *dm_void
);
void
odm_evm_fast_ant_training_callback(
void *dm_void
);
#endif
void
odm_hw_ant_div(
void *dm_void
);
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
void
odm_fast_ant_training(
void *dm_void
);
void
odm_fast_ant_training_callback(
void *dm_void
);
void
odm_fast_ant_training_work_item_callback(
void *dm_void
);
#endif
void
odm_ant_div_init(
void *dm_void
);
void
odm_ant_div(
void *dm_void
);
void
odm_antsel_statistics(
void *dm_void,
void *phy_info_void,
u8 antsel_tr_mux,
u32 mac_id,
u32 utility,
u8 method,
u8 is_cck_rate
);
void
odm_process_rssi_for_ant_div(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
odm_set_tx_ant_by_tx_info(
void *dm_void,
u8 *desc,
u8 mac_id
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
void
odm_set_tx_ant_by_tx_info(
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
unsigned short aid
);
#if 1/*def def CONFIG_WLAN_HAL*/
void
odm_set_tx_ant_by_tx_info_hal(
struct rtl8192cd_priv *priv,
void *pdesc_data,
u16 aid
);
#endif /*#ifdef CONFIG_WLAN_HAL*/
#endif
void
odm_ant_div_config(
void *dm_void
);
void
odm_ant_div_timers(
void *dm_void,
u8 state
);
void
phydm_antdiv_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
void
odm_ant_div_reset(
void *dm_void
);
void
odm_antenna_diversity_init(
void *dm_void
);
void
odm_antenna_diversity(
void *dm_void
);
#endif /*#ifndef __ODMANTDIV_H__*/

1424
hal/phydm/phydm_api.c Normal file
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250
hal/phydm/phydm_api.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_API_H__
#define __PHYDM_API_H__
#define PHYDM_API_VERSION "1.0" /* 2017.07.10 Dino, Add phydm_api.h*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
/*NBI API------------------------------------*/
#define NBI_TABLE_SIZE_128 27
#define NBI_TABLE_SIZE_256 59
#define NUM_START_CH_80M 7
#define NUM_START_CH_40M 14
#define CH_OFFSET_40M 2
#define CH_OFFSET_80M 6
#define FFT_128_TYPE 1
#define FFT_256_TYPE 2
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
/*------------------------------------------------*/
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct phydm_api_stuc {
u32 rx_iqc_reg_1; /*N-mode: for pathA REG0xc14*/
u32 rx_iqc_reg_2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap;/*REG0x520[23:16]*/
};
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
phydm_dynamic_ant_weighting(
void *dm_void
);
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void
phydm_dyn_ant_weight_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
void
phydm_pathb_q_matrix_rotate_en(
void *dm_void
);
void
phydm_pathb_q_matrix_rotate(
void *dm_void,
u16 phase_idx
);
void
phydm_init_trx_antenna_setting(
void *dm_void
);
void
phydm_config_ofdm_rx_path(
void *dm_void,
u32 path
);
void
phydm_config_cck_rx_path(
void *dm_void,
enum bb_path path
);
void
phydm_config_cck_rx_antenna_init(
void *dm_void
);
void
phydm_config_trx_path(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_tx_2path(
void *dm_void
);
void
phydm_stop_3_wire(
void *dm_void,
u8 set_type
);
u8
phydm_stop_ic_trx(
void *dm_void,
u8 set_type
);
void
phydm_set_ext_switch(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_nbi_enable(
void *dm_void,
u32 enable
);
u8
phydm_csi_mask_setting(
void *dm_void,
u32 enable,
u32 channel,
u32 bw,
u32 f_interference,
u32 Second_ch
);
u8
phydm_nbi_setting(
void *dm_void,
u32 enable,
u32 channel,
u32 bw,
u32 f_interference,
u32 second_ch
);
void
phydm_api_debug(
void *dm_void,
u32 function_map,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_stop_ck320(
void *dm_void,
u8 enable
);
boolean
phydm_set_bb_txagc_offset(
void *dm_void,
s8 power_offset,
u8 add_half_db
);
#ifdef PHYDM_COMMON_API_SUPPORT
boolean
phydm_api_set_txagc(
void *dm_void,
u32 power_index,
enum rf_path path,
u8 hw_rate,
boolean is_single_rate
);
u8
phydm_api_get_txagc(
void *dm_void,
enum rf_path path,
u8 hw_rate
);
boolean
phydm_api_switch_bw_channel(
void *dm_void,
u8 central_ch,
u8 primary_ch_idx,
enum channel_width bandwidth
);
boolean
phydm_api_trx_mode(
void *dm_void,
enum bb_path tx_path,
enum bb_path rx_path,
boolean is_tx2_path
);
#endif
#endif

682
hal/phydm/phydm_auto_dbg.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_AUTO_DEGBUG
void
phydm_check_hang_reset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
atd_t->dbg_step = 0;
atd_t->auto_dbg_type = AUTO_DBG_STOP;
phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
dm->debug_components &= (~ODM_COMP_API);
}
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
void
phydm_auto_check_hang_engine_n(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
struct n_dbgport_803 dbgport_803 = {0};
u32 value32_tmp = 0, value32_tmp_2 = 0;
u8 i;
u32 curr_dbg_port_val[DBGPORT_CHK_NUM];
u16 curr_ofdm_t_cnt;
u16 curr_ofdm_r_cnt;
u16 curr_cck_t_cnt;
u16 curr_cck_r_cnt;
u16 curr_ofdm_crc_error_cnt;
u16 curr_cck_crc_error_cnt;
u16 diff_ofdm_t_cnt;
u16 diff_ofdm_r_cnt;
u16 diff_cck_t_cnt;
u16 diff_cck_r_cnt;
u16 diff_ofdm_crc_error_cnt;
u16 diff_cck_crc_error_cnt;
u8 rf_mode;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
phydm_check_hang_reset(dm);
return;
}
if (atd_t->dbg_step == 0) {
pr_debug("dbg_step=0\n\n");
/*Reset all packet counter*/
odm_set_bb_reg(dm, 0xf14, BIT(16), 1);
odm_set_bb_reg(dm, 0xf14, BIT(16), 0);
} else if (atd_t->dbg_step == 1) {
pr_debug("dbg_step=1\n\n");
/*Check packet counter Register*/
atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD);
atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD);
atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD);
atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);;
atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD);
atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) {
atd_t->dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm);
phydm_release_bb_dbg_port(dm);
}
}
} else if (atd_t->dbg_step == 2) {
pr_debug("dbg_step=2\n\n");
/*Check packet counter Register*/
curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD);
curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD);
curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD);
curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);;
curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD);
curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) {
curr_dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm);
phydm_release_bb_dbg_port(dm);
}
}
/*=== Make check hang decision ================================*/
pr_debug("Check Hang Decision\n\n");
/* ----- Check RF Register -----------------------------------*/
for (i = 0; i < dm->num_rf_path; i++) {
rf_mode = (u8)odm_get_rf_reg(dm, i, 0x0, 0xf0000);
pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
if (rf_mode > 3) {
pr_debug("Incorrect RF mode\n");
pr_debug("ReasonCode:RHN-1\n");
}
}
value32_tmp = odm_get_rf_reg(dm, 0, 0xb0, 0xf0000);
if (dm->support_ic_type == ODM_RTL8188E) {
if (value32_tmp != 0xff8c8) {
pr_debug("ReasonCode:RHN-3\n");
}
}
/* ----- Check BB Register -----------------------------------*/
/*BB mode table*/
value32_tmp = odm_get_bb_reg(dm, 0x824, 0xe);
value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0xe);
pr_debug("BB TX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2);
if ((value32_tmp > 3) || (value32_tmp_2 > 3)) {
pr_debug("ReasonCode:RHN-2\n");
}
value32_tmp = odm_get_bb_reg(dm, 0x824, 0x700000);
value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0x700000);
pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2);
if ((value32_tmp > 3) || (value32_tmp_2 > 3)) {
pr_debug("ReasonCode:RHN-2\n");
}
/*BB HW Block*/
value32_tmp = odm_get_bb_reg(dm, 0x800, MASKDWORD);
if (!(value32_tmp & BIT(24))) {
pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
pr_debug("ReasonCode: THN-3\n");
}
if (!(value32_tmp & BIT(25))) {
pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
pr_debug("ReasonCode:THN-3\n");
}
/*BB Continue TX*/
value32_tmp = odm_get_bb_reg(dm, 0xd00, 0x70000000);
pr_debug("Continue TX=%d\n", value32_tmp);
if (value32_tmp != 0) {
pr_debug("ReasonCode: THN-4\n");
}
/* ----- Check Packet Counter --------------------------------*/
diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt - atd_t->ofdm_crc_error_cnt;
diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
diff_cck_crc_error_cnt = curr_cck_crc_error_cnt - atd_t->cck_crc_error_cnt;
pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt, atd_t->ofdm_crc_error_cnt);
pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_ofdm_t_cnt, curr_ofdm_r_cnt, curr_ofdm_crc_error_cnt);
pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_ofdm_t_cnt, diff_ofdm_r_cnt, diff_ofdm_crc_error_cnt);
pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->cck_t_cnt, atd_t->cck_r_cnt, atd_t->cck_crc_error_cnt);
pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_cck_t_cnt, curr_cck_r_cnt, curr_cck_crc_error_cnt);
pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_cck_t_cnt, diff_cck_r_cnt, diff_cck_crc_error_cnt);
/* ----- Check Dbg Port --------------------------------*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
pr_debug("Dbg_port=((0x%x))\n", atd_t->dbg_port_table[i]);
pr_debug("Val{pre, curr}={0x%x, 0x%x}\n", atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
if ((atd_t->dbg_port_table[i]) == 0) {
if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) {
pr_debug("BB state hang\n");
pr_debug("ReasonCode:\n");
}
} else if (atd_t->dbg_port_table[i] == 0x803) {
if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) {
//dbgport_803 = (struct n_dbgport_803 )(atd_t->dbg_port_val[i]);
odm_move_memory(dm, &dbgport_803,
&atd_t->dbg_port_val[i],
sizeof(struct n_dbgport_803));
pr_debug("RSTB{BB, GLB, OFDM}={%d, %d, %d}\n", dbgport_803.bb_rst_b, dbgport_803.glb_rst_b, dbgport_803.ofdm_rst_b);
pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n", dbgport_803.ofdm_tx_en, dbgport_803.cck_tx_en, dbgport_803.phy_tx_on);
pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n", dbgport_803.ofdm_cca_pp, dbgport_803.cck_cca_pp);
if (dbgport_803.phy_tx_on)
pr_debug("Maybe TX Hang\n");
else if (dbgport_803.ofdm_cca_pp || dbgport_803.cck_cca_pp)
pr_debug("Maybe RX Hang\n");
}
} else if (atd_t->dbg_port_table[i] == 0x208) {
if ((atd_t->dbg_port_val[i] & BIT(30)) && (curr_dbg_port_val[i] & BIT(30))) {
pr_debug("EDCCA Pause TX\n");
pr_debug("ReasonCode: THN-2\n");
}
} else if (atd_t->dbg_port_table[i] == 0xab0) {
if (((atd_t->dbg_port_val[i] & 0xffffff) == 0) ||
((curr_dbg_port_val[i] & 0xffffff) == 0)) {
pr_debug("Wrong L-SIG formate\n");
pr_debug("ReasonCode: THN-1\n");
}
}
}
phydm_check_hang_reset(dm);
}
atd_t->dbg_step++;
}
void
phydm_bb_auto_check_hang_start_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"PHYDM auto check hang (N-series) is started, Please check the system log\n");
dm->debug_components |= ODM_COMP_API;
atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
atd_t->dbg_step = 0;
phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
*_used = used;
*_out_len = out_len;
}
void
phydm_bb_rx_hang_info_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"not support now\n");
*_used = used;
*_out_len = out_len;
}
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
void
phydm_bb_rx_hang_info_ac(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
return;
value32 = odm_get_bb_reg(dm, 0xF80, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...",
value32);
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7);
/* dbg_port = basic state machine */
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "basic state machine",
value32);
}
/* dbg_port = state machine */
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "state machine", value32);
}
/* dbg_port = CCA-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "CCA-related", value32);
}
/* dbg_port = edcca/rxd*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "edcca/rxd", value32);
}
/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x",
"rx_state/mux_state/ADC_MASK_OFDM", value32);
}
/* dbg_port = bf-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = bf-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = txon/rxd*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "txon/rxd", value32);
}
/* dbg_port = l_rate/l_length*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "l_rate/l_length",
value32);
}
/* dbg_port = rxd/rxd_hit*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
}
/* dbg_port = dis_cca*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "dis_cca", value32);
}
/* dbg_port = tx*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "tx", value32);
}
/* dbg_port = rx plcp*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
}
*_used = used;
*_out_len = out_len;
}
#endif
void
phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Show dbg port: {1} {1}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Auto check hang: {1} {2}\n");
return;
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
if (var1[1] == 1) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
phydm_bb_rx_hang_info_ac(dm, &used, output, &out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
#endif
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_bb_rx_hang_info_n(dm, &used, output, &out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
#endif
}
} else if (var1[1] == 2) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_bb_auto_check_hang_start_n(dm, &used, output, &out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
#endif
}
}
}
*_used = used;
*_out_len = out_len;
}
#endif
void
phydm_auto_dbg_engine(
void *dm_void
)
{
#ifdef PHYDM_AUTO_DEGBUG
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
pr_debug("%s ======>\n", __func__);
if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
pr_debug("Not Support\n");
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_auto_check_hang_engine_n(dm);
#else
pr_debug("Not Support\n");
#endif
}
} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
pr_debug("Not Support\n");
}
#endif
}
void
phydm_auto_dbg_engine_init(
void *dm_void
)
{
#ifdef PHYDM_AUTO_DEGBUG
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0, 0xab1, 0xab2};
PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__);
odm_move_memory(dm, &atd_t->dbg_port_table[0],
&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
phydm_check_hang_reset(dm);
#endif
}

124
hal/phydm/phydm_auto_dbg.h Normal file
View File

@@ -0,0 +1,124 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_AUTO_DBG_H__
#define __PHYDM_AUTO_DBG_H__
#define AUTO_DBG_VERSION "1.0" /* 2017.05.015 Dino, Add phydm_auto_dbg.h*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define AUTO_CHK_HANG_STEP_MAX 3
#define DBGPORT_CHK_NUM 6
#ifdef PHYDM_AUTO_DEGBUG
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
enum auto_dbg_type_e{
AUTO_DBG_STOP = 0,
AUTO_DBG_CHECK_HANG = 1,
AUTO_DBG_CHECK_RA = 2,
AUTO_DBG_CHECK_DIG = 3
};
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct n_dbgport_803 {
/*BYTE 3*/
u8 bb_rst_b: 1;
u8 glb_rst_b: 1;
u8 zero_1bit_1:1;
u8 ofdm_rst_b: 1;
u8 cck_txpe: 1;
u8 ofdm_txpe: 1;
u8 phy_tx_on: 1;
u8 tdrdy: 1;
/*BYTE 2*/
u8 txd:8;
/*BYTE 1*/
u8 cck_cca_pp: 1;
u8 ofdm_cca_pp: 1;
u8 rx_rst: 1;
u8 rdrdy: 1;
u8 rxd_7_4: 4;
/*BYTE 0*/
u8 rxd_3_0: 4;
u8 ofdm_tx_en: 1;
u8 cck_tx_en: 1;
u8 zero_1bit_2:1;
u8 clk_80m: 1;
};
struct phydm_auto_dbg_struc {
enum auto_dbg_type_e auto_dbg_type;
u8 dbg_step;
u16 dbg_port_table[DBGPORT_CHK_NUM];
u32 dbg_port_val[DBGPORT_CHK_NUM];
u16 ofdm_t_cnt;
u16 ofdm_r_cnt;
u16 cck_t_cnt;
u16 cck_r_cnt;
u16 ofdm_crc_error_cnt;
u16 cck_crc_error_cnt;
};
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
void
phydm_auto_dbg_engine(
void *dm_void
);
void
phydm_auto_dbg_engine_init(
void *dm_void
);
#endif

2049
hal/phydm/phydm_beamforming.c Normal file
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411
hal/phydm/phydm_beamforming.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_PHYDM_BEAMFORMING_H
#define __INC_PHYDM_BEAMFORMING_H
#ifndef BEAMFORMING_SUPPORT
#define BEAMFORMING_SUPPORT 0
#endif
/*Beamforming Related*/
#include "txbf/halcomtxbf.h"
#include "txbf/haltxbfjaguar.h"
#include "txbf/haltxbf8192e.h"
#include "txbf/haltxbf8814a.h"
#include "txbf/haltxbf8822b.h"
#include "txbf/haltxbfinterface.h"
#if (BEAMFORMING_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#endif
#define MAX_BEAMFORMEE_SU 2
#define MAX_BEAMFORMER_SU 2
#if (RTL8822B_SUPPORT == 1)
#define MAX_BEAMFORMEE_MU 6
#define MAX_BEAMFORMER_MU 1
#else
#define MAX_BEAMFORMEE_MU 0
#define MAX_BEAMFORMER_MU 0
#endif
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/*for different naming between WIN and CE*/
#define BEACON_QUEUE BCN_QUEUE_INX
#define NORMAL_QUEUE MGT_QUEUE_INX
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
#endif
enum beamforming_entry_state {
BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
BEAMFORMING_ENTRY_STATE_INITIALIZEING,
BEAMFORMING_ENTRY_STATE_INITIALIZED,
BEAMFORMING_ENTRY_STATE_PROGRESSING,
BEAMFORMING_ENTRY_STATE_PROGRESSED
};
enum beamforming_notify_state {
BEAMFORMING_NOTIFY_NONE,
BEAMFORMING_NOTIFY_ADD,
BEAMFORMING_NOTIFY_DELETE,
BEAMFORMEE_NOTIFY_ADD_SU,
BEAMFORMEE_NOTIFY_DELETE_SU,
BEAMFORMEE_NOTIFY_ADD_MU,
BEAMFORMEE_NOTIFY_DELETE_MU,
BEAMFORMING_NOTIFY_RESET
};
enum beamforming_cap {
BEAMFORMING_CAP_NONE = 0x0,
BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP = BIT(9),
BEAMFORMEE_CAP = BIT(10),
};
enum sounding_mode {
SOUNDING_SW_VHT_TIMER = 0x0,
SOUNDING_SW_HT_TIMER = 0x1,
sounding_stop_all_timer = 0x2,
SOUNDING_HW_VHT_TIMER = 0x3,
SOUNDING_HW_HT_TIMER = 0x4,
SOUNDING_STOP_OID_TIMER = 0x5,
SOUNDING_AUTO_VHT_TIMER = 0x6,
SOUNDING_AUTO_HT_TIMER = 0x7,
SOUNDING_FW_VHT_TIMER = 0x8,
SOUNDING_FW_HT_TIMER = 0x9,
};
struct _RT_BEAMFORM_STAINFO {
u8 *ra;
u16 aid;
u16 mac_id;
u8 my_mac_addr[6];
/*WIRELESS_MODE wireless_mode;*/
enum channel_width bw;
enum beamforming_cap beamform_cap;
u8 ht_beamform_cap;
u16 vht_beamform_cap;
u8 cur_beamform;
u16 cur_beamform_vht;
};
struct _RT_BEAMFORMEE_ENTRY {
boolean is_used;
boolean is_txbf;
boolean is_sound;
u16 aid; /*Used to construct AID field of NDPA packet.*/
u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id; /*Used to fill Tx DESC*/
u8 my_mac_addr[6];
u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
enum channel_width sound_bw; /*Sounding band_width*/
u16 sound_period;
enum beamforming_cap beamform_entry_cap;
enum beamforming_entry_state beamform_entry_state;
boolean is_beamforming_in_progress;
/*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
/*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
/*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
u16 log_status_fail_cnt:5; /* 0~21 */
u16 default_csi_cnt:5; /* 0~21 */
u8 csi_matrix[327];
u16 csi_matrix_len;
u8 num_of_sounding_dim;
u8 comp_steering_num_of_bfer;
u8 su_reg_index;
/*For MU-MIMO*/
boolean is_mu_sta;
u8 mu_reg_index;
u8 gid_valid[8];
u8 user_position[16];
};
struct _RT_BEAMFORMER_ENTRY {
boolean is_used;
/*P_AID of BFer entry is probably not used*/
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id;
u8 my_mac_addr[6];
u8 mac_addr[6];
enum beamforming_cap beamform_entry_cap;
u8 num_of_sounding_dim;
u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/
u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/
u8 log_seq; /*Modified by Jeffery @2014-10-29*/
u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/
u16 log_success:2; /*Modified by Jeffery @2014-10-29*/
u8 su_reg_index;
/*For MU-MIMO*/
boolean is_mu_ap;
u8 gid_valid[8];
u8 user_position[16];
u16 aid;
};
struct _RT_SOUNDING_INFO {
u8 sound_idx;
enum channel_width sound_bw;
enum sounding_mode sound_mode;
u16 sound_period;
};
struct _RT_BEAMFORMING_OID_INFO {
u8 sound_oid_idx;
enum channel_width sound_oid_bw;
enum sounding_mode sound_oid_mode;
u16 sound_oid_period;
};
struct _RT_BEAMFORMING_INFO {
enum beamforming_cap beamform_cap;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
u8 beamformee_cur_idx;
struct phydm_timer_list beamforming_timer;
struct phydm_timer_list mu_timer;
struct _RT_SOUNDING_INFO sounding_info;
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
struct _HAL_TXBF_INFO txbf_info;
u8 sounding_sequence;
u8 beamformee_su_cnt;
u8 beamformer_su_cnt;
u32 beamformee_su_reg_maping;
u32 beamformer_su_reg_maping;
/*For MU-MINO*/
u8 beamformee_mu_cnt;
u8 beamformer_mu_cnt;
u32 beamformee_mu_reg_maping;
u8 mu_ap_index;
boolean is_mu_sounding;
u8 first_mu_bfee_index;
boolean is_mu_sounding_in_progress;
boolean dbg_disable_mu_tx;
boolean apply_v_matrix;
boolean snding3ss;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *source_adapter;
#endif
/* Control register */
u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */
u8 tx_bf_data_rate;
u8 last_usb_hub;
};
void
phydm_get_txbf_device_num(
void *dm_void,
u8 macid
);
struct _RT_NDPA_STA_INFO {
u16 aid:12;
u16 feedback_type:1;
u16 nc_index:3;
};
enum phydm_acting_type {
phydm_acting_as_ibss = 0,
phydm_acting_as_ap = 1
};
enum beamforming_cap
phydm_beamforming_get_entry_beam_cap_by_mac_id(
void *dm_void,
u8 mac_id
);
struct _RT_BEAMFORMEE_ENTRY *
phydm_beamforming_get_bfee_entry_by_addr(
void *dm_void,
u8 *RA,
u8 *idx
);
struct _RT_BEAMFORMER_ENTRY *
phydm_beamforming_get_bfer_entry_by_addr(
void *dm_void,
u8 *TA,
u8 *idx
);
void
phydm_beamforming_notify(
void *dm_void
);
boolean
phydm_acting_determine(
void *dm_void,
enum phydm_acting_type type
);
void
beamforming_enter(
void *dm_void,
u16 sta_idx
);
void
beamforming_leave(
void *dm_void,
u8 *RA
);
boolean
beamforming_start_fw(
void *dm_void,
u8 idx
);
void
beamforming_check_sounding_success(
void *dm_void,
boolean status
);
void
phydm_beamforming_end_sw(
void *dm_void,
boolean status
);
void
beamforming_timer_callback(
void *dm_void
);
void
phydm_beamforming_init(
void *dm_void
);
enum beamforming_cap
phydm_beamforming_get_beam_cap(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info
);
enum beamforming_cap
phydm_get_beamform_cap(
void *dm_void
);
boolean
beamforming_control_v1(
void *dm_void,
u8 *RA,
u8 AID,
u8 mode,
enum channel_width BW,
u8 rate
);
boolean
phydm_beamforming_control_v2(
void *dm_void,
u8 idx,
u8 mode,
enum channel_width BW,
u16 period
);
void
phydm_beamforming_watchdog(
void *dm_void
);
void
beamforming_sw_timer_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct phydm_timer_list *timer
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *function_context
#endif
);
boolean
beamforming_send_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW,
u8 q_idx
);
boolean
beamforming_send_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW,
u8 q_idx
);
#else
#define beamforming_gid_paid(adapter, tcb)
#define phydm_acting_determine(dm, type) false
#define beamforming_enter(dm, sta_idx)
#define beamforming_leave(dm, RA)
#define beamforming_end_fw(dm)
#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
#define beamforming_control_v2(dm, idx, mode, BW, period) true
#define phydm_beamforming_end_sw(dm, _status)
#define beamforming_timer_callback(dm)
#define phydm_beamforming_init(dm)
#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
#define beamforming_watchdog(dm)
#define phydm_beamforming_watchdog(dm)
#endif
#endif

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hal/phydm/phydm_cck_pd.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_SUPPORT_CCKPD
void
phydm_write_cck_cca_th_new_cs_ratio(
void *dm_void,
u8 cca_th,
u8 cca_th_aaa
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
PHYDM_DBG(dm, DBG_CCKPD, "[New] pd_th=0x%x, cs_ratio=0x%x\n\n", cca_th, cca_th_aaa);
if (cckpd_t->cur_cck_cca_thres != cca_th) {
cckpd_t->cur_cck_cca_thres = cca_th;
odm_set_bb_reg(dm, 0xa08, 0xf0000, cca_th);
cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
}
if (cckpd_t->cck_cca_th_aaa != cca_th_aaa) {
cckpd_t->cck_cca_th_aaa = cca_th_aaa;
odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cca_th_aaa);
cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
}
}
void
phydm_write_cck_cca_th(
void *dm_void,
u8 cca_th
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cca_th);
if (cckpd_t->cur_cck_cca_thres != cca_th) {
odm_write_1byte(dm, ODM_REG(CCK_CCA, dm), cca_th);
cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
}
cckpd_t->cur_cck_cca_thres = cca_th;
}
void
phydm_set_cckpd_val(
void *dm_void,
u32 *val_buf,
u8 val_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (val_len != 2) {
PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=2\n");
return;
}
/*val_buf[0]: 0xa0a*/
/*val_buf[1]: 0xaaa*/
if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) {
phydm_write_cck_cca_th_new_cs_ratio(dm, (u8)val_buf[0], (u8)val_buf[1]);
} else {
phydm_write_cck_cca_th(dm, (u8)val_buf[0]);
}
}
boolean
phydm_stop_cck_pd_th(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) {
PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n");
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#ifdef MCR_WIRELESS_EXTEND
phydm_write_cck_cca_th(dm, 0x43);
#endif
#endif
return true;
}
if (dm->pause_ability & ODM_BB_CCK_PD) {
PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n", dm->pause_lv_table.lv_cckpd);
return true;
}
#if 0/*(DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))*/
if (dm->ext_lna)
return true;
#endif
return false;
}
void
phydm_cckpd(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
u8 cur_cck_cca_th= cckpd_t->cur_cck_cca_thres;
if (dm->is_linked) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
/*Add hp_hw_id condition due to 22B LPS power consumption issue and [PCIE-1596]*/
if (dm->hp_hw_id && (dm->traffic_load == TRAFFIC_ULTRA_LOW))
cur_cck_cca_th = 0x40;
else if (dm->rssi_min > 35)
cur_cck_cca_th = 0xcd;
else if (dm->rssi_min > 20) {
if (cckpd_t->cck_fa_ma > 500)
cur_cck_cca_th = 0xcd;
else if (cckpd_t->cck_fa_ma < 250)
cur_cck_cca_th = 0x83;
} else {
if((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) && (cckpd_t->cck_fa_ma > 200))
cur_cck_cca_th = 0xc3; /*for ASUS OTA test*/
else
cur_cck_cca_th = 0x83;
}
#else /*ODM_AP*/
if (dig_t->cur_ig_value > 0x32)
cur_cck_cca_th = 0xed;
else if (dig_t->cur_ig_value > 0x2a)
cur_cck_cca_th = 0xdd;
else if (dig_t->cur_ig_value > 0x24)
cur_cck_cca_th = 0xcd;
else
cur_cck_cca_th = 0x83;
#endif
} else {
if (cckpd_t->cck_fa_ma > 1000)
cur_cck_cca_th = 0x83;
else if (cckpd_t->cck_fa_ma < 500)
cur_cck_cca_th = 0x40;
}
phydm_write_cck_cca_th(dm, cur_cck_cca_th);
/*PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cur_cck_cca_th);*/
}
void
phydm_cckpd_new_cs_ratio(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
u8 pd_th = 0, cs_ration = 0, cs_2r_offset = 0;
u8 igi_curr = dig_t->cur_ig_value;
u8 en_2rcca;
boolean is_update = true;
PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
en_2rcca = (u8)(odm_get_bb_reg(dm, 0xa2c, BIT(18)) && odm_get_bb_reg(dm, 0xa2c, BIT(22)));
if (dm->is_linked) {
if ((igi_curr > 0x38) && (dm->rssi_min > 32)) {
cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP * 2;
cs_2r_offset = 5;
pd_th = 0xd;
} else if ((igi_curr > 0x2a) && (dm->rssi_min > 32)) {
cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP;
cs_2r_offset = 4;
pd_th = 0xd;
} else if ((igi_curr > 0x24) || (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
cs_ration = dig_t->aaa_default + AAA_BASE;
cs_2r_offset = 3;
pd_th = 0xd;
} else if ((igi_curr <= 0x24) || (dm->rssi_min < 22)) {
if (cckpd_t->cck_fa_ma > 1000) {
cs_ration = dig_t->aaa_default + AAA_STEP;
cs_2r_offset = 1;
pd_th = 0x7;
} else if (cckpd_t->cck_fa_ma < 500) {
cs_ration = dig_t->aaa_default;
pd_th = 0x3;
} else {
is_update = false;
cs_ration = cckpd_t->cck_cca_th_aaa;
pd_th = cckpd_t->cur_cck_cca_thres;
}
}
} else {
if (cckpd_t->cck_fa_ma > 1000) {
cs_ration = dig_t->aaa_default + AAA_STEP;
cs_2r_offset = 1;
pd_th = 0x7;
} else if (cckpd_t->cck_fa_ma < 500) {
cs_ration = dig_t->aaa_default;
pd_th = 0x3;
} else {
is_update = false;
cs_ration = cckpd_t->cck_cca_th_aaa;
pd_th = cckpd_t->cur_cck_cca_thres;
}
}
if (en_2rcca)
cs_ration = (cs_ration >= cs_2r_offset) ? (cs_ration - cs_2r_offset) : 0;
PHYDM_DBG(dm, DBG_CCKPD,
"[New] cs_ratio=0x%x, pd_th=0x%x\n", cs_ration, pd_th);
if (is_update) {
cckpd_t->cur_cck_cca_thres = pd_th;
cckpd_t->cck_cca_th_aaa = cs_ration;
odm_set_bb_reg(dm, 0xa08, 0xf0000, pd_th);
odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cs_ration);
}
/*phydm_write_cck_cca_th_new_cs_ratio(dm, pd_th, cs_ration);*/
}
#endif
void
phydm_cck_pd_th(
void *dm_void
)
{
#ifdef PHYDM_SUPPORT_CCKPD
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fa_struct *fa_t= &dm->false_alm_cnt;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
u32 cnt_cck_fail_tmp = fa_t->cnt_cck_fail;
#ifdef PHYDM_TDMA_DIG_SUPPORT
struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
#endif
PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
if (phydm_stop_cck_pd_th(dm) == true)
return;
#ifdef PHYDM_TDMA_DIG_SUPPORT
cnt_cck_fail_tmp = (dm->original_dig_restore) ? (fa_t->cnt_cck_fail) : (fa_acc_t->cnt_cck_fail_1sec);
#endif
if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
cckpd_t->cck_fa_ma = cnt_cck_fail_tmp;
else {
cckpd_t->cck_fa_ma = ((cckpd_t->cck_fa_ma << 1) +
cckpd_t->cck_fa_ma + cnt_cck_fail_tmp) >> 2;
}
PHYDM_DBG(dm, DBG_CCKPD, "CCK FA=%d\n", cckpd_t->cck_fa_ma);
if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC)
phydm_cckpd_new_cs_ratio(dm);
else
phydm_cckpd(dm);
#endif
}
void
odm_pause_cck_packet_detection(
void *dm_void,
enum phydm_pause_type pause_type,
enum phydm_pause_level pause_lv,
u8 cck_pd_th
)
{
#ifdef PHYDM_SUPPORT_CCKPD
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
s8 max_level;
u8 i;
PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
if ((cckpd_t->pause_bitmap == 0) &&
(!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT)))) {
PHYDM_DBG(dm, DBG_CCKPD, "Return: not support\n");
return;
}
if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
PHYDM_DBG(dm, DBG_CCKPD, "Return: Wrong LV !\n");
return;
}
PHYDM_DBG(dm, DBG_CCKPD, "Set pause{Type, LV, val} = {%d, %d, 0x%x}\n",
pause_type, pause_lv, cck_pd_th);
PHYDM_DBG(dm, DBG_CCKPD, "pause LV=0x%x\n", cckpd_t->pause_bitmap);
for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n",
i, cckpd_t->pause_cckpd_value[i]);
}
switch (pause_type) {
case PHYDM_PAUSE:
{
/* Disable CCK PD */
dm->support_ability &= ~ODM_BB_CCK_PD;
PHYDM_DBG(dm, DBG_CCKPD, "Pause CCK PD th\n");
/* Backup original CCK PD threshold decided by CCK PD mechanism */
if (cckpd_t->pause_bitmap == 0) {
cckpd_t->cckpd_bkp = cckpd_t->cur_cck_cca_thres;
PHYDM_DBG(dm, DBG_CCKPD, "cckpd_bkp=0x%x\n",
cckpd_t->cckpd_bkp);
}
cckpd_t->pause_bitmap |= BIT(pause_lv); /* Update pause level */
cckpd_t->pause_cckpd_value[pause_lv] = cck_pd_th;
/* Write new CCK PD threshold */
if (BIT(pause_lv + 1) > cckpd_t->pause_bitmap) {
PHYDM_DBG(dm, DBG_CCKPD, "> ori pause LV=0x%x\n",
cckpd_t->pause_bitmap);
phydm_write_cck_cca_th(dm, cck_pd_th);
}
break;
}
case PHYDM_RESUME:
{
/* check if the level is illegal or not */
if ((cckpd_t->pause_bitmap & (BIT(pause_lv))) != 0) {
cckpd_t->pause_bitmap &= (~(BIT(pause_lv)));
cckpd_t->pause_cckpd_value[pause_lv] = 0;
PHYDM_DBG(dm, DBG_CCKPD, "Resume CCK PD\n");
} else {
PHYDM_DBG(dm, DBG_CCKPD, "Wrong resume LV\n");
break;
}
/* Resume CCKPD */
if (cckpd_t->pause_bitmap == 0) {
PHYDM_DBG(dm, DBG_CCKPD, "Revert bkp_CCKPD=0x%x\n",
cckpd_t->cckpd_bkp);
phydm_write_cck_cca_th(dm, cckpd_t->cckpd_bkp);
dm->support_ability |= ODM_BB_CCK_PD;/* Enable CCKPD */
break;
}
if (BIT(pause_lv) <= cckpd_t->pause_bitmap)
break;
/* Calculate the maximum level now */
for (max_level = (pause_lv - 1); max_level >= 0; max_level--) {
if (cckpd_t->pause_bitmap & BIT(max_level))
break;
}
/* write CCKPD of lower level */
phydm_write_cck_cca_th(dm, cckpd_t->pause_cckpd_value[max_level]);
PHYDM_DBG(dm, DBG_CCKPD, "Write CCKPD=0x%x for max_LV=%d\n",
cckpd_t->pause_cckpd_value[max_level], max_level);
break;
}
default:
PHYDM_DBG(dm, DBG_CCKPD, "Wrong type\n");
break;
}
PHYDM_DBG(dm, DBG_CCKPD, "New pause bitmap=0x%x\n",
cckpd_t->pause_bitmap);
for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n",
i, cckpd_t->pause_cckpd_value[i]);
}
#endif
}
void
phydm_cck_pd_init(
void *dm_void
)
{
#ifdef PHYDM_SUPPORT_CCKPD
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
cckpd_t->cur_cck_cca_thres = 0;
cckpd_t->cck_cca_th_aaa = 0;
cckpd_t->pause_bitmap = 0;
if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) {
dig_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000);
cckpd_t->cck_cca_th_aaa = dig_t->aaa_default;
cckpd_t->cur_cck_cca_thres = dig_t->a0a_default;
} else {
dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000);
cckpd_t->cur_cck_cca_thres = dig_t->a0a_default;
}
odm_memory_set(dm, cckpd_t->pause_cckpd_value, 0, PHYDM_PAUSE_MAX_NUM);
#endif
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_CCK_PD_H__
#define __PHYDM_CCK_PD_H__
#define CCK_PD_VERSION "1.0" /* 2017.05.09 Dino, Add phydm_cck_pd.h*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define AAA_BASE 4
#define AAA_STEP 2
#define CCK_FA_MA_RESET 0xffffffff
#define EXTEND_CCK_CCATH_AAA_IC (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |ODM_RTL8710B)
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
#ifdef PHYDM_SUPPORT_CCKPD
struct phydm_cckpd_struct {
u8 cur_cck_cca_thres; /*0xA0A*/
u8 cck_cca_th_aaa; /*0xAAA*/
u32 cck_fa_ma;
u8 cckpd_bkp;
u32 rvrt_val[2];
u8 pause_bitmap;/*will be removed*/
u8 pause_lv;
u8 pause_cckpd_value[PHYDM_PAUSE_MAX_NUM]; /*will be removed*/
};
#endif
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
phydm_set_cckpd_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
void
phydm_cck_pd_th(
void *dm_void
);
void
odm_pause_cck_packet_detection(
void *dm_void,
enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level,
u8 cck_pd_threshold
);
void
phydm_cck_pd_init(
void *dm_void
);
#endif

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hal/phydm/phydm_ccx.c Normal file
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384
hal/phydm/phydm_ccx.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define CCX_EN 1
#define MAX_ENV_MNTR_TIME 8 /*second*/
#define IGI_TO_NHM_TH_MULTIPLIER 2
#define MS_TO_4US_RATIO 250
#define CCA_CAP 14
#define CLM_MAX_REPORT_TIME 10
#define DEVIDER_ERROR 0xffff
#define CLM_PERIOD_MAX 65535
#define NHM_PERIOD_MAX 65534
#define NHM_TH_NUM 11 /*threshold number of NHM*/
#define NHM_RPT_NUM 12
#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM_threshold = IGI * 2*/
#define NTH_TH_2_RSSI(th) ((th >> 1) - 10)
/*FAHM*/
#define FAHM_INCLD_FA BIT(0)
#define FAHM_INCLD_CRC_OK BIT(1)
#define FAHM_INCLD_CRC_ER BIT(2)
#define NHM_SUCCESS BIT(0)
#define CLM_SUCCESS BIT(1)
#define FAHM_SUCCESS BIT(2)
#define ENV_MNTR_FAIL 0xff
/* 1 ============================================================
* 1 enumrate
* 1 ============================================================ */
enum phydm_clm_level {
CLM_RELEASE = 0,
CLM_LV_1 = 1, /* Low Priority function */
CLM_LV_2 = 2, /* Middle Priority function */
CLM_LV_3 = 3, /* High priority function (ex: Check hang function) */
CLM_LV_4 = 4, /* Debug function (the highest priority) */
CLM_MAX_NUM = 5
};
enum phydm_nhm_level {
NHM_RELEASE = 0,
NHM_LV_1 = 1, /* Low Priority function */
NHM_LV_2 = 2, /* Middle Priority function */
NHM_LV_3 = 3, /* High priority function (ex: Check hang function) */
NHM_LV_4 = 4, /* Debug function (the highest priority) */
NHM_MAX_NUM = 5
};
enum nhm_divider_opt_all {
NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/
NHM_VALID = 1, /*nhm SUM report = 255*/
NHM_CNT_INIT
};
enum nhm_setting {
SET_NHM_SETTING,
STORE_NHM_SETTING,
RESTORE_NHM_SETTING
};
enum nhm_inexclude_cca_all {
NHM_EXCLUDE_CCA = 0,
NHM_INCLUDE_CCA = 1,
NHM_CCA_INIT
};
enum nhm_inexclude_txon_all {
NHM_EXCLUDE_TXON = 0,
NHM_INCLUDE_TXON = 1,
NHM_TXON_INIT
};
enum nhm_application {
NHM_BACKGROUND = 0,/*default*/
NHM_ACS = 1,
IEEE_11K_HIGH = 2,
IEEE_11K_LOW = 3,
INTEL_XBOX = 4,
NHM_DBG = 5, /*manual trigger*/
};
enum clm_application {
CLM_BACKGROUND = 0,/*default*/
CLM_ACS = 1,
};
enum clm_monitor_mode {
CLM_DRIVER_MNTR = 1,
CLM_FW_MNTR = 2
};
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct env_trig_rpt {
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
};
struct env_mntr_rpt {
u8 nhm_ratio;
u8 nhm_result[NHM_RPT_NUM];
u8 clm_ratio;
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
};
struct nhm_para_info {
enum nhm_inexclude_txon_all incld_txon; /*Include TX on*/
enum nhm_inexclude_cca_all incld_cca; /*Include CCA*/
enum nhm_divider_opt_all div_opt; /*divider option*/
enum nhm_application nhm_app;
enum phydm_nhm_level nhm_lv;
u16 mntr_time; /*0~262 unit ms*/
};
struct clm_para_info {
enum clm_application clm_app;
enum phydm_clm_level clm_lv;
u16 mntr_time; /*0~262 unit ms*/
};
struct ccx_info {
u32 nhm_trigger_time;
u32 clm_trigger_time;
#ifdef NHM_SUPPORT
enum nhm_application nhm_app;
enum nhm_inexclude_txon_all nhm_include_txon;
enum nhm_inexclude_cca_all nhm_include_cca;
enum nhm_divider_opt_all nhm_divider_opt;
/*Report*/
u8 nhm_th[NHM_TH_NUM];
u8 nhm_result[NHM_RPT_NUM];
u16 nhm_period; /* 4us per unit */
u8 nhm_igi;
u8 nhm_manual_ctrl;
u8 nhm_ratio; /*1% per nuit, it means the interference igi can't overcome.*/
u8 nhm_rpt_sum;
u16 nhm_duration; /*Real time of NHM_VALID */
u8 nhm_set_lv;
boolean nhm_ongoing;
u8 nhm_rpt_stamp;
#endif
#ifdef CLM_SUPPORT
enum clm_application clm_app;
u8 clm_manual_ctrl;
u8 clm_set_lv;
boolean clm_ongoing;
u16 clm_period; /* 4us per unit */
u16 clm_result;
u8 clm_ratio;
u32 clm_fw_result_acc;
u8 clm_fw_result_cnt;
enum clm_monitor_mode clm_mntr_mode;
u8 clm_rpt_stamp;
#endif
#ifdef FAHM_SUPPORT
boolean fahm_ongoing;
u8 env_mntr_igi;
u8 fahm_nume_sel; /*fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
u8 fahm_denum_sel; /*fahm_denumerator_sel: select {FA, CRCOK, CRC_fail} */
u16 fahm_period; /*unit: 4us*/
#endif
#if 1 /*Will remove*/
/*Previous Settings*/
enum nhm_inexclude_txon_all nhm_inexclude_txon_restore;
enum nhm_inexclude_cca_all nhm_inexclude_cca_restore;
u8 nhm_th_restore[NHM_TH_NUM];
u16 nhm_period_restore;/* 4us per unit */
u8 echo_igi; /* nhm_result comes from this igi */
#endif
};
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
void
phydm_get_nhm_result(
void *dm_void
);
void
phydm_set_nhm_th_by_igi(
void *dm_void,
u8 igi
);
void
phydm_nhm_setting(
void *dm_void,
u8 nhm_setting
);
void
phydm_ccx_monitor_trigger(
void *dm_void,
u16 monitor_time
);
void
phydm_ccx_monitor_result(
void *dm_void
);
#ifdef FAHM_SUPPORT
void
phydm_fahm_init(
void *dm_void
);
void
phydm_fahm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
/*NHM*/
#ifdef NHM_SUPPORT
void
phydm_nhm_trigger(
void *dm_void
);
void
phydm_nhm_init(
void *dm_void
);
void
phydm_nhm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
/*CLM*/
#ifdef CLM_SUPPORT
void
phydm_clm_c2h_report_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
void
phydm_clm_h2c(
void *dm_void,
u16 obs_time,
u8 fw_clm_en
);
void
phydm_clm_setting(
void *dm_void,
u16 clm_period
);
void
phydm_clm_trigger(
void *dm_void
);
boolean
phydm_clm_check_rdy(
void *dm_void
);
void
phydm_clm_get_utility(
void *dm_void
);
boolean
phydm_clm_get_result(
void *dm_void
);
u8
phydm_clm_mntr_set(
void *dm_void,
struct clm_para_info *clm_para
);
void
phydm_set_clm_mntr_mode(
void *dm_void,
enum clm_monitor_mode mode
);
void
phydm_clm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
u8
phydm_env_mntr_trigger(
void *dm_void,
struct nhm_para_info *nhm_para,
struct clm_para_info *clm_para,
struct env_trig_rpt *rpt
);
u8
phydm_env_mntr_result(
void *dm_void,
struct env_mntr_rpt *rpt
);
void
phydm_env_mntr_watchdog(
void *dm_void
);
void
phydm_env_monitor_init(
void *dm_void
);
void
phydm_env_mntr_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void
phydm_set_crystal_cap(
void *dm_void,
u8 crystal_cap
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
if (cfo_track->crystal_cap == crystal_cap)
return;
crystal_cap = crystal_cap & 0x3F;
cfo_track->crystal_cap = crystal_cap;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
#if (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6)));
#endif
}
#if (RTL8812A_SUPPORT == 1)
else if (dm->support_ic_type & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8703B_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8723D_SUPPORT == 1)
else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) {
/* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8814A_SUPPORT == 1)
else if (dm->support_ic_type & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
}
#endif
#if (RTL8710B_SUPPORT == 1)
else if (dm->support_ic_type & (ODM_RTL8710B)) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
HAL_SetSYSOnReg((PADAPTER)dm->adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6)));
#endif
}
#endif
PHYDM_DBG(dm, DBG_CFO_TRK, "Set rystal_cap = 0x%x\n", cfo_track->crystal_cap);
}
u8
phydm_get_default_crytaltal_cap(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 crystal_cap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
crystal_cap = rtlefuse->crystalcap;
#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
crystal_cap = hal_data->crystal_cap;
#else
struct rtl8192cd_priv *priv = dm->priv;
if (priv->pmib->dot11RFEntry.xcap > 0)
crystal_cap = priv->pmib->dot11RFEntry.xcap;
#endif
crystal_cap = crystal_cap & 0x3f;
return crystal_cap;
}
void
phydm_set_atc_status(
void *dm_void,
boolean atc_status
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
if (cfo_track->is_atc_status == atc_status)
return;
odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm), atc_status);
cfo_track->is_atc_status = atc_status;
}
boolean
phydm_get_atc_status(
void *dm_void
)
{
boolean atc_status;
struct dm_struct *dm = (struct dm_struct *)dm_void;
atc_status = (boolean)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm));
return atc_status;
}
void
phydm_cfo_tracking_reset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
cfo_track->def_x_cap = phydm_get_default_crytaltal_cap(dm);
cfo_track->is_adjust = true;
if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n", cfo_track->crystal_cap);
} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n", cfo_track->crystal_cap);
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
phydm_set_atc_status(dm, true);
#endif
}
void
phydm_cfo_tracking_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
cfo_track->def_x_cap = cfo_track->crystal_cap = phydm_get_default_crytaltal_cap(dm);
cfo_track->is_atc_status = phydm_get_atc_status(dm);
cfo_track->is_adjust = true;
PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init()=========>\n");
PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", cfo_track->is_atc_status, cfo_track->def_x_cap);
#if RTL8822B_SUPPORT
/* Crystal cap. control by WiFi */
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
#endif
#if RTL8821C_SUPPORT
/* Crystal cap. control by WiFi */
if (dm->support_ic_type & ODM_RTL8821C)
odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
#endif
}
void
phydm_cfo_tracking(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
s32 cfo_avg = 0, cfo_path_sum = 0; /*avg among each path*/
u32 cfo_rpt_sum, cfo_khz_avg[4] = {0};
s8 crystal_cap = cfo_track->crystal_cap;
u8 i, valid_path_cnt = 0;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) {
return;
}
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
if (!dm->is_linked || !dm->is_one_entry_only) {
phydm_cfo_tracking_reset(dm);
PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked = %d, one_entry_only = %d\n",
dm->is_linked, dm->is_one_entry_only);
} else {
/* No new packet */
if (cfo_track->packet_count == cfo_track->packet_count_pre) {
PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
return;
}
cfo_track->packet_count_pre = cfo_track->packet_count;
/*Calculate CFO */
for (i = 0; i < dm->num_rf_path; i++) {
if (cfo_track->CFO_cnt[i] == 0)
continue;
valid_path_cnt++;
cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(((cfo_track->CFO_tail[i] < 0) ? (0 - cfo_track->CFO_tail[i]) : cfo_track->CFO_tail[i]));
cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i];
PHYDM_DBG(dm, DBG_CFO_TRK, "[Path-%d] CFO_sum = (( %d )), cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
i, cfo_rpt_sum, cfo_track->CFO_cnt[i], ((cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i]);
}
for (i = 0; i < valid_path_cnt; i++) {
if (cfo_track->CFO_tail[i] < 0) {
cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
} else
cfo_path_sum += (s32)cfo_khz_avg[i];
}
if (valid_path_cnt >= 2)
cfo_avg = cfo_path_sum / valid_path_cnt;
else
cfo_avg = cfo_path_sum;
cfo_track->CFO_ave_pre = cfo_avg;
PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt = ((%d)), CFO_avg_path=((%d kHz))\n", valid_path_cnt, cfo_avg);
/*reset counter*/
for (i = 0; i < dm->num_rf_path; i++) {
cfo_track->CFO_tail[i] = 0;
cfo_track->CFO_cnt[i] = 0;
}
/* To adjust crystal cap or not */
if (cfo_track->is_adjust == false) {
if (cfo_avg > CFO_TRK_ENABLE_TH || cfo_avg < (-CFO_TRK_ENABLE_TH))
cfo_track->is_adjust = true;
} else {
if (cfo_avg < CFO_TRK_STOP_TH && cfo_avg > (-CFO_TRK_STOP_TH))
cfo_track->is_adjust = false;
}
#ifdef ODM_CONFIG_BT_COEXIST
/*BT case: Disable CFO tracking */
if (dm->bt_info_table.is_bt_enabled) {
cfo_track->is_adjust = false;
phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "Disable CFO tracking for BT\n");
}
#endif
/*Adjust Crystal Cap. */
if (cfo_track->is_adjust) {
if (cfo_avg > CFO_TRK_STOP_TH)
crystal_cap += 1;
else if (cfo_avg < (-CFO_TRK_STOP_TH))
crystal_cap -=1;
if (crystal_cap > 0x3f)
crystal_cap = 0x3f;
else if (crystal_cap < 0)
crystal_cap = 0;
phydm_set_crystal_cap(dm, (u8)crystal_cap);
}
PHYDM_DBG(dm, DBG_CFO_TRK, "Crystal cap{Current, Default}={0x%x, 0x%x}\n\n",
cfo_track->crystal_cap, cfo_track->def_x_cap);
/* Dynamic ATC switch */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC) {
phydm_set_atc_status(dm, false);
PHYDM_DBG(dm, DBG_CFO_TRK, "Disable ATC\n");
} else {
phydm_set_atc_status(dm, true);
PHYDM_DBG(dm, DBG_CFO_TRK, "Enable ATC\n");
}
}
#endif
}
}
void
phydm_parsing_cfo(
void *dm_void,
void *pktinfo_void,
s8 *pcfotail,
u8 num_ss
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
u8 i;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (pktinfo->is_packet_match_bssid)
#else
if (pktinfo->station_id != 0)
#endif
{
if (num_ss > dm->num_rf_path) /*For fool proof*/
num_ss = dm->num_rf_path;
/*PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss = ((%d)), dm->num_rf_path = ((%d))\n", num_ss, dm->num_rf_path);*/
/* 3 Update CFO report for path-A & path-B */
/* Only paht-A and path-B have CFO tail and short CFO */
for (i = 0; i < num_ss; i++) {
cfo_track->CFO_tail[i] += pcfotail[i];
cfo_track->CFO_cnt[i]++;
/*PHYDM_DBG(dm, DBG_CFO_TRK, "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
pktinfo->station_id, i, pktinfo->data_rate, pcfotail[i], cfo_track->CFO_tail[i], cfo_track->CFO_cnt[i]);
*/
}
/* 3 Update packet counter */
if (cfo_track->packet_count == 0xffffffff)
cfo_track->packet_count = 0;
else
cfo_track->packet_count++;
}
}

71
hal/phydm/phydm_cfotracking.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
#define CFO_TRK_ENABLE_TH 20 /* (kHz) enable CFO Tracking threshold*/
#define CFO_TRK_STOP_TH 10 /* (kHz) disable CFO Tracking threshold*/
#define CFO_TH_ATC 80 /* kHz */
struct phydm_cfo_track_struct {
boolean is_atc_status;
boolean is_adjust; /*already modify crystal cap*/
u8 crystal_cap;
u8 def_x_cap;
s32 CFO_tail[4];
u32 CFO_cnt[4];
s32 CFO_ave_pre;
u32 packet_count;
u32 packet_count_pre;
};
void
phydm_set_crystal_cap(
void *dm_void,
u8 crystal_cap
);
void
phydm_cfo_tracking_init(
void *dm_void
);
void
phydm_cfo_tracking(
void *dm_void
);
void
phydm_parsing_cfo(
void *dm_void,
void *pktinfo_void,
s8 *pcfotail,
u8 num_ss
);
#endif

3786
hal/phydm/phydm_debug.c Normal file
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392
hal/phydm/phydm_debug.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/
#define DEBUG_VERSION "1.4" /*2017.03.13 Dino*/
/* -----------------------------------------------------------------------------
* Define the debug levels
*
* 1. DBG_TRACE and DBG_LOUD are used for normal cases.
* So that, they can help SW engineer to develope or trace states changed
* and also help HW enginner to trace every operation to and from HW,
* e.g IO, Tx, Rx.
*
* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
* which help us to debug SW or HW.
*
* -----------------------------------------------------------------------------
*
* Never used in a call to ODM_RT_TRACE()!
* */
#define ODM_DBG_OFF 1
/*
* Fatal bug.
* For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
* resource allocation failed, unexpected HW behavior, HW BUG and so on.
* */
#define ODM_DBG_SERIOUS 2
/*
* Abnormal, rare, or unexpeted cases.
* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
* */
#define ODM_DBG_WARNING 3
/*
* Normal case with useful information about current SW or HW state.
* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
* SW protocol state change, dynamic mechanism state change and so on.
* */
#define ODM_DBG_LOUD 4
/*
* Normal case with detail execution flow or information.
* */
#define ODM_DBG_TRACE 5
/*FW DBG MSG*/
#define RATE_DECISION 1
#define INIT_RA_TABLE 2
#define RATE_UP 4
#define RATE_DOWN 8
#define TRY_DONE 16
#define RA_H2C 32
#define F_RATE_AP_RPT 64
#define DBC_FW_CLM 9
/* -----------------------------------------------------------------------------
* Define the tracing components
*
* -----------------------------------------------------------------------------
*BB FW Functions*/
#define PHYDM_FW_COMP_RA BIT(0)
#define PHYDM_FW_COMP_MU BIT(1)
#define PHYDM_FW_COMP_PATH_DIV BIT(2)
#define PHYDM_FW_COMP_PT BIT(3)
/*------------------------Export Marco Definition---------------------------*/
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
extern VOID DCMD_Printf(const char *pMsg);
#define pr_debug DbgPrint
#define dcmd_printf DCMD_Printf
#define dcmd_scanf DCMD_Scanf
#define RT_PRINTK pr_debug
#define PRINT_MAX_SIZE 512
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#undef pr_debug
#define pr_debug printk
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_TRACE(adapter, comp, drv_level, fmt, args...) \
RTW_INFO(fmt, ## args)
#else
#define pr_debug panic_printk
/*#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & (dm->debug_components)) { \
pr_debug("[PHYDM] "); \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
int __i; \
u8 *__ptr = (u8 *)addr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
pr_debug("\n"); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
DbgPrint("[PHYDM] %s", buf);
}
static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*DbgPrint("DM Print Fail\n");*/
return;
}
DbgPrint("%s", buf);
}
#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) do {\
if ((comp) & p_dm->debug_components) { \
\
int __i; \
u8 *__ptr = (u8 *)ptr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
pr_debug("\n"); \
} \
} while (0)
#else
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & (dm->debug_components)) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " fmt, ##args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " title_str "%pM\n", \
addr); \
} \
} while (0)
#endif
#define ODM_RT_TRACE(dm, comp, level, fmt)
#else
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{}
static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
{}
#else
#define PHYDM_DBG(dm, comp, fmt)
#define PHYDM_DBG_F(dm, comp, fmt)
#endif
#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
#define ODM_RT_TRACE(dm, comp, level, fmt)
#endif
#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define PHYDM_DBGPRINT 0
#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z)
#define PHYDM_VAST_INFO_SNPRINTF PDM_SNPF
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(msg) \
do {\
rsprintf msg;\
pr_debug("%s", output);\
} while (0)
#else
static __inline void PDM_SNPF(u32 out_len, u32 used, char * buff, int len, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*DbgPrint("DM Print Fail\n");*/
return;
}
DCMD_Printf(buf);
}
#endif /*#if (PHYDM_DBGPRINT == 1)*/
#else /*(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
#define PHYDM_DBGPRINT 0
#else
#define PHYDM_DBGPRINT 1
#endif
#define MAX_ARGC 20
#define MAX_ARGV 16
#define DCMD_DECIMAL "%d"
#define DCMD_CHAR "%c"
#define DCMD_HEX "%x"
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
#define PHYDM_VAST_INFO_SNPRINTF(out_len, used, buff, len, fmt, args...) \
do { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
} while (0)
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
snprintf(buff, len, fmt, ##args); \
pr_debug("%s", output); \
} while (0)
#else
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
if (out_len > used) \
used += snprintf(buff, len, fmt, ##args); \
} while (0)
#endif
#endif
void phydm_init_debug_setting(struct dm_struct *dm);
void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
void phydm_release_bb_dbg_port(void *dm_void);
u32 phydm_get_bb_dbg_port_value(void *dm_void);
void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
void phydm_rx_rate_distribution(void *dm_void);
void phydm_get_avg_phystatus_val(void *dm_void);
void phydm_get_phy_statistic(void *dm_void);
void phydm_basic_dbg_message(void *dm_void);
void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
u32 *_out_len);
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
char *output, u32 out_len);
#endif
void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
u8 flag, char *output, u32 out_len);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_sbd_check(
struct dm_struct *dm
);
void phydm_sbd_callback(
struct phydm_timer_list *timer
);
void phydm_sbd_workitem_callback(
void *context
);
#endif
void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
u32 fw_debug_component, u32 monitor_mode, u32 macid);
void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
#endif /* __ODM_DBG_H__ */

689
hal/phydm/phydm_dfs.c Normal file
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@@ -0,0 +1,689 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*
============================================================
include files
============================================================
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if defined(CONFIG_PHYDM_DFS_MASTER)
boolean phydm_dfs_is_meteorology_channel(void *dm_void){
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 c_channel = *dm->channel;
u8 band_width = *dm->band_width;
return ( (band_width == CHANNEL_WIDTH_80 && (c_channel) >= 116 && (c_channel) <= 128) ||
(band_width == CHANNEL_WIDTH_40 && (c_channel) >= 116 && (c_channel) <= 128) ||
(band_width == CHANNEL_WIDTH_20 && (c_channel) >= 120 && (c_channel) <= 128) );
}
void phydm_radar_detect_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_set_bb_reg(dm, 0x924, BIT(15), 0);
odm_set_bb_reg(dm, 0x924, BIT(15), 1);
}
void phydm_radar_detect_disable(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_set_bb_reg(dm, 0x924, BIT(15), 0);
PHYDM_DBG(dm, DBG_DFS, "\n");
}
static void phydm_radar_detect_with_dbg_parm(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_set_bb_reg(dm, 0x918, MASKDWORD, dm->radar_detect_reg_918);
odm_set_bb_reg(dm, 0x91c, MASKDWORD, dm->radar_detect_reg_91c);
odm_set_bb_reg(dm, 0x920, MASKDWORD, dm->radar_detect_reg_920);
odm_set_bb_reg(dm, 0x924, MASKDWORD, dm->radar_detect_reg_924);
}
/* Init radar detection parameters, called after ch, bw is set */
void phydm_radar_detect_enable(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
u8 region_domain = dm->dfs_region_domain;
u8 c_channel = *dm->channel;
u8 band_width = *dm->band_width;
u8 enable = 0;
PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
goto exit;
}
if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
odm_set_bb_reg(dm, 0x814, 0x3fffffff, 0x04cc4d10);
odm_set_bb_reg(dm, 0x834, MASKBYTE0, 0x06);
if (dm->radar_detect_dbg_parm_en) {
phydm_radar_detect_with_dbg_parm(dm);
enable = 1;
goto exit;
}
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c17ecdf);
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500);
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0fa21a20);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0f69204);
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67234);
if (c_channel >= 52 && c_channel <= 64) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16ecdf);
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0f141a20);
} else {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf);
if (band_width == CHANNEL_WIDTH_20)
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64721a20);
else
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68721a20);
}
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf);
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67231);
if (band_width == CHANNEL_WIDTH_20)
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64741a20);
else
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68741a20);
} else {
/* not supported */
PHYDM_DBG(dm, DBG_DFS, "Unsupported dfs_region_domain:%d\n", region_domain);
goto exit;
}
} else if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
odm_set_bb_reg(dm, 0x814, 0x3fffffff, 0x04cc4d10);
odm_set_bb_reg(dm, 0x834, MASKBYTE0, 0x06);
/* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
if (band_width == CHANNEL_WIDTH_20)
odm_set_bb_reg(dm, 0x1984, BIT(26), 1);
else
odm_set_bb_reg(dm, 0x1984, BIT(26), 0);
}
if (dm->radar_detect_dbg_parm_en) {
phydm_radar_detect_with_dbg_parm(dm);
enable = 1;
goto exit;
}
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf);
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500);
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0fa21a20);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0f57204);
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67234);
if (c_channel >= 52 && c_channel <= 64) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16ecdf);
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0f141a20);
} else {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c166cdf);
if (band_width == CHANNEL_WIDTH_20)
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64721a20);
else
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68721a20);
}
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c166cdf);
odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500);
odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67231);
if (band_width == CHANNEL_WIDTH_20)
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64741a20);
else
odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68741a20);
} else {
/* not supported */
PHYDM_DBG(dm, DBG_DFS, "Unsupported dfs_region_domain:%d\n", region_domain);
goto exit;
}
} else {
/* not supported IC type*/
PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n", dm->support_ic_type);
goto exit;
}
enable = 1;
dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, 0x91c, 0x000000ff);
dfs->pwdb_th = (u8)odm_get_bb_reg(dm, 0x918, 0x00001f00);
dfs->peak_th = (u8)odm_get_bb_reg(dm, 0x918, 0x00030000);
dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, 0x920, 0x000f0000);
dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, 0x920, 0x00f00000);
dfs->peak_window = (u8)odm_get_bb_reg(dm, 0x920, 0x00000300);
dfs->nb2wb_th = (u8)odm_get_bb_reg(dm, 0x920, 0x0000e000);
phydm_dfs_parameter_init(dm);
exit:
if (enable) {
phydm_radar_detect_reset(dm);
PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel, band_width);
} else
phydm_radar_detect_disable(dm);
}
void phydm_dfs_parameter_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
u8 i;
dfs->fa_mask_th = 30;
dfs->det_print = 1;
dfs->det_print2 = 0;
dfs->st_l2h_min = 0x20;
dfs->st_l2h_max = 0x4e;
dfs->pwdb_scalar_factor = 12;
dfs->pwdb_th = 8;
for (i = 0 ; i < 5 ; i++) {
dfs->pulse_flag_hist[i] = 0;
dfs->radar_det_mask_hist[i] = 0;
dfs->fa_inc_hist[i] = 0;
}
}
void phydm_dfs_dynamic_setting(
void *dm_void
){
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
u8 peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0;
u8 peak_window_cur=0, nb2wb_th_cur=0;
u8 region_domain = dm->dfs_region_domain;
u8 c_channel = *dm->channel;
if (dm->rx_tp <= 2) {
dfs->idle_mode = 1;
if(dfs->force_TP_mode)
dfs->idle_mode = 0;
} else{
dfs->idle_mode = 0;
}
if ((dfs->idle_mode == 1)) { /*idle (no traffic)*/
peak_th_cur = 3;
short_pulse_cnt_th_cur = 6;
long_pulse_cnt_th_cur = 13;
peak_window_cur = 2;
nb2wb_th_cur = 6;
three_peak_opt_cur = 1;
three_peak_th2_cur = 2;
if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
if ((c_channel >= 52) && (c_channel <= 64)) {
short_pulse_cnt_th_cur = 14;
long_pulse_cnt_th_cur = 15;
nb2wb_th_cur = 3;
three_peak_th2_cur = 0;
} else {
short_pulse_cnt_th_cur = 6;
nb2wb_th_cur = 3;
three_peak_th2_cur = 0;
long_pulse_cnt_th_cur = 10;
}
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
three_peak_th2_cur = 0;
} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
long_pulse_cnt_th_cur = 15;
if (phydm_dfs_is_meteorology_channel(dm)) {/*need to add check cac end condition*/
peak_th_cur = 2;
nb2wb_th_cur = 3;
three_peak_opt_cur = 1;
three_peak_th2_cur = 0;
short_pulse_cnt_th_cur = 7;
} else {
three_peak_opt_cur = 1;
three_peak_th2_cur = 0;
short_pulse_cnt_th_cur = 7;
nb2wb_th_cur = 3;
}
} else /*default: FCC*/
three_peak_th2_cur = 0;
} else { /*in service (with TP)*/
peak_th_cur = 2;
short_pulse_cnt_th_cur = 6;
long_pulse_cnt_th_cur = 9;
peak_window_cur = 2;
nb2wb_th_cur = 3;
three_peak_opt_cur = 1;
three_peak_th2_cur = 2;
if(region_domain == PHYDM_DFS_DOMAIN_MKK){
if ((c_channel >= 52) && (c_channel <= 64)) {
long_pulse_cnt_th_cur = 15;
short_pulse_cnt_th_cur = 5; /*for high duty cycle*/
three_peak_th2_cur = 0;
}
else {
three_peak_opt_cur = 0;
three_peak_th2_cur = 0;
long_pulse_cnt_th_cur = 8;
}
}
else if(region_domain == PHYDM_DFS_DOMAIN_FCC){
}
else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){
long_pulse_cnt_th_cur = 15;
short_pulse_cnt_th_cur = 5;
three_peak_opt_cur = 0;
}
}
}
boolean
phydm_radar_detect_dm_check(
void *dm_void
){
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
u8 region_domain = dm->dfs_region_domain, index = 0;
u16 i = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0, total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0, max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0;
u16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0, ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0, leg_crc_ok_cnt_inc = 0;
u16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0, short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0, long_pulse_cnt_inc = 0, total_pulse_count_inc = 0;
u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0, reg920_value = 0, reg924_value = 0;
boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0, fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0, radar_detected = 0;
u8 st_l2h_new = 0, fa_mask_th = 0, sum = 0;
u8 c_channel = *dm->channel;
/*Get FA count during past 100ms*/
fa_count_cur = (u16)odm_get_bb_reg(dm, 0xf48, 0x0000ffff);
if (dfs->fa_count_pre == 0)
fa_count_inc = 0;
else if (fa_count_cur >= dfs->fa_count_pre)
fa_count_inc = fa_count_cur - dfs->fa_count_pre;
else
fa_count_inc = fa_count_cur;
dfs->fa_count_pre = fa_count_cur;
dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;
for (i=0; i<5; i++) {
total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
if (dfs->fa_inc_hist[i] > max_fa_in_hist)
max_fa_in_hist = dfs->fa_inc_hist[i];
}
if (dfs->mask_idx >= 2)
index = dfs->mask_idx - 2;
else
index = 5 + dfs->mask_idx - 2;
if (index == 0)
pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[index+1] + dfs->fa_inc_hist[4];
else if (index == 4)
pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[0] + dfs->fa_inc_hist[index-1];
else
pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[index+1] + dfs->fa_inc_hist[index-1];
/*Get VHT CRC32 ok count during past 100ms*/
vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf0c, 0x00003fff);
if (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre)
vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur - dfs->vht_crc_ok_cnt_pre;
else
vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur;
dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur;
/*Get HT CRC32 ok count during past 100ms*/
ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf10, 0x00003fff);
if (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre)
ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre;
else
ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur;
dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur;
/*Get Legacy CRC32 ok count during past 100ms*/
leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf14, 0x00003fff);
if (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre)
leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre;
else
leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur;
dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur;
if ((vht_crc_ok_cnt_cur == 0x3fff) ||
(ht_crc_ok_cnt_cur == 0x3fff) ||
(leg_crc_ok_cnt_cur == 0x3fff)) {
odm_set_bb_reg(dm, 0xb58, BIT(0), 1);
odm_set_bb_reg(dm, 0xb58, BIT(0), 0);
}
total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc + ht_crc_ok_cnt_inc + leg_crc_ok_cnt_inc;
/*Get short pulse count, need carefully handle the counter overflow*/
regf98_value = odm_get_bb_reg(dm, 0xf98, 0xffffffff);
short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre)
short_pulse_cnt_inc = short_pulse_cnt_cur - dfs->short_pulse_cnt_pre;
else
short_pulse_cnt_inc = short_pulse_cnt_cur;
dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
/*Get long pulse count, need carefully handle the counter overflow*/
long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre)
long_pulse_cnt_inc = long_pulse_cnt_cur - dfs->long_pulse_cnt_pre;
else
long_pulse_cnt_inc = long_pulse_cnt_cur;
dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
if (dfs->det_print){
PHYDM_DBG(dm, DBG_DFS, "=====================================================================\n");
PHYDM_DBG(dm, DBG_DFS, "Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n",
total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc, ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc);
PHYDM_DBG(dm, DBG_DFS, "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
dfs->igi_cur, dfs->st_l2h_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc);
PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n", dm->rx_tp);
reg918_value = odm_get_bb_reg(dm, 0x918, 0xffffffff);
reg91c_value = odm_get_bb_reg(dm, 0x91c, 0xffffffff);
reg920_value = odm_get_bb_reg(dm, 0x920, 0xffffffff);
reg924_value = odm_get_bb_reg(dm, 0x924, 0xffffffff);
PHYDM_DBG(dm, DBG_DFS, "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value);
PHYDM_DBG(dm, DBG_DFS, "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d\n", region_domain, dfs->dbg_mode, dfs->idle_mode);
}
tri_short_pulse = (regf98_value & BIT(17))? 1 : 0;
tri_long_pulse = (regf98_value & BIT(19))? 1 : 0;
if(tri_short_pulse)
radar_type = 0;
else if(tri_long_pulse)
radar_type = 1;
if (tri_short_pulse) {
odm_set_bb_reg(dm, 0x924, BIT(15), 0);
odm_set_bb_reg(dm, 0x924, BIT(15), 1);
}
if (tri_long_pulse) {
odm_set_bb_reg(dm, 0x924, BIT(15), 0);
odm_set_bb_reg(dm, 0x924, BIT(15), 1);
if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
if ((c_channel >= 52) && (c_channel <= 64)) {
tri_long_pulse = 0;
}
}
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
tri_long_pulse = 0;
}
}
st_l2h_new = dfs->st_l2h_cur;
dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
/* PSD(not ready) */
fault_flag_det = 0;
fault_flag_psd = 0;
fa_flag = 0;
if(region_domain == PHYDM_DFS_DOMAIN_ETSI){
fa_mask_th = dfs->fa_mask_th + 20;
}
else{
fa_mask_th = dfs->fa_mask_th;
}
if (max_fa_in_hist >= fa_mask_th || total_fa_in_hist >= fa_mask_th || pre_post_now_acc_fa_in_hist >= fa_mask_th || (dfs->igi_cur >= 0x30)){
st_l2h_new = dfs->st_l2h_max;
dfs->radar_det_mask_hist[index] = 1;
if (dfs->pulse_flag_hist[index] == 1){
dfs->pulse_flag_hist[index] = 0;
if (dfs->det_print2){
PHYDM_DBG(dm, DBG_DFS, "Radar is masked : FA mask\n");
}
}
fa_flag = 1;
} else {
dfs->radar_det_mask_hist[index] = 0;
}
if (dfs->det_print) {
PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
for (i=0; i<5; i++)
PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->radar_det_mask_hist[i]);
PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
for (i=0; i<5; i++)
PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
for (i=0; i<5; i++)
PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
PHYDM_DBG(dm, DBG_DFS,
"\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ", fa_mask_th, max_fa_in_hist, total_fa_in_hist, pre_post_now_acc_fa_in_hist);
}
sum = 0;
for (k=0; k<5; k++) {
if (dfs->radar_det_mask_hist[k] == 1)
sum++;
}
if (dfs->mask_hist_checked <= 5)
dfs->mask_hist_checked++;
if ((dfs->mask_hist_checked >= 5) && dfs->pulse_flag_hist[index])
{
if (sum <= 2)
{
radar_detected = 1 ;
PHYDM_DBG(dm, DBG_DFS, "Detected type %d radar signal!\n", radar_type);
}
else {
fault_flag_det = 1;
if (dfs->det_print2){
PHYDM_DBG(dm, DBG_DFS, "Radar is masked : mask_hist large than thd\n");
}
}
}
dfs->mask_idx++;
if (dfs->mask_idx == 5)
dfs->mask_idx = 0;
if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) {
if (dfs->igi_cur < 0x30) {
st_l2h_new = dfs->st_l2h_min;
}
}
if ((st_l2h_new != dfs->st_l2h_cur)) {
if (st_l2h_new < dfs->st_l2h_min) {
dfs->st_l2h_cur = dfs->st_l2h_min;
}
else if (st_l2h_new > dfs->st_l2h_max)
dfs->st_l2h_cur = dfs->st_l2h_max;
else
dfs->st_l2h_cur = st_l2h_new;
odm_set_bb_reg(dm, 0x91c, 0xff, dfs->st_l2h_cur);
dfs->pwdb_th = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)/2 + dfs->pwdb_scalar_factor;
dfs->pwdb_th = MAX_2(dfs->pwdb_th, (int)dfs->pwdb_th); /*limit the pwdb value to absoulte lower bound 8*/
dfs->pwdb_th = MIN_2(dfs->pwdb_th, 0x1f); /*limit the pwdb value to absoulte upper bound 0x1f*/
odm_set_bb_reg(dm, 0x918, 0x00001f00, dfs->pwdb_th);
}
if (dfs->det_print) {
PHYDM_DBG(dm, DBG_DFS,
"fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n", fault_flag_det, fault_flag_psd, radar_detected);
}
return radar_detected;
}
boolean phydm_radar_detect(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
boolean enable_DFS = false;
boolean radar_detected = false;
dfs->igi_cur = (u8)odm_get_bb_reg(dm, 0xc50, 0x0000007f);
dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, 0x91c, 0x000000ff);
/* dynamic pwdb calibration */
if (dfs->igi_pre != dfs->igi_cur) {
dfs->pwdb_th = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)/2 + dfs->pwdb_scalar_factor;
dfs->pwdb_th = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); /* limit the pwdb value to absoulte lower bound 0xa */
dfs->pwdb_th = MIN_2(dfs->pwdb_th_cur, 0x1f); /* limit the pwdb value to absoulte upper bound 0x1f */
odm_set_bb_reg(dm, 0x918, 0x00001f00, dfs->pwdb_th);
}
dfs->igi_pre = dfs->igi_cur;
phydm_dfs_dynamic_setting(dm);
radar_detected = phydm_radar_detect_dm_check(dm);
if (odm_get_bb_reg(dm, 0x924, BIT(15)))
enable_DFS = true;
if (enable_DFS && radar_detected) {
PHYDM_DBG(dm, DBG_DFS, "Radar detect: enable_DFS:%d, radar_detected:%d\n", enable_DFS, radar_detected);
phydm_radar_detect_reset(dm);
if (dfs->dbg_mode == 1){
PHYDM_DBG(dm, DBG_DFS, "Radar is detected in DFS dbg mode.\n");
radar_detected = 0;
}
}
return enable_DFS && radar_detected;
}
void
phydm_dfs_debug(
void *dm_void,
u32 *const argv,
u32 *_used,
char *output,
u32 *_out_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS);
u32 used = *_used;
u32 out_len = *_out_len;
dfs->dbg_mode = (boolean)argv[0];
dfs->force_TP_mode = (boolean)argv[1];
dfs->det_print = (boolean)argv[2];
dfs->det_print2 = (boolean)argv[3];
PDM_SNPF(out_len, used, output + used, out_len - used,
"dbg_mode: %d, force_TP_mode: %d, det_print: %d, det_print2: %d\n",
dfs->dbg_mode, dfs->force_TP_mode, dfs->det_print,
dfs->det_print2);
/*switch (argv[0]) {
case 1:
#if defined(CONFIG_PHYDM_DFS_MASTER)
set dbg parameters for radar detection instead of the default value
if (argv[1] == 1) {
dm->radar_detect_reg_918 = argv[2];
dm->radar_detect_reg_91c = argv[3];
dm->radar_detect_reg_920 = argv[4];
dm->radar_detect_reg_924 = argv[5];
dm->radar_detect_dbg_parm_en = 1;
PDM_SNPF((output + used, out_len - used, "Radar detection with dbg parameter\n"));
PDM_SNPF((output + used, out_len - used, "reg918:0x%08X\n", dm->radar_detect_reg_918));
PDM_SNPF((output + used, out_len - used, "reg91c:0x%08X\n", dm->radar_detect_reg_91c));
PDM_SNPF((output + used, out_len - used, "reg920:0x%08X\n", dm->radar_detect_reg_920));
PDM_SNPF((output + used, out_len - used, "reg924:0x%08X\n", dm->radar_detect_reg_924));
} else {
dm->radar_detect_dbg_parm_en = 0;
PDM_SNPF((output + used, out_len - used, "Radar detection with default parameter\n"));
}
phydm_radar_detect_enable(dm);
#endif defined(CONFIG_PHYDM_DFS_MASTER)
break;
default:
break;
}*/
}
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_is_dfs_band(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
((*dm->channel >= 100) && (*dm->channel <= 140)))
return true;
else
return false;
}
boolean
phydm_dfs_master_enabled(
void *dm_void
)
{
#ifdef CONFIG_PHYDM_DFS_MASTER
struct dm_struct *dm = (struct dm_struct *)dm_void;
return *dm->dfs_master_enabled ? true : false;
#else
return false;
#endif
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_DFS_H__
#define __PHYDM_DFS_H__
#define DFS_VERSION "1.1"
/* ============================================================
Definition
============================================================
*/
/*
============================================================
1 structure
============================================================
*/
struct _DFS_STATISTICS {
u8 mask_idx;
u8 igi_cur;
u8 igi_pre;
u8 st_l2h_cur;
u16 fa_count_pre;
u16 fa_inc_hist[5];
u16 vht_crc_ok_cnt_pre;
u16 ht_crc_ok_cnt_pre;
u16 leg_crc_ok_cnt_pre;
u16 short_pulse_cnt_pre;
u16 long_pulse_cnt_pre;
u8 pwdb_th;
u8 pwdb_th_cur;
u8 pwdb_scalar_factor;
u8 peak_th;
u8 short_pulse_cnt_th;
u8 long_pulse_cnt_th;
u8 peak_window;
u8 nb2wb_th;
u8 fa_mask_th;
u8 det_flag_offset;
u8 st_l2h_max;
u8 st_l2h_min;
u8 mask_hist_checked;
boolean pulse_flag_hist[5];
boolean radar_det_mask_hist[5];
boolean idle_mode;
boolean force_TP_mode;
boolean dbg_mode;
boolean det_print;
boolean det_print2;
};
/* ============================================================
enumeration
============================================================
*/
enum phydm_dfs_region_domain {
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
PHYDM_DFS_DOMAIN_FCC = 1,
PHYDM_DFS_DOMAIN_MKK = 2,
PHYDM_DFS_DOMAIN_ETSI = 3,
};
/*
============================================================
function prototype
============================================================
*/
#if defined(CONFIG_PHYDM_DFS_MASTER)
void phydm_radar_detect_reset(void *dm_void);
void phydm_radar_detect_disable(void *dm_void);
void phydm_radar_detect_enable(void *dm_void);
boolean phydm_radar_detect(void *dm_void);
void phydm_dfs_parameter_init(void *dm_void);
void phydm_dfs_debug(void *dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len);
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_dfs_is_meteorology_channel(
void *dm_void
);
boolean
phydm_is_dfs_band(
void *dm_void
);
boolean
phydm_dfs_master_enabled(
void *dm_void
);
#endif /*#ifndef __PHYDM_DFS_H__ */

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hal/phydm/phydm_dig.c Normal file
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363
hal/phydm/phydm_dig.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
/*#define DIG_VERSION "1.4"*/ /* 2017.04.18 YuChen. refine DIG code structure*/
/*#define DIG_VERSION "2.0"*/ /* 2017.05.09 Dino. Move CCKPD to new files*/
/*#define DIG_VERSION "2.1"*/ /* 2017.06.01 YuChen. Refine DFS condition*/
#define DIG_VERSION "2.2" /* 2017.06.13 YuChen. Remove MP dig*/
#define DIG_HW 0
/*--------------------Define ---------------------------------------*/
/*=== [DIG Boundary] ========================================*/
/*DIG coverage mode*/
#define DIG_MAX_COVERAGR 0x26
#define DIG_MIN_COVERAGE 0x1c
#define DIG_MAX_OF_MIN_COVERAGE 0x22
/*DIG performance mode*/
#if (DIG_HW == 1)
#define DIG_MAX_BALANCE_MODE 0x32
#else
#define DIG_MAX_BALANCE_MODE 0x3e
#endif
#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
#define DIG_MAX_PERFORMANCE_MODE 0x5a
#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*from 3E -> 2A, refine by YuChen 2017/04/18*/
#define DIG_MIN_PERFORMANCE 0x20
/*DIG DFS function*/
#define DIG_MAX_DFS 0x28
#define DIG_MIN_DFS 0x20
/*DIG LPS function*/
#define DIG_MAX_LPS 0x3e
#define DIG_MIN_LPS 0x20
/*=== [DIG FA Threshold] ======================================*/
/*Normal*/
#define DM_DIG_FA_TH0 500
#define DM_DIG_FA_TH1 750
/*LPS*/
#define DM_DIG_FA_TH0_LPS 4 /* -> 4 lps */
#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
#define RSSI_OFFSET_DIG_LPS 5
/*LNA saturation check*/
#define OFDM_AGC_TAB_0 0
#define OFDM_AGC_TAB_2 2
#define DIFF_RSSI_TO_IGI 10
#define ONE_SEC_MS 1000
/*--------------------Enum-----------------------------------*/
enum dig_goupcheck_level {
DIG_GOUPCHECK_LEVEL_0,
DIG_GOUPCHECK_LEVEL_1,
DIG_GOUPCHECK_LEVEL_2
};
enum phydm_dig_mode {
PHYDM_DIG_PERFORAMNCE_MODE = 0,
PHYDM_DIG_COVERAGE_MODE = 1,
};
enum lna_sat_timer_state {
INIT_LNA_SAT_CHK_TIMMER,
CANCEL_LNA_SAT_CHK_TIMMER,
RELEASE_LNA_SAT_CHK_TIMMER
};
/*--------------------Define Struct-----------------------------------*/
struct phydm_dig_struct {
boolean is_ignore_dig; /*for old pause function*/
boolean is_dbg_fa_th;
u8 dig_mode_decision;
u8 cur_ig_value;
u8 rvrt_val;
u8 igi_backup;
u8 rx_gain_range_max; /*dig_dynamic_max*/
u8 rx_gain_range_min; /*dig_dynamic_min*/
u8 dm_dig_max; /*Absolutly upper bound*/
u8 dm_dig_min; /*Absolutly lower bound*/
u8 dig_max_of_min; /*Absolutly max of min*/
boolean is_media_connect;
u32 ant_div_rssi_max;
u8 *is_p2p_in_process;
u8 pause_lv_bitmap; /*bit-map of pause level*/
u8 pause_dig_value[PHYDM_PAUSE_MAX_NUM];
enum dig_goupcheck_level dig_go_up_check_level;
u8 aaa_default;
u8 a0a_default;
u16 fa_th[3];
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
u8 rf_gain_idx;
u8 agc_table_idx;
u8 big_jump_lmt[16];
u8 enable_adjust_big_jump:1;
u8 big_jump_step1:3;
u8 big_jump_step2:2;
u8 big_jump_step3:2;
#endif
u8 dig_upcheck_initial_value;
u8 dig_level0_ratio_reciprocal;
u8 dig_level1_ratio_reciprocal;
#ifdef PHYDM_TDMA_DIG_SUPPORT
u8 cur_ig_value_tdma;
u8 low_ig_value;
u8 tdma_dig_state; /*To distinguish which state is now.(L-sate or H-state)*/
u8 tdma_dig_cnt; /*for phydm_tdma_dig_timer_check use*/
u8 pre_tdma_dig_cnt;
u8 sec_factor;
u32 cur_timestamp;
u32 pre_timestamp;
u32 fa_start_timestamp;
u32 fa_end_timestamp;
u32 fa_acc_1sec_timestamp;
#endif
};
struct phydm_fa_struct {
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_crc8_fail;
u32 cnt_crc8_fail_vht;
u32 cnt_mcs_fail;
u32 cnt_mcs_fail_vht;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /* For RTL8881A */
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_pre;
u32 cnt_fast_fsync;
u32 cnt_sb_search_fail;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_bw_usc;
u32 cnt_bw_lsc;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_ht_crc32_error_agg;
u32 cnt_ht_crc32_ok_agg;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 time_fa_all;
boolean cck_block_enable;
boolean ofdm_block_enable;
u32 dbg_port0;
boolean edcca_flag;
};
#ifdef PHYDM_TDMA_DIG_SUPPORT
struct phydm_fa_acc_struct {
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_crc8_fail;
u32 cnt_mcs_fail;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /*For RTL8881A*/
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_pre;
u32 cnt_fast_fsync;
u32 cnt_sb_search_fail;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 cnt_all_1sec;
u32 cnt_cca_all_1sec;
u32 cnt_cck_fail_1sec;
};
#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
struct phydm_lna_sat_info_struct {
u32 sat_cnt_acc_patha;
u32 sat_cnt_acc_pathb;
u32 check_time;
boolean pre_sat_status;
boolean cur_sat_status;
struct phydm_timer_list phydm_lna_sat_chk_timer;
u32 cur_timer_check_cnt;
u32 pre_timer_check_cnt;
};
/*--------------------Function declaration-----------------------------*/
void
odm_write_dig(
void *dm_void,
u8 current_igi
);
void
phydm_set_dig_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
void
odm_pause_dig(
void *dm_void,
enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level,
u8 igi_value
);
void
phydm_dig_init(
void *dm_void
);
void
phydm_dig(
void *dm_void
);
void
phydm_dig_lps_32k(
void *dm_void
);
void
phydm_dig_by_rssi_lps(
void *dm_void
);
void
odm_false_alarm_counter_statistics(
void *dm_void
);
#ifdef PHYDM_TDMA_DIG_SUPPORT
void
phydm_set_tdma_dig_timer(
void *dm_void
);
void
phydm_tdma_dig_timer_check(
void *dm_void
);
void
phydm_tdma_dig(
void *dm_void
);
void
phydm_tdma_false_alarm_counter_check(
void *dm_void
);
void
phydm_tdma_dig_add_interrupt_mask_handler(
void *dm_void
);
void
phydm_false_alarm_counter_reset(
void *dm_void
);
void
phydm_false_alarm_counter_acc(
void *dm_void,
boolean rssi_dump_en
);
void
phydm_false_alarm_counter_acc_reset(
void *dm_void
);
#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
void
phydm_set_ofdm_agc_tab(
void *dm_void,
u8 tab_sel
);
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
u8
phydm_get_ofdm_agc_tab(
void *dm_void
);
void
phydm_lna_sat_chk(
void *dm_void
);
void
phydm_lna_sat_chk_timers(
void *dm_void,
u8 state
);
void
phydm_lna_sat_chk_watchdog(
void *dm_void
);
#endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
void
phydm_dig_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_DYNAMIC_RX_PATH
void
phydm_process_phy_status_for_dynamic_rx_path(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
}
void
phydm_drp_get_statistic(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
odm_false_alarm_counter_statistics(dm);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all);
}
void
phydm_dynamic_rx_path(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
u8 training_set_timmer_en;
u8 curr_drp_state;
u32 rx_ok_cal;
u32 RSSI = 0;
struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return Init] Not Support Dynamic RX PAth\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state);
curr_drp_state = p_dm_drp_table->drp_state;
if (p_dm_drp_table->drp_state == DRP_INIT_STATE) {
phydm_drp_get_statistic(dm);
if (false_alm_cnt->cnt_crc32_ok_all > 20) { /*Signal + Interference*/
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all);
p_dm_drp_table->drp_state = DRP_INIT_STATE;
training_set_timmer_en = false;
} else {/*Interference only*/
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all);
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0;
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
training_set_timmer_en = true;
}
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all;
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1;
p_dm_drp_table->curr_rx_path = BB_PATH_B;
training_set_timmer_en = true;
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all;
#if 1
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
#else
if (*(dm->mp_mode)) {
rx_ok_cal = dm->phy_dbg_info.num_qry_phy_status_cck + dm->phy_dbg_info.num_qry_phy_status_ofdm;
RSSI = (rx_ok_cal != 0) ? dm->rx_pwdb_ave / rx_ok_cal : 0;
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "MP RSSI = ((%d))\n", RSSI);
}
if (RSSI > p_dm_drp_table->rssi_threshold)
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
else {
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2;
p_dm_drp_table->curr_rx_path = BB_PATH_A;
training_set_timmer_en = true;
}
#endif
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all;
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
}
if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2);
if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) {
if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold)
p_dm_drp_table->curr_rx_path = BB_PATH_B;
else
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
} else
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training Result] curr_rx_path = ((%s%s)),\n",
((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " "));
p_dm_drp_table->drp_state = DRP_INIT_STATE;
training_set_timmer_en = false;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state);
if (training_set_timmer_en) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n",
((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " "), p_dm_drp_table->training_time);
phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path);
odm_set_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/
} else
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state);
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
phydm_dynamic_rx_path_callback(
struct phydm_timer_list *timer
)
{
void *adapter = (void *)timer->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(hal_data->DM_OutSrc);
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
#if USE_WORKITEM
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
#else
{
/* dbg_print("phydm_dynamic_rx_path\n"); */
phydm_dynamic_rx_path(dm);
}
#endif
#else
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
#endif
}
void
phydm_dynamic_rx_path_workitem_callback(
void *context
)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(hal_data->DM_OutSrc);
/* dbg_print("phydm_dynamic_rx_path\n"); */
phydm_dynamic_rx_path(dm);
}
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
phydm_dynamic_rx_path_callback(
void *function_context
)
{
struct dm_struct *dm = (struct dm_struct *)function_context;
void *padapter = dm->adapter;
if (*(dm->is_net_closed) == true)
return;
#if 0 /* Can't do I/O in timer callback*/
odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
#else
/*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/
#endif
}
#endif
void
phydm_dynamic_rx_path_timers(
void *dm_void,
u8 state
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
if (state == INIT_DRP_TIMMER) {
odm_initialize_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer),
(void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer");
} else if (state == CANCEL_DRP_TIMMER)
odm_cancel_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
else if (state == RELEASE_DRP_TIMMER)
odm_release_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
}
void
phydm_dynamic_rx_path_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
boolean ret_value;
if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return] Not Support Dynamic RX PAth\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "phydm_dynamic_rx_path_init\n");
p_dm_drp_table->drp_state = DRP_INIT_STATE;
p_dm_drp_table->rssi_threshold = DRP_RSSI_TH;
p_dm_drp_table->fa_count_thresold = 50;
p_dm_drp_table->fa_diff_threshold = 50;
p_dm_drp_table->training_time = 100; /*ms*/
p_dm_drp_table->drp_skip_counter = 0;
p_dm_drp_table->drp_period = 0;
p_dm_drp_table->drp_init_finished = true;
ret_value = phydm_api_trx_mode(dm, (enum bb_path)BB_PATH_AB, (enum bb_path)BB_PATH_AB, true);
}
void
phydm_drp_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
switch (dm_value[0]) {
case DRP_TRAINING_TIME:
p_dm_drp_table->training_time = (u16)dm_value[1];
break;
case DRP_TRAINING_PERIOD:
p_dm_drp_table->drp_period = (u8)dm_value[1];
break;
case DRP_RSSI_THRESHOLD:
p_dm_drp_table->rssi_threshold = (u8)dm_value[1];
break;
case DRP_FA_THRESHOLD:
p_dm_drp_table->fa_count_thresold = dm_value[1];
break;
case DRP_FA_DIFF_THRESHOLD:
p_dm_drp_table->fa_diff_threshold = dm_value[1];
break;
default:
PDM_SNPF(out_len, used, output + used, out_len - used,
"[DRP] unknown command\n");
break;
}
*_used = used;
*_out_len = out_len;
}
void
phydm_dynamic_rx_path_caller(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period)
p_dm_drp_table->drp_skip_counter++;
else
p_dm_drp_table->drp_skip_counter = 0;
if (p_dm_drp_table->drp_skip_counter != 0)
return;
if (p_dm_drp_table->drp_init_finished != true)
return;
phydm_dynamic_rx_path(dm);
}
#endif

151
hal/phydm/phydm_dynamic_rx_path.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDYMICRXPATH_H__
#define __PHYDMDYMICRXPATH_H__
#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */
#define DRP_RSSI_TH 35
#define INIT_DRP_TIMMER 0
#define CANCEL_DRP_TIMMER 1
#define RELEASE_DRP_TIMMER 2
#if (RTL8822B_SUPPORT == 1)
struct drp_rtl8822b_struct {
enum bb_path path_judge;
u16 path_a_cck_fa;
u16 path_b_cck_fa;
};
#endif
#ifdef CONFIG_DYNAMIC_RX_PATH
enum drp_state {
DRP_INIT_STATE = 0,
DRP_TRAINING_STATE_0 = 1,
DRP_TRAINING_STATE_1 = 2,
DRP_TRAINING_STATE_2 = 3,
DRP_DECISION_STATE = 4
};
enum adjustable_value {
DRP_TRAINING_TIME = 0,
DRP_TRAINING_PERIOD = 1,
DRP_RSSI_THRESHOLD = 2,
DRP_FA_THRESHOLD = 3,
DRP_FA_DIFF_THRESHOLD = 4
};
struct _DYNAMIC_RX_PATH_ {
u8 curr_rx_path;
u8 drp_state;
u16 training_time;
u8 rssi_threshold;
u32 fa_count_thresold;
u32 fa_diff_threshold;
u32 curr_cca_all_cnt_0;
u32 curr_fa_all_cnt_0;
u32 curr_cca_all_cnt_1;
u32 curr_fa_all_cnt_1;
u32 curr_cca_all_cnt_2;
u32 curr_fa_all_cnt_2;
u8 drp_skip_counter;
u8 drp_period;
u8 drp_init_finished;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM phydm_dynamic_rx_path_workitem;
#endif
#endif
struct phydm_timer_list phydm_dynamic_rx_path_timer;
};
void
phydm_process_phy_status_for_dynamic_rx_path(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
void
phydm_dynamic_rx_path(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
phydm_dynamic_rx_path_callback(
struct phydm_timer_list *timer
);
void
phydm_dynamic_rx_path_workitem_callback(
void *context
);
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
phydm_dynamic_rx_path_callback(
void *function_context
);
#endif
void
phydm_dynamic_rx_path_timers(
void *dm_void,
u8 state
);
void
phydm_dynamic_rx_path_init(
void *dm_void
);
void
phydm_drp_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_dynamic_rx_path_caller(
void *dm_void
);
#endif
#endif

712
hal/phydm/phydm_dynamictxpower.c Normal file
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@@ -0,0 +1,712 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* *********************Power training init************************ */
void phydm_pow_train_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
/* This is for power training init @ 11N serious */
#if DEV_BUS_TYPE == RT_USB_INTERFACE
if (RT_GetInterfaceSelection((PADAPTER)adapter) == INTF_SEL1_USB_High_Power) {
odm_dynamic_tx_power_save_power_index(dm);
}
#else
/* so 92c pci do not need dynamic tx power? vivi check it later */
#endif
#endif
}
void
odm_dynamic_tx_power_save_power_index(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 index;
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/* Save PT index, but nothing used?? */
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
for (index = 0; index < 6; index++)
hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte((PADAPTER)adapter, power_index_reg[index]);
#endif
#endif
}
void
odm_dynamic_tx_power_restore_power_index(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 index;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for (index = 0; index < 6; index++)
PlatformEFIOWrite1Byte(adapter, power_index_reg[index], hal_data->PowerIndex_backup[index]);
#endif
}
void
odm_dynamic_tx_power_write_power_index(
void *dm_void,
u8 value)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 index;
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for (index = 0; index < 6; index++)
/* platform_efio_write_1byte(adapter, power_index_reg[index], value); */
odm_write_1byte(dm, power_index_reg[index], value);
}
/* ************************************************************ */
#ifdef CONFIG_DYNAMIC_TX_TWR
boolean
phydm_check_rates(
void *dm_void,
u8 rate_idx
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 check_rate_bitmap0 = 0x08080808; /* check CCK11M, OFDM54M, MCS7, MCS15*/
u32 check_rate_bitmap1 = 0x80200808; /* check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
u32 check_rate_bitmap2 = 0x00080200; /* check VHT3SS M9, VHT4SS M9*/
u32 bitmap_result;
#if (RTL8822B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8822B) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0xfffff000;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8197F_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8197F) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8821C) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0x003ff000;
check_rate_bitmap0 &= 0x000fffff;
}
#endif
if (rate_idx >= 64)
bitmap_result = BIT(rate_idx-64) & check_rate_bitmap2;
else if (rate_idx >= 32)
bitmap_result = BIT(rate_idx-32) & check_rate_bitmap1;
else if (rate_idx <= 31)
bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
if (bitmap_result!=0)
return true;
else
return false;
}
enum rf_path
phydm_check_paths(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path max_path;
#if (RTL8822B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8822B)
max_path = RF_PATH_B;
#endif
#if (RTL8197F_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8197F)
max_path = RF_PATH_B;
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8821C)
max_path = RF_PATH_A;
#endif
return max_path;
}
u8
phydm_search_min_power_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path path;
enum rf_path max_path;
u8 min_gain_index = 0x3f;
u8 gain_index;
u8 rate_idx;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "phydm_search_min_power_index\n");
max_path = phydm_check_paths(dm);
for (path = 0; path <= max_path; path++)
for (rate_idx = 0; rate_idx < 84; rate_idx++)
if (phydm_check_rates(dm, rate_idx)) {
gain_index = phydm_api_get_txagc(dm, path, rate_idx);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Support Rate: ((%d)) -> Gain index: ((%d))\n", rate_idx, gain_index);
if (gain_index < min_gain_index)
min_gain_index = gain_index;
}
return min_gain_index;
}
void
phydm_dynamic_tx_power_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
dm->last_dtp_lvl = tx_high_pwr_level_normal;
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
dm->min_power_index = phydm_search_min_power_index(dm);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain index: ((%d))\n", dm->min_power_index);
}
u8
phydm_pwr_lvl_check(
void *dm_void,
u8 input_rssi
)
{
if (input_rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
return tx_high_pwr_level_level2;
/**/
} else if (input_rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
return tx_high_pwr_level_level1;
/**/
} else if (input_rssi < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
return tx_high_pwr_level_normal;
/**/
}
else {
return tx_high_pwr_level_normal;
}
}
void
phydm_dynamic_response_power(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 now_pwr_lvl;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dm->last_dtp_lvl != dm->dynamic_tx_high_power_lvl) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl);
dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
now_pwr_lvl = dm->dynamic_tx_high_power_lvl;
if (now_pwr_lvl == tx_high_pwr_level_level2 || now_pwr_lvl == tx_high_pwr_level_level1) {
odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT(19) | BIT(18), 1); /* Resp TXAGC offset = -3dB*/
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power Set TX power: level 1\n");
} else if (now_pwr_lvl == tx_high_pwr_level_normal) {
odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT(19) | BIT(18), 0); /* Resp TXAGC offset = 0dB*/
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power Set TX power: normal\n");
}
}
}
void
phydm_dtp_fill_cmninfo(
void *dm_void,
u8 macid,
u8 dtp_lvl
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dtp_info *dtp= NULL;
dtp = &dm->phydm_sta_info[macid]->dtp_stat;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dtp_lvl == tx_high_pwr_level_level2)
dtp->dyn_tx_power = PHYDM_OFFSET_MINUS_7DB;
else if (dtp_lvl == tx_high_pwr_level_level1)
dtp->dyn_tx_power = PHYDM_OFFSET_MINUS_3DB;
else
dtp->dyn_tx_power = PHYDM_OFFSET_ZERO;
}
void
phydm_dtp_per_sta(
void *dm_void,
u8 macid
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct dtp_info *dtp = NULL;
struct rssi_info *rssi = NULL;
if (is_sta_active(sta)) {
dtp = &sta->dtp_stat;
rssi = &sta->rssi_stat;
dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm,rssi->rssi);
if (dtp->sta_tx_high_power_lvl != dtp->sta_last_dtp_lvl) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "STA=%d : update_DTP_lv: ((%d)) -> ((%d))\n", macid, dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl);
dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
phydm_dtp_fill_cmninfo(dm, macid, dm->dynamic_tx_high_power_lvl);
}
}
}
#else
void
phydm_dynamic_tx_power_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
/*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/
/* PHYDM_DBG(dm,DBG_DYN_TXPWR, */
/* ("DynamicTxPowerEnable=%d\n", mgnt_info->is_dynamic_tx_power_enable));*/
/* return;*/
/*} else*/
{
mgnt_info->bDynamicTxPowerEnable = true;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DynamicTxPowerEnable=%d\n", mgnt_info->bDynamicTxPowerEnable);
}
#if DEV_BUS_TYPE == RT_USB_INTERFACE
if (RT_GetInterfaceSelection((PADAPTER)adapter) == INTF_SEL1_USB_High_Power) {
mgnt_info->bDynamicTxPowerEnable = true;
} else
#else
/* so 92c pci do not need dynamic tx power? vivi check it later */
mgnt_info->bDynamicTxPowerEnable = false;
#endif
hal_data->LastDTPLvl = tx_high_pwr_level_normal;
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
dm->last_dtp_lvl = tx_high_pwr_level_normal;
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
dm->tx_agc_ofdm_18_6 = odm_get_bb_reg(dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
#endif
}
void
odm_dynamic_tx_power_nic_ce(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
#if (RTL8821A_SUPPORT == 1)
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 val;
u8 rssi_tmp = dm->rssi_min;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2;
/**/
} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1;
/**/
} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
/**/
}
if (dm->last_dtp_lvl == dm->dynamic_tx_high_power_lvl)
return;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl);
dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
if (dm->support_ic_type & (ODM_RTL8821)) {
if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) {
odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
val = dm->tx_agc_ofdm_18_6 & 0xff;
if (val >= 0x20)
val -= 0x16;
odm_set_bb_reg(dm, 0xC24, 0xff, val);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: level 2\n");
} else if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) {
odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
val = dm->tx_agc_ofdm_18_6 & 0xff;
if (val >= 0x20)
val -= 0x10;
odm_set_bb_reg(dm, 0xC24, 0xff, val);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: level 1\n");
} else if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) {
odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/
odm_set_bb_reg(dm, 0xC24, MASKDWORD, dm->tx_agc_ofdm_18_6);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: normal\n");
}
}
#endif
#endif
}
void
odm_dynamic_tx_power(
void *dm_void
)
{
/* */
/* For AP/ADSL use struct rtl8192cd_priv* */
/* For CE/NIC use struct void* */
/* */
/* struct void* adapter = dm->adapter;
* struct rtl8192cd_priv* priv = dm->priv; */
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
/* */
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
/* HW dynamic mechanism. */
/* */
switch (dm->support_platform) {
case ODM_WIN:
odm_dynamic_tx_power_nic(dm);
break;
case ODM_CE:
odm_dynamic_tx_power_nic_ce(dm);
break;
default:
break;
}
}
void
odm_dynamic_tx_power_nic(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
if (dm->support_ic_type == ODM_RTL8814A)
odm_dynamic_tx_power_8814a(dm);
else if (dm->support_ic_type & ODM_RTL8821) {
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
if (mgnt_info->RegRspPwr == 1) {
if (dm->rssi_min > 60)
odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/
else if (dm->rssi_min < 55)
odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/
}
}
#endif
}
void
odm_dynamic_tx_power_8821(
void *dm_void,
u8 *desc,
u8 mac_id
)
{
#if (RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *entry;
u8 reg0xc56_byte;
u8 txpwr_offset = 0;
entry = dm->phydm_sta_info[mac_id];
reg0xc56_byte = odm_read_1byte(dm, 0xc56);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "reg0xc56_byte=%d\n", reg0xc56_byte);
if (entry[mac_id].rssi_stat.rssi > 85) {
/* Avoid TXAGC error after TX power offset is applied.
For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
Total power = 6-11= -5( overflow!! ), PA may be burned !
so txpwr_offset should be adjusted by Reg0xc56*/
if (reg0xc56_byte < 7)
txpwr_offset = 1;
else if (reg0xc56_byte < 11)
txpwr_offset = 2;
else
txpwr_offset = 3;
SET_TX_DESC_TX_POWER_OFFSET_8812(desc, txpwr_offset);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", entry[mac_id].rssi_stat.rssi, txpwr_offset);
} else {
SET_TX_DESC_TX_POWER_OFFSET_8812(desc, txpwr_offset);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", entry[mac_id].rssi_stat.rssi, txpwr_offset);
}
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
#endif /*#if (RTL8821A_SUPPORT==1)*/
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_dynamic_tx_power_8814a(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
s32 undecorated_smoothed_pwdb = dm->rssi_min;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"TxLevel=%d mgnt_info->iot_action=%x mgnt_info->is_dynamic_tx_power_enable=%d\n",
hal_data->DynamicTxHighPowerLvl, mgnt_info->IOTAction, mgnt_info->bDynamicTxPowerEnable);
/*STA not connected and AP not connected*/
if ((!mgnt_info->bMediaConnect) && (hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "Not connected to any reset power lvl\n");
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
return;
}
if (!mgnt_info->bDynamicTxPowerEnable || mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
else {
/*Should we separate as 2.4G/5G band?*/
PHYDM_DBG(dm, DBG_DYN_TXPWR, "rssi_tmp = %d\n", undecorated_smoothed_pwdb);
if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_level1 (TxPwr=0x0)\n");
} else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
(undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_level1 (TxPwr=0x10)\n");
} else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_normal\n");
}
}
if (hal_data->DynamicTxHighPowerLvl != hal_data->LastDTPLvl) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8814a() channel = %d\n", hal_data->CurrentChannel);
odm_set_tx_power_level8814(adapter, hal_data->CurrentChannel, hal_data->DynamicTxHighPowerLvl);
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n",
hal_data->CurrentChannel, hal_data->LastDTPLvl, hal_data->DynamicTxHighPowerLvl);
hal_data->LastDTPLvl = hal_data->DynamicTxHighPowerLvl;
}
/**/
/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
/**/
/**/
void
odm_set_tx_power_level8814(
void *adapter,
u8 channel,
u8 pwr_lvl
)
{
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
u32 i, j, k = 0;
u32 value[264] = {0};
u32 path = 0, power_index, txagc_table_wd = 0x00801000;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}
};
for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
u8 usb_host = UsbModeQueryHubUsbType((PADAPTER)adapter);
u8 usb_rfset = UsbModeQueryRfSet((PADAPTER)adapter);
u8 usb_rf_type = RT_GetRFType((PADAPTER)adapter);
for (i = 0; i <= 16; i++) {
for (j = 0; j <= 3; j++) {
if (jaguar2_rates[i][j] == 0)
continue;
txagc_table_wd = 0x00801000;
power_index = (u32) PHY_GetTxPowerIndex((PADAPTER)adapter, (u8)path, jaguar2_rates[i][j], hal_data->CurrentChannelBW, channel);
/*for Query bus type to recude tx power.*/
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
if (channel <= 14) {
if (power_index >= 16)
power_index -= 16;
else
power_index = 0;
} else
power_index = 0;
}
if (pwr_lvl == tx_high_pwr_level_level1) {
if (power_index >= 0x10)
power_index -= 0x10;
else
power_index = 0;
} else if (pwr_lvl == tx_high_pwr_level_level2)
power_index = 0;
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
PHY_SetTxPowerIndexShadow((PADAPTER)adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
value[k++] = txagc_table_wd;
}
}
}
if (((PADAPTER)adapter)->MgntInfo.bScanInProgress == false && ((PADAPTER)adapter)->MgntInfo.RegFWOffload == 2)
HalDownloadTxPowerLevel8814((PADAPTER)adapter, value);
#endif
}
#endif
#endif /* #ifdef CONFIG_DYNAMIC_TX_TWR */
void
phydm_dynamic_tx_power(
void *dm_void
)
{
#ifdef CONFIG_DYNAMIC_TX_TWR
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = NULL;
u8 i;
u8 cnt = 0;
u8 rssi_min = dm->rssi_min;
u8 rssi_tmp;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
/* Response Power */
dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min);
phydm_dynamic_response_power(dm);
/* Per STA Tx power */
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
phydm_dtp_per_sta(dm, i);
cnt++;
if (cnt >= dm->number_linked_client)
break;
}
#endif
}

134
hal/phydm/phydm_dynamictxpower.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/
#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#endif
#define tx_high_pwr_level_normal 0
#define tx_high_pwr_level_level1 1
#define tx_high_pwr_level_level2 2
#define tx_high_pwr_level_bt1 3
#define tx_high_pwr_level_bt2 4
#define tx_high_pwr_level_15 5
#define tx_high_pwr_level_35 6
#define tx_high_pwr_level_50 7
#define tx_high_pwr_level_70 8
#define tx_high_pwr_level_100 9
enum phydm_dtp_power_offset {
PHYDM_OFFSET_ZERO = 0,
PHYDM_OFFSET_MINUS_3DB = 1,
PHYDM_OFFSET_MINUS_7DB = 2,
PHYDM_OFFSET_MINUS_11DB = 3,
PHYDM_OFFSET_ADD_3DB = 4,
PHYDM_OFFSET_ADD_6DB = 5
};
void
phydm_pow_train_init(
void *dm_void
);
void
phydm_dynamic_tx_power(
void *dm_void
);
void
odm_dynamic_tx_power_restore_power_index(
void *dm_void
);
void
odm_dynamic_tx_power_nic(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
odm_dynamic_tx_power_save_power_index(
void *dm_void
);
void
odm_dynamic_tx_power_write_power_index(
void *dm_void,
u8 value);
void
odm_dynamic_tx_power_8821(
void *dm_void,
u8 *desc,
u8 mac_id
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_dynamic_tx_power_8814a(
void *dm_void
);
void
odm_set_tx_power_level8814(
void *adapter,
u8 channel,
u8 pwr_lvl
);
#endif
#endif
void
odm_dynamic_tx_power(
void *dm_void
);
void
phydm_dynamic_tx_power(
void *dm_void
);
void
phydm_dynamic_tx_power_init(
void *dm_void
);
#endif

52
hal/phydm/phydm_features.h Normal file
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@@ -0,0 +1,52 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_H__
#define __PHYDM_FEATURES_H__
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B)
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
/*20170103 YuChen add for FW API*/
#define PHYDM_FW_API_ENABLE_8822B 1
#define PHYDM_FW_API_FUNC_ENABLE_8822B 1
#define PHYDM_FW_API_ENABLE_8821C 1
#define PHYDM_FW_API_FUNC_ENABLE_8821C 1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "phydm_features_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "phydm_features_ce.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "phydm_features_ap.h"
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_AP_H__
#define __PHYDM_FEATURES_AP_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
#if (RTL8197F_SUPPORT == 1)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#endif
#if (RTL8197F_SUPPORT == 1)
#define PHYDM_LNA_SAT_CHK_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define PHYDM_POWER_TRAINING_SUPPORT*/
#endif
#if (RTL8822B_SUPPORT == 1)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*#define CONFIG_ADAPTIVE_SOML*/
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
#define PHYDM_DIG_MODE_DECISION_SUPPORT
/*#define CONFIG_PSD_TOOL*/
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_AP
/* #define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_RA_DYNAMIC_RATE_ID
#define CONFIG_BB_TXBF_API
/*#define ODM_CONFIG_BT_COEXIST*/
/*#define PHYDM_3RD_REFORM_RA_MASK*/
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define PHYDM_SUPPORT_RSSI_MONITOR
#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
#define CONFIG_PHYDM_DEBUG_FUNCTION
#endif
/* [ Configure Antenna Diversity ] */
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
#define SKIP_EVM_ANTDIV_TRAINING_PATCH
/*----------*/
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_2G_DIVERSITY
#endif
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
#define CONFIG_NO_5G_DIVERSITY
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
#define CONFIG_5G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_5G_CG_TRX_DIVERSITY
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_2G5G_CG_TRX_DIVERSITY
#endif
#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_5G_DIVERSITY
#endif
/*----------*/
#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_2G_SUPPORT_ANTDIV
#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_5G_SUPPORT_ANTDIV
#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
/*----------*/
#endif /*Antenna Diveristy*/
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_CE_H__
#define __PHYDM_FEATURES_CE_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#if (RTL8822B_SUPPORT == 1)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#define CONFIG_RECEIVER_BLOCKING
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_CE
/*Antenna Diversity*/
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8821A_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#endif
#endif
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
/*#define PHYDM_DIG_MODE_DECISION_SUPPORT*/
#define CONFIG_PSD_TOOL
/*#define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_3RD_REFORM_RA_MASK
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define PHYDM_SUPPORT_RSSI_MONITOR
/*#define PHYDM_AUTO_DEGBUG*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_WIN_H__
#define __PHYDM_FEATURES_WIN_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#if (RTL8822B_SUPPORT == 1)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*#define CONFIG_ADAPTIVE_SOML*/
#endif
/*Antenna Diversity*/
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
/* --[SmtAnt]-----------------------------------------*/
#if (RTL8821A_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#define CONFIG_FAT_PATCH
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
#define CONFIG_HL_SMART_ANTENNA
#endif
/* --------------------------------------------------*/
#endif
/*[SmartAntenna]*/
#define CONFIG_SMART_ANTENNA
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#define CONFIG_RECEIVER_BLOCKING
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
#define CONFIG_RA_FW_DBG_CODE
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
/*#define PHYDM_DIG_MODE_DECISION_SUPPORT */
#define CONFIG_PSD_TOOL
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_WIN
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_ANT_DETECTION
/*#define CONFIG_RA_DBG_CMD*/
#define CONFIG_BB_TXBF_API
#define ODM_CONFIG_BT_COEXIST
#define PHYDM_3RD_REFORM_RA_MASK
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define CONFIG_PHYDM_DFS_MASTER
#define PHYDM_SUPPORT_RSSI_MONITOR
#define PHYDM_AUTO_DEGBUG
#define CONFIG_PHYDM_DEBUG_FUNCTION
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(dm, array_mp_##ic##_agc_tab_diff_##band, \
sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32)))
#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(dm, array_tc_##ic##_agc_tab_diff_##band, \
sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (dm->is_mp_chip)\
AGC_DIFF_CONFIG_MP(ic, band);\
else\
AGC_DIFF_CONFIG_TC(ic, band);\
} while (0)
/* ************************************************************
* structure and define
* ************************************************************ */
enum hal_status
odm_config_rf_with_tx_pwr_track_header_file(
struct dm_struct *dm
);
enum hal_status
odm_config_rf_with_header_file(
struct dm_struct *dm,
enum odm_rf_config_type config_type,
u8 e_rf_path
);
enum hal_status
odm_config_bb_with_header_file(
struct dm_struct *dm,
enum odm_bb_config_type config_type
);
enum hal_status
odm_config_mac_with_header_file(
struct dm_struct *dm
);
u32
odm_get_hw_img_version(
struct dm_struct *dm
);
u32
query_phydm_trx_capability(
struct dm_struct *dm
);
u32
query_phydm_stbc_capability(
struct dm_struct *dm
);
u32
query_phydm_ldpc_capability(
struct dm_struct *dm
);
u32
query_phydm_txbf_parameters(
struct dm_struct *dm
);
u32
query_phydm_txbf_capability(
struct dm_struct *dm
);
#endif /*#ifndef __HALHWOUTSRC_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
#define INTERFACE_VERSION "1.2" /*2017.05.03 YuChen add phy param offload HAL MAC API*/
#define pdm_set_reg odm_set_bb_reg
/*=========== Constant/Structure/Enum/... Define*/
enum phydm_h2c_cmd {
PHYDM_H2C_RA_MASK = 0x40,
PHYDM_H2C_TXBF = 0x41,
ODM_H2C_RSSI_REPORT = 0x42,
ODM_H2C_IQ_CALIBRATION = 0x45,
PHYDM_RA_MASK_ABOVE_3SS = 0x46,
ODM_H2C_RA_PARA_ADJUST = 0x47,
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
PHYDM_H2C_FW_TRACE_EN = 0x49,
ODM_H2C_WIFI_CALIBRATION = 0x6d,
PHYDM_H2C_MU = 0x4a,
PHYDM_H2C_FW_GENERAL_INIT = 0x4c,
PHYDM_H2C_FW_CLM_MNTR = 0x4d,
ODM_MAX_H2CCMD
};
enum phydm_c2h_evt {
PHYDM_C2H_DBG = 0,
PHYDM_C2H_LB = 1,
PHYDM_C2H_XBF = 2,
PHYDM_C2H_TX_REPORT = 3,
PHYDM_C2H_INFO = 9,
PHYDM_C2H_BT_MP = 11,
PHYDM_C2H_RA_RPT = 12,
PHYDM_C2H_RA_PARA_RPT = 14,
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
PHYDM_C2H_CLM_MONITOR = 0x2a,
PHYDM_C2H_DBG_CODE = 0xFE,
PHYDM_C2H_EXTEND = 0xFF,
};
enum phydm_extend_c2h_evt {
PHYDM_EXTEND_C2H_DBG_PRINT = 0
};
enum phydm_halmac_param {
PHYDM_HALMAC_CMD_MAC_W8 = 0,
PHYDM_HALMAC_CMD_MAC_W16 = 1,
PHYDM_HALMAC_CMD_MAC_W32 = 2,
PHYDM_HALMAC_CMD_BB_W8,
PHYDM_HALMAC_CMD_BB_W16,
PHYDM_HALMAC_CMD_BB_W32,
PHYDM_HALMAC_CMD_RF_W,
PHYDM_HALMAC_CMD_DELAY_US,
PHYDM_HALMAC_CMD_DELAY_MS,
PHYDM_HALMAC_CMD_END = 0XFF,
};
/*=========== Macro Define*/
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
/* _cat: implemented by Token-Pasting Operator. */
#if 0
#define _cat(_name, _ic_type, _func) \
(\
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pdm_odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#ifdef __ECOS
#define _rtk_cat(_name, _ic_type, _func) \
(\
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name) \
)
#else
#define _cat(_name, _ic_type, _func) \
(\
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name) \
)
#endif
/*
* only sample code
*#define _cat(_name, _ic_type, _func) \
* ( \
* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \
* _func##_ic(_name, _8195) \
* )
*/
/* _name: name of register or bit.
* Example: "ODM_REG(R_A_AGC_CORE1, dm)"
* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */
#ifdef __ECOS
#define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
#else
#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
#endif
/*
* =========== Extern Variable ??? It should be forbidden.
* */
/*
* =========== EXtern Function Prototype
* */
u8
odm_read_1byte(
struct dm_struct *dm,
u32 reg_addr
);
u16
odm_read_2byte(
struct dm_struct *dm,
u32 reg_addr
);
u32
odm_read_4byte(
struct dm_struct *dm,
u32 reg_addr
);
void
odm_write_1byte(
struct dm_struct *dm,
u32 reg_addr,
u8 data
);
void
odm_write_2byte(
struct dm_struct *dm,
u32 reg_addr,
u16 data
);
void
odm_write_4byte(
struct dm_struct *dm,
u32 reg_addr,
u32 data
);
void
odm_set_mac_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32
odm_get_mac_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask
);
void
odm_set_bb_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32
odm_get_bb_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask
);
void
odm_set_rf_reg(
struct dm_struct *dm,
u8 e_rf_path,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32
odm_get_rf_reg(
struct dm_struct *dm,
u8 e_rf_path,
u32 reg_addr,
u32 bit_mask
);
/*
* Memory Relative Function.
* */
void
odm_allocate_memory(
struct dm_struct *dm,
void **ptr,
u32 length
);
void
odm_free_memory(
struct dm_struct *dm,
void *ptr,
u32 length
);
void
odm_move_memory(
struct dm_struct *dm,
void *dest,
void *src,
u32 length
);
s32 odm_compare_memory(
struct dm_struct *dm,
void *buf1,
void *buf2,
u32 length
);
void odm_memory_set(
struct dm_struct *dm,
void *pbuf,
s8 value,
u32 length
);
/*
* ODM MISC-spin lock relative API.
* */
void
odm_acquire_spin_lock(
struct dm_struct *dm,
enum rt_spinlock_type type
);
void
odm_release_spin_lock(
struct dm_struct *dm,
enum rt_spinlock_type type
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/*
* ODM MISC-workitem relative API.
* */
void
odm_initialize_work_item(
struct dm_struct *dm,
PRT_WORK_ITEM p_rt_work_item,
RT_WORKITEM_CALL_BACK rt_work_item_callback,
void *context,
const char *sz_id
);
void
odm_start_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void
odm_stop_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void
odm_free_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void
odm_schedule_work_item(
PRT_WORK_ITEM p_rt_work_item
);
boolean
odm_is_work_item_scheduled(
PRT_WORK_ITEM p_rt_work_item
);
#endif
/*
* ODM Timer relative API.
* */
void
ODM_delay_ms(u32 ms);
void
ODM_delay_us(u32 us);
void
ODM_sleep_ms(u32 ms);
void
ODM_sleep_us(u32 us);
void
odm_set_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer,
u32 ms_delay
);
void
odm_initialize_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer,
void *call_back_func,
void *context,
const char *sz_id
);
void
odm_cancel_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer
);
void
odm_release_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer
);
/*ODM FW relative API.*/
enum hal_status
phydm_set_reg_by_fw(
struct dm_struct *dm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum rf_path e_rf_path,
u32 delay_time
);
void
odm_fill_h2c_cmd(
struct dm_struct *dm,
u8 element_id,
u32 cmd_len,
u8 *cmd_buffer
);
u8
phydm_c2H_content_parsing(
void *dm_void,
u8 c2h_cmd_id,
u8 c2h_cmd_len,
u8 *tmp_buf
);
u64
odm_get_current_time(
struct dm_struct *dm
);
u64
odm_get_progressing_time(
struct dm_struct *dm,
u64 start_time
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) && !defined(DM_ODM_CE_MAC80211)
void
phydm_set_hw_reg_handler_interface (
struct dm_struct *dm,
u8 reg_Name,
u8 *val
);
void
phydm_get_hal_def_var_handler_interface (
struct dm_struct *dm,
enum _HAL_DEF_VARIABLE e_variable,
void *value
);
#endif
void
odm_set_tx_power_index_by_rate_section (
struct dm_struct *dm,
enum rf_path path,
u8 channel,
u8 rate_section
);
u8
odm_get_tx_power_index (
struct dm_struct *dm,
enum rf_path path,
u8 tx_rate,
u8 band_width,
u8 channel
);
u8
odm_efuse_one_byte_read(
struct dm_struct *dm,
u16 addr,
u8 *data,
boolean b_pseu_do_test
);
void
odm_efuse_logical_map_read(
struct dm_struct *dm,
u8 type,
u16 offset,
u32 *data
);
enum hal_status
odm_iq_calibrate_by_fw(
struct dm_struct *dm,
u8 clear,
u8 segment
);
void
odm_cmn_info_ptr_array_hook(
struct dm_struct *dm,
enum odm_cmninfo cmn_info,
u16 index,
void *value
);
void
phydm_cmn_sta_info_hook(
struct dm_struct *dm,
u8 index,
struct cmn_sta_info *pcmn_sta_info
);
void
phydm_macid2sta_idx_table(
struct dm_struct *dm,
u8 entry_idx,
struct cmn_sta_info *pcmn_sta_info
);
void
phydm_add_interrupt_mask_handler(
struct dm_struct *dm,
u8 interrupt_type
);
void
phydm_enable_rx_related_interrupt_handler(
struct dm_struct *dm
);
#if 0
boolean
phydm_get_txbf_en(
struct dm_struct *dm,
u16 mac_id,
u8 i
);
#endif
void
phydm_iqk_wait(
struct dm_struct *dm,
u32 timeout
);
#endif /* __ODM_INTERFACE_H__ */

179
hal/phydm/phydm_math_lib.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
const u16 db_invert_table[12][8] = {
{ 1, 1, 1, 2, 2, 2, 2, 3},
{ 3, 3, 4, 4, 4, 5, 6, 6},
{ 7, 8, 9, 10, 11, 13, 14, 16},
{ 18, 20, 22, 25, 28, 32, 35, 40},
{ 45, 50, 56, 63, 71, 79, 89, 100},
{ 112, 126, 141, 158, 178, 200, 224, 251},
{ 282, 316, 355, 398, 447, 501, 562, 631},
{ 708, 794, 891, 1000, 1122, 1259, 1413, 1585},
{ 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
{ 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
{ 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
{ 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
};
/*Y = 10*log(X)*/
s32
odm_pwdb_conversion(
s32 X,
u32 total_bit,
u32 decimal_bit
)
{
s32 Y, integer = 0, decimal = 0;
u32 i;
if (X == 0)
X = 1; /* log2(x), x can't be 0 */
for (i = (total_bit - 1); i > 0; i--) {
if (X & BIT(i)) {
integer = i;
if (i > 0)
decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */
break;
}
}
Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
return Y;
}
s32
odm_sign_conversion(
s32 value,
u32 total_bit
)
{
if (value & BIT(total_bit - 1))
value -= BIT(total_bit);
return value;
}
void
phydm_seq_sorting(
void *dm_void,
u32 *value,
u32 *rank_idx,
u32 *idx_out,
u8 seq_length
)
{
u8 i = 0, j = 0;
u32 tmp_a, tmp_b;
u32 tmp_idx_a, tmp_idx_b;
for (i = 0; i < seq_length; i++) {
rank_idx[i] = i;
/**/
}
for (i = 0; i < (seq_length - 1); i++) {
for (j = 0; j < (seq_length - 1 - i); j++) {
tmp_a = value[j];
tmp_b = value[j + 1];
tmp_idx_a = rank_idx[j];
tmp_idx_b = rank_idx[j + 1];
if (tmp_a < tmp_b) {
value[j] = tmp_b;
value[j + 1] = tmp_a;
rank_idx[j] = tmp_idx_b;
rank_idx[j + 1] = tmp_idx_a;
}
}
}
for (i = 0; i < seq_length; i++) {
idx_out[rank_idx[i]] = i + 1;
/**/
}
}
u32
odm_convert_to_db(
u32 value)
{
u8 i;
u8 j;
u32 dB;
value = value & 0xFFFF;
for (i = 0; i < 12; i++) {
if (value <= db_invert_table[i][7])
break;
}
if (i >= 12) {
return 96; /* maximum 96 dB */
}
for (j = 0; j < 8; j++) {
if (value <= db_invert_table[i][j])
break;
}
dB = (i << 3) + j + 1;
return dB;
}
u32
odm_convert_to_linear(
u32 value)
{
u8 i;
u8 j;
u32 linear;
/* 1dB~96dB */
value = value & 0xFF;
i = (u8)((value - 1) >> 3);
j = (u8)(value - 1) - (i << 3);
linear = db_invert_table[i][j];
return linear;
}

87
hal/phydm/phydm_math_lib.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_MATH_LIB_H__
#define __PHYDM_MATH_LIB_H__
#define AUTO_MATH_LIB_VERSION "1.0" /* 2017.06.06*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
s32
odm_pwdb_conversion(
s32 X,
u32 total_bit,
u32 decimal_bit
);
s32
odm_sign_conversion(
s32 value,
u32 total_bit
);
void
phydm_seq_sorting(
void *dm_void,
u32 *value,
u32 *rank_idx,
u32 *idx_out,
u8 seq_length
);
u32
odm_convert_to_db(
u32 value
);
u32
odm_convert_to_linear(
u32 value
);
#endif

427
hal/phydm/phydm_noisemonitor.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* *************************************************
* This function is for inband noise test utility only
* To obtain the inband noise level(dbm), do the following.
* 1. disable DIG and Power Saving
* 2. Set initial gain = 0x1a
* 3. Stop updating idle time pwer report (for driver read)
* - 0x80c[25]
*
* ************************************************* */
#define VALID_CNT 5
void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
{
u8 rf_path;
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data->valid_cnt[rf_path])
noise_data->sum[rf_path] /= noise_data->valid_cnt[rf_path];
else
noise_data->sum[rf_path] = 0;
}
}
s16 odm_inband_noise_monitor_n_series(struct dm_struct *dm, u8 is_pause_dig, u8 igi_value, u32 max_time)
{
u32 tmp4b;
u8 max_rf_path = 0, rf_path;
u8 reg_c50, reg_c58, valid_done = 0;
struct noise_level noise_data;
u64 start = 0, func_start = 0, func_end = 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_DebugControlInbandNoise_Nseries() ==>\n");
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/* step 1. Disable DIG && Set initial gain. */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
while (1) {
/* Stop updating idle time pwer report (for driver read) */
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
/* Read Noise Floor Report */
tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD);
/* update idle time pwer report per 5us */
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
}
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data.valid_cnt[rf_path] >= VALID_CNT)
continue;
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
PHYDM_DBG(dm, DBG_ENV_MNTR, "rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", noise_data.sum[rf_path]);
if (noise_data.valid_cnt[rf_path] == VALID_CNT)
valid_done++;
}
if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
reg_c50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0);
reg_c58 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B],
dm->noise_level.noise_all);
/* step 4. Recover the Dig */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
s16
phydm_idle_noise_measurement_ac(
struct dm_struct *dm,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
{
u32 tmp4b;
u8 max_rf_path = 0, rf_path;
u8 reg_c50, reg_e50, valid_done = 0;
u64 start = 0, func_start = 0, func_end = 0;
struct noise_level noise_data;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR, "phydm_idle_noise_measurement_ac==>\n");
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/*Step 1. Disable DIG && Set initial gain.*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
/*Step 2. Get noise power level*/
start = odm_get_current_time(dm);
while (1) {
/*Stop updating idle time pwer report (for driver read)*/
odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x1);
/*Read Noise Floor Report*/
tmp4b = odm_get_bb_reg(dm, 0xff0, MASKDWORD);
/*update idle time pwer report per 5us*/
odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x0);
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
noise_data.sval[rf_path] = noise_data.sval[rf_path] >> 1;
}
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data.valid_cnt[rf_path] >= VALID_CNT)
continue;
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n", noise_data.sum[rf_path]);
if (noise_data.valid_cnt[rf_path] == VALID_CNT)
valid_done++;
}
if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, 0xc50, MASKBYTE0);
reg_c50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_e50 = (u8)odm_get_bb_reg(dm, 0xe50, MASKBYTE0);
reg_e50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B],
dm->noise_level.noise_all);
/*Step 3. Recover the Dig*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
s16
odm_inband_noise_monitor_ac_series(
struct dm_struct *dm,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
{
s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
s32 value32, pwdb_A = 0, sval, noise, sum = 0;
boolean pd_flag;
u8 valid_cnt = 0;
u64 start = 0, func_start = 0, func_end = 0;
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
return phydm_idle_noise_measurement_ac(dm, is_pause_dig, igi_value, max_time);
if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
return 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() ==>\n");
/* step 1. Disable DIG && Set initial gain. */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
/* step 3. Get noise power level */
while (1) {
/*Set IGI=0x1C */
odm_write_dig(dm, 0x1C);
/*stop CK320&CK88 */
odm_set_bb_reg(dm, 0x8B4, BIT(6), 1);
/*Read path-A */
odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
value32 = odm_get_bb_reg(dm, 0xFA0, MASKDWORD); /*read debug port*/
rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
pd_flag = (boolean)((value32 & BIT(31)) >> 31);
/*Not in packet detection period or Tx state */
if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
/*sign conversion*/
rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
PHYDM_DBG(dm, DBG_ENV_MNTR, "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF);
}
/*Start CK320&CK88*/
odm_set_bb_reg(dm, 0x8B4, BIT(6), 0);
/*BB Reset*/
odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0)));
odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0));
/*PMAC Reset*/
odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) & (~BIT(0)));
odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0));
/*CCK Reset*/
if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) & (~BIT(4)));
odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) | BIT(4));
}
sval = pwdb_A;
if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)){
valid_cnt++;
sum += sval;
PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(dm, start) > max_time)) {
sum /= VALID_CNT;
PHYDM_DBG(dm, DBG_ENV_MNTR, "After divided, sum = %d\n", sum);
break;
}
}
}
/*ADC backoff is 12dB,*/
/*Ptarget=0x1C-110=-82dBm*/
noise = sum + 12 + 0x1C - 110;
/*Offset*/
noise = noise - 3;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
dm->noise_level.noise_all = (s16)noise;
/* step 4. Recover the Dig*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() <==\n");
return dm->noise_level.noise_all;
}
s16
odm_inband_noise_monitor(
void *dm_void,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
igi_value = 0x32; /*since HW ability is about +15~-35, we fix IGI = -60 for maximum coverage*/
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return odm_inband_noise_monitor_ac_series(dm, is_pause_dig, igi_value, max_time);
else
return odm_inband_noise_monitor_n_series(dm, is_pause_dig, igi_value, max_time);
}
void
phydm_noisy_detection(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 total_fa_cnt, total_cca_cnt;
u32 score = 0, i, score_smooth;
total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
total_fa_cnt = dm->false_alm_cnt.cnt_all;
#if 0
if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */
;
#endif
for (i = 0; i <= 16; i++) {
if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
score = 16 - i;
break;
}
}
/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) + (score << 2);
/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
score_smooth = (total_cca_cnt >= 300) ? ((dm->noisy_decision_smooth + 3) >> 3) : 0;
dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score, score_smooth, dm->noisy_decision);
}

55
hal/phydm/phydm_noisemonitor.h Normal file
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@@ -0,0 +1,55 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */
struct noise_level {
u8 value[PHYDM_MAX_RF_PATH];
s8 sval[PHYDM_MAX_RF_PATH];
s32 sum[PHYDM_MAX_RF_PATH];
u8 valid[PHYDM_MAX_RF_PATH];
u8 valid_cnt[PHYDM_MAX_RF_PATH];
};
struct odm_noise_monitor {
s8 noise[PHYDM_MAX_RF_PATH];
s16 noise_all;
};
s16 odm_inband_noise_monitor(
void *dm_void,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
);
void
phydm_noisy_detection(
void *dm_void
);
#endif

709
hal/phydm/phydm_pathdiv.c Normal file
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@@ -0,0 +1,709 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (defined(CONFIG_PATH_DIVERSITY))
#if RTL8814A_SUPPORT
void
phydm_dtp_fix_tx_path(
void *dm_void,
u8 path
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
u8 i, num_enable_path = 0;
if (path == dm_path_div->pre_tx_path)
return;
else
dm_path_div->pre_tx_path = path;
odm_set_bb_reg(dm, 0x93c, BIT(18) | BIT(19), 3);
for (i = 0; i < 4; i++) {
if (path & BIT(i))
num_enable_path++;
}
PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n", num_enable_path);
if (num_enable_path == 1) {
odm_set_bb_reg(dm, 0x93c, 0xf00000, path);
if (path == BB_PATH_A) { /* 1-1 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n");
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
} else if (path == BB_PATH_B) { /* 1-2 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n");
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0);
} else if (path == BB_PATH_C) { /* 1-3 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n");
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 0);
} else if (path == BB_PATH_D) { /* 1-4 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n");
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 0);
}
} else if (num_enable_path == 2) {
odm_set_bb_reg(dm, 0x93c, 0xf00000, path);
odm_set_bb_reg(dm, 0x940, 0xf0, path);
if (path == (BB_PATH_AB)) { /* 2-1 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1);
} else if (path == BB_PATH_AC) { /* 2-2 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A C ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1);
} else if (path == BB_PATH_AD) { /* 2-3 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A D ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1);
} else if (path == BB_PATH_BC) { /* 2-4 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B C ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0);
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1);
} else if (path == BB_PATH_BD) { /* 2-5 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B D ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1);
} else if (path == BB_PATH_CD) { /* 2-6 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C D ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 0);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 0);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1);
}
} else if (num_enable_path == 3) {
odm_set_bb_reg(dm, 0x93c, 0xf00000, path);
odm_set_bb_reg(dm, 0x940, 0xf0, path);
odm_set_bb_reg(dm, 0x940, 0xf0000, path);
if (path == BB_PATH_ABC) { /* 3-1 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B C))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1);
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 2);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1);
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 2);
/* set for 3ss */
odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0);
odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 1);
odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 2);
} else if (path == BB_PATH_ABD) { /* 3-2 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B D ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2);
/* set for 3ss */
odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0);
odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 1);
odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2);
} else if (path == BB_PATH_ACD) { /* 3-3 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A C D ))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0);
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0);
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2);
/* set for 3ss */
odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0);
odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 1);
odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2);
} else if (path == BB_PATH_BCD) { /* 3-4 */
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B C D))\n");
/* set for 1ss */
odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0);
odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1);
odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2);
/* set for 2ss */
odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1);
odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2);
/* set for 3ss */
odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 0);
odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 1);
odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2);
}
} else if (num_enable_path == 4)
PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A B C D))\n");
}
void
phydm_find_default_path(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0;
u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0;
/* 2 Default path Selection By RSSI */
rssi_avg_a = (dm_path_div->path_a_cnt_all > 0) ? (dm_path_div->path_a_sum_all / dm_path_div->path_a_cnt_all) : 0 ;
rssi_avg_b = (dm_path_div->path_b_cnt_all > 0) ? (dm_path_div->path_b_sum_all / dm_path_div->path_b_cnt_all) : 0 ;
rssi_avg_c = (dm_path_div->path_c_cnt_all > 0) ? (dm_path_div->path_c_sum_all / dm_path_div->path_c_cnt_all) : 0 ;
rssi_avg_d = (dm_path_div->path_d_cnt_all > 0) ? (dm_path_div->path_d_sum_all / dm_path_div->path_d_cnt_all) : 0 ;
dm_path_div->path_a_sum_all = 0;
dm_path_div->path_a_cnt_all = 0;
dm_path_div->path_b_sum_all = 0;
dm_path_div->path_b_cnt_all = 0;
dm_path_div->path_c_sum_all = 0;
dm_path_div->path_c_cnt_all = 0;
dm_path_div->path_d_sum_all = 0;
dm_path_div->path_d_cnt_all = 0;
if (dm_path_div->use_path_a_as_default_ant == 1) {
rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3;
if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) {
dm_path_div->is_path_a_exist = true;
dm_path_div->default_path = PATH_A;
} else
dm_path_div->is_path_a_exist = false;
} else {
if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d))
dm_path_div->default_path = PATH_A;
else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d))
dm_path_div->default_path = PATH_B;
else if (rssi_avg_c >= rssi_avg_d)
dm_path_div->default_path = PATH_C;
else
dm_path_div->default_path = PATH_D;
}
}
void
phydm_candidate_dtp_update(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
dm_path_div->num_candidate = 3;
if (dm_path_div->use_path_a_as_default_ant == 1) {
if (dm_path_div->num_tx_path == 3) {
if (dm_path_div->is_path_a_exist) {
dm_path_div->ant_candidate_1 = BB_PATH_ABC;
dm_path_div->ant_candidate_2 = BB_PATH_ABD;
dm_path_div->ant_candidate_3 = BB_PATH_ACD;
} else { /* use path BCD */
dm_path_div->num_candidate = 1;
phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);
return;
}
} else if (dm_path_div->num_tx_path == 2) {
if (dm_path_div->is_path_a_exist) {
dm_path_div->ant_candidate_1 = BB_PATH_AB;
dm_path_div->ant_candidate_2 = BB_PATH_AC;
dm_path_div->ant_candidate_3 = BB_PATH_AD;
} else {
dm_path_div->ant_candidate_1 = BB_PATH_BC;
dm_path_div->ant_candidate_2 = BB_PATH_BD;
dm_path_div->ant_candidate_3 = BB_PATH_CD;
}
}
} else {
/* 2 3 TX mode */
if (dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */
if (dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
dm_path_div->ant_candidate_1 = BB_PATH_ABC;
dm_path_div->ant_candidate_2 = BB_PATH_ABD;
dm_path_div->ant_candidate_3 = BB_PATH_ACD;
} else if (dm_path_div->default_path == PATH_B) {
dm_path_div->ant_candidate_1 = BB_PATH_ABC;
dm_path_div->ant_candidate_2 = BB_PATH_ABD;
dm_path_div->ant_candidate_3 = BB_PATH_BCD;
} else if (dm_path_div->default_path == PATH_C) {
dm_path_div->ant_candidate_1 = BB_PATH_ABC;
dm_path_div->ant_candidate_2 = BB_PATH_ACD;
dm_path_div->ant_candidate_3 = BB_PATH_BCD;
} else if (dm_path_div->default_path == PATH_D) {
dm_path_div->ant_candidate_1 = BB_PATH_ABD;
dm_path_div->ant_candidate_2 = BB_PATH_ACD;
dm_path_div->ant_candidate_3 = BB_PATH_BCD;
}
}
/* 2 2 TX mode */
else if (dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */
if (dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
dm_path_div->ant_candidate_1 = BB_PATH_AB;
dm_path_div->ant_candidate_2 = BB_PATH_AC;
dm_path_div->ant_candidate_3 = BB_PATH_AD;
} else if (dm_path_div->default_path == PATH_B) {
dm_path_div->ant_candidate_1 = BB_PATH_AB;
dm_path_div->ant_candidate_2 = BB_PATH_BC;
dm_path_div->ant_candidate_3 = BB_PATH_BD;
} else if (dm_path_div->default_path == PATH_C) {
dm_path_div->ant_candidate_1 = BB_PATH_AC;
dm_path_div->ant_candidate_2 = BB_PATH_BC;
dm_path_div->ant_candidate_3 = BB_PATH_CD;
} else if (dm_path_div->default_path == PATH_D) {
dm_path_div->ant_candidate_1 = BB_PATH_AD;
dm_path_div->ant_candidate_2 = BB_PATH_BD;
dm_path_div->ant_candidate_3 = BB_PATH_CD;
}
}
}
}
void
phydm_dynamic_tx_path(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
struct sta_info *entry;
u32 i;
u8 num_client = 0;
u8 h2c_parameter[6] = {0};
if (!dm->is_linked) { /* is_linked==False */
PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n");
if (dm_path_div->is_become_linked == true) {
PHYDM_DBG(dm, DBG_PATH_DIV, " [Be disconnected]----->\n");
dm_path_div->is_become_linked = dm->is_linked;
}
return;
} else {
if (dm_path_div->is_become_linked == false) {
PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n");
dm_path_div->is_become_linked = dm->is_linked;
}
}
/* 2 [period CTRL] */
if (dm_path_div->dtp_period >= 2)
dm_path_div->dtp_period = 0;
else {
/* PHYDM_DBG(dm,DBG_PATH_DIV, "Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",dm_path_div->dtp_period); */
dm_path_div->dtp_period++;
return;
}
/* 2 [Fix path] */
if (dm->path_select != PHYDM_AUTO_PATH)
return;
/* 2 [Check Bfer] */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (BEAMFORMING_SUPPORT == 1)
{
enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap);
if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */
if (dm_path_div->fix_path_bfer == 0) {
PHYDM_DBG(dm, DBG_PATH_DIV, "[ PathDiv : OFF ] BFmer ==1\n");
dm_path_div->fix_path_bfer = 1 ;
}
return;
} else { /* BFmer Off && Div Off->Div On */
if (dm_path_div->fix_path_bfer == 1) {
PHYDM_DBG(dm, DBG_PATH_DIV, "[ PathDiv : ON ] BFmer ==0\n");
dm_path_div->fix_path_bfer = 0;
}
}
}
#endif
#endif
if (dm_path_div->use_path_a_as_default_ant == 1) {
phydm_find_default_path(dm);
phydm_candidate_dtp_update(dm);
} else {
if (dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) {
phydm_find_default_path(dm);
phydm_candidate_dtp_update(dm);
dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
}
else if (dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
dm_path_div->dtp_check_patha_counter++;
if (dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) {
dm_path_div->dtp_check_patha_counter = 0;
dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
}
#if 0
/* 2 Search space update */
else {
/* 1. find the worst candidate */
/* 2. repalce the worst candidate */
}
#endif
}
}
/* 2 Dynamic path Selection H2C */
if (dm_path_div->num_candidate == 1)
return;
else {
h2c_parameter[0] = dm_path_div->num_candidate;
h2c_parameter[1] = dm_path_div->num_tx_path;
h2c_parameter[2] = dm_path_div->ant_candidate_1;
h2c_parameter[3] = dm_path_div->ant_candidate_2;
h2c_parameter[4] = dm_path_div->ant_candidate_3;
odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
}
}
void
phydm_dynamic_tx_path_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
void *adapter = dm->adapter;
u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD };
u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC};
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
dm_path_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0;
PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n", dm_path_div->is_u3_mode);
#else
dm_path_div->is_u3_mode = 1;
#endif
PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n");
memcpy(&dm_path_div->search_space_2[0], &search_space_2[0],
NUM_CHOOSE2_FROM4);
memcpy(&dm_path_div->search_space_3[0], &search_space_3[0],
NUM_CHOOSE3_FROM4);
dm_path_div->use_path_a_as_default_ant = 1;
dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
dm->path_select = PHYDM_AUTO_PATH;
dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
if (dm_path_div->is_u3_mode) {
dm_path_div->num_tx_path = 3;
phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);/* 3TX Set Init TX path*/
} else {
dm_path_div->num_tx_path = 2;
phydm_dtp_fix_tx_path(dm, BB_PATH_BC);/* 2TX // Set Init TX path*/
}
}
void
phydm_process_rssi_for_path_div(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
return;
if (pktinfo->data_rate <= ODM_RATE11M)
return;
if (dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
#if RTL8814A_SUPPORT
if (dm->support_ic_type & ODM_RTL8814A) {
dm_path_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0];
dm_path_div->path_a_cnt_all++;
dm_path_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1];
dm_path_div->path_b_cnt_all++;
dm_path_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2];
dm_path_div->path_c_cnt_all++;
dm_path_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3];
dm_path_div->path_d_cnt_all++;
}
#endif
} else {
dm_path_div->path_a_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[0];
dm_path_div->path_a_cnt[pktinfo->station_id]++;
dm_path_div->path_b_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[1];
dm_path_div->path_b_cnt[pktinfo->station_id]++;
}
}
#endif /* #if RTL8814A_SUPPORT */
void
odm_pathdiv_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
u32 used = *_used;
u32 out_len = *_out_len;
dm->path_select = (dm_value[0] & 0xf);
PDM_SNPF(out_len, used, output + used, out_len - used,
"Path_select = (( 0x%x ))\n", dm->path_select);
/* 2 [Fix path] */
if (dm->path_select != PHYDM_AUTO_PATH) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Trun on path [%s%s%s%s]\n",
((dm->path_select) & 0x1) ? "A" : "",
((dm->path_select) & 0x2) ? "B" : "",
((dm->path_select) & 0x4) ? "C" : "",
((dm->path_select) & 0x8) ? "D" : "");
phydm_dtp_fix_tx_path(dm, dm->path_select);
} else
PDM_SNPF(out_len, used, output + used, out_len - used,
"%s\n", "Auto path");
*_used = used;
*_out_len = out_len;
}
#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
void
phydm_c2h_dtp_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
)
{
#if (defined(CONFIG_PATH_DIVERSITY))
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
u8 macid = cmd_buf[0];
u8 target = cmd_buf[1];
u8 nsc_1 = cmd_buf[2];
u8 nsc_2 = cmd_buf[3];
u8 nsc_3 = cmd_buf[4];
PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target);
/*
if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3))
{
phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_1);
}
else if( nsc_2 >= nsc_3)
{
phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_2);
}
else
{
phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_3);
}
*/
#endif
}
void
odm_path_diversity(
void *dm_void
)
{
#if (defined(CONFIG_PATH_DIVERSITY))
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_PATH_DIV)) {
PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n");
return;
}
#if RTL8812A_SUPPORT
if (dm->support_ic_type & ODM_RTL8812)
odm_path_diversity_8812a(dm);
else
#endif
#if RTL8814A_SUPPORT
if (dm->support_ic_type & ODM_RTL8814A)
phydm_dynamic_tx_path(dm);
else
#endif
{}
#endif
}
void
phydm_path_diversity_init(
void *dm_void
)
{
#if (defined(CONFIG_PATH_DIVERSITY))
struct dm_struct *dm = (struct dm_struct *)dm_void;
/*dm->support_ability |= ODM_BB_PATH_DIV;*/
if (*dm->mp_mode == true)
return;
if (!(dm->support_ability & ODM_BB_PATH_DIV)) {
PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n");
return;
}
#if RTL8812A_SUPPORT
if (dm->support_ic_type & ODM_RTL8812)
odm_path_diversity_init_8812a(dm);
else
#endif
#if RTL8814A_SUPPORT
if (dm->support_ic_type & ODM_RTL8814A)
phydm_dynamic_tx_path_init(dm);
else
#endif
{}
#endif
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/*
* 2011/12/02 MH Copy from MP oursrc for temporarily test.
* */
void
odm_path_div_chk_ant_switch_callback(
struct phydm_timer_list *timer
)
{
}
void
odm_path_div_chk_ant_switch_workitem_callback(
void *context
)
{
}
void
odm_cck_tx_path_diversity_callback(
struct phydm_timer_list *timer
)
{
}
void
odm_cck_tx_path_diversity_work_item_callback(
void *context
)
{
}
u8
odm_sw_ant_div_select_scan_chnl(
void *adapter
)
{
return 0;
}
void
odm_sw_ant_div_construct_scan_chnl(
void *adapter,
u8 scan_chnl
)
{
}
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */

304
hal/phydm/phydm_pathdiv.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
#if (defined(CONFIG_PATH_DIVERSITY))
#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */
#define NUM_RESET_DTP_PERIOD 5
#define ANT_DECT_RSSI_TH 3
#define PATH_A 1
#define PATH_B 2
#define PATH_C 3
#define PATH_D 4
#define PHYDM_AUTO_PATH 0
#define PHYDM_FIX_PATH 1
#define NUM_CHOOSE2_FROM4 6
#define NUM_CHOOSE3_FROM4 4
enum phydm_dtp_state {
PHYDM_DTP_INIT = 1,
PHYDM_DTP_RUNNING_1
};
enum phydm_path_div_type {
PHYDM_2R_PATH_DIV = 1,
PHYDM_4R_PATH_DIV = 2
};
void
phydm_process_rssi_for_path_div(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
struct _ODM_PATH_DIVERSITY_ {
u8 resp_tx_path;
u8 path_sel[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u8 phydm_path_div_type;
#if RTL8814A_SUPPORT
u32 path_a_sum_all;
u32 path_b_sum_all;
u32 path_c_sum_all;
u32 path_d_sum_all;
u32 path_a_cnt_all;
u32 path_b_cnt_all;
u32 path_c_cnt_all;
u32 path_d_cnt_all;
u8 dtp_period;
boolean is_become_linked;
boolean is_u3_mode;
u8 num_tx_path;
u8 default_path;
u8 num_candidate;
u8 ant_candidate_1;
u8 ant_candidate_2;
u8 ant_candidate_3;
u8 phydm_dtp_state;
u8 dtp_check_patha_counter;
boolean fix_path_bfer;
u8 search_space_2[NUM_CHOOSE2_FROM4];
u8 search_space_3[NUM_CHOOSE3_FROM4];
u8 pre_tx_path;
u8 use_path_a_as_default_ant;
boolean is_path_a_exist;
#endif
};
#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
void
phydm_c2h_dtp_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
void
phydm_path_diversity_init(
void *dm_void
);
void
odm_path_diversity(
void *dm_void
);
void
odm_pathdiv_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
/* 1 [OLD IC]-------------------------------------------------------------------------------- */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
/* #define PATHDIV_ENABLE 1 */
#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi
#define path_div_check_before_link8192c odm_path_diversity_before_link92c
struct _path_div_parameter_define_ {
u32 org_5g_rege30;
u32 org_5g_regc14;
u32 org_5g_regca0;
u32 swt_5g_rege30;
u32 swt_5g_regc14;
u32 swt_5g_regca0;
/* for 2G IQK information */
u32 org_2g_regc80;
u32 org_2g_regc4c;
u32 org_2g_regc94;
u32 org_2g_regc14;
u32 org_2g_regca0;
u32 swt_2g_regc80;
u32 swt_2g_regc4c;
u32 swt_2g_regc94;
u32 swt_2g_regc14;
u32 swt_2g_regca0;
};
void
odm_path_diversity_init_92c(
void *adapter
);
void
odm_2t_path_diversity_init_92c(
void *adapter
);
void
odm_1t_path_diversity_init_92c(
void *adapter
);
boolean
odm_is_connected_92c(
void *adapter
);
boolean
odm_path_diversity_before_link92c(
/* struct void* adapter */
struct dm_struct *dm
);
void
odm_path_diversity_after_link_92c(
void *adapter
);
void
odm_set_resp_path_92c(
void *adapter,
u8 default_resp_path
);
void
odm_ofdm_tx_path_diversity_92c(
void *adapter
);
void
odm_cck_tx_path_diversity_92c(
void *adapter
);
void
odm_reset_path_diversity_92c(
void *adapter
);
void
odm_cck_tx_path_diversity_callback(
struct phydm_timer_list *timer
);
void
odm_cck_tx_path_diversity_work_item_callback(
void *context
);
void
odm_path_div_chk_ant_switch_callback(
struct phydm_timer_list *timer
);
void
odm_path_div_chk_ant_switch_workitem_callback(
void *context
);
void
odm_path_div_chk_ant_switch(
struct dm_struct *dm
);
void
odm_cck_path_diversity_chk_per_pkt_rssi(
void *adapter,
boolean is_def_port,
boolean is_match_bssid,
struct _WLAN_STA *entry,
PRT_RFD rfd,
u8 *desc
);
void
odm_path_div_chk_per_pkt_rssi(
void *adapter,
boolean is_def_port,
boolean is_match_bssid,
struct _WLAN_STA *entry,
PRT_RFD rfd
);
void
odm_path_div_rest_after_link(
struct dm_struct *dm
);
void
odm_fill_tx_path_in_txdesc(
void *adapter,
PRT_TCB tcb,
u8 *desc
);
void
odm_path_div_init_92d(
struct dm_struct *dm
);
u8
odm_sw_ant_div_select_scan_chnl(
void *adapter
);
void
odm_sw_ant_div_construct_scan_chnl(
void *adapter,
u8 scan_chnl
);
#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */
#endif /* #ifndef __ODMPATHDIV_H__ */

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hal/phydm/phydm_pow_train.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_POWER_TRAINING_SUPPORT
void
phydm_reset_pt_para(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
}
void
phydm_update_power_training_state(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u32 pt_score_tmp = 0;
u32 crc_ok_cnt;
u32 cca_all_cnt;
/*is_disable_power_training is the key to H2C to disable/enable power training*/
/*if is_disable_power_training == 1, it will use largest power*/
if (!(dm->support_ability & ODM_BB_PWR_TRAIN)) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
return;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __FUNCTION__);
if (pow_train_t->force_power_training_state == DISABLE_POW_TRAIN) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
return;
} else if (pow_train_t->force_power_training_state == ENABLE_POW_TRAIN) {
dm->is_disable_power_training = false;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
return;
} else if (pow_train_t->force_power_training_state == DYNAMIC_POW_TRAIN) {
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
if (!dm->is_linked) {
dm->is_disable_power_training = true;
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to no link.\n");
return;
}
/* First connect */
if ((dm->is_linked) && (!dig_t->is_media_connect)) {
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "(PT)First Connect\n");
return;
}
/* Compute score */
crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm + dm->phy_dbg_info.num_qry_phy_status_cck;
cca_all_cnt = fa_cnt->cnt_cca_all;
if (crc_ok_cnt < cca_all_cnt) {
/* crc_ok <= (2/3)*cca */
if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_all_cnt)
pt_score_tmp = DISABLE_PT_SCORE;
/* crc_ok <= (4/5)*cca */
else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_all_cnt)
pt_score_tmp = KEEP_PRE_PT_SCORE;
/* crc_ok > (4/5)*cca */
else
pt_score_tmp = ENABLE_PT_SCORE;
} else {
pt_score_tmp = ENABLE_PT_SCORE;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "crc_ok_cnt = %d, cnt_cca_all = %d\n",
crc_ok_cnt, cca_all_cnt);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
dm->phy_dbg_info.num_qry_phy_status_ofdm, dm->phy_dbg_info.num_qry_phy_status_cck);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = %d\n", pt_score_tmp);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = 0(DISABLE), 1(KEEP), 2(ENABLE)\n");
/* smoothing */
pow_train_t->pow_train_score = (pt_score_tmp << 4) + (pow_train_t->pow_train_score >> 1) + (pow_train_t->pow_train_score >> 2);
pt_score_tmp = (pow_train_t->pow_train_score + 32) >> 6;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pow_train_score = %d, score after smoothing = %d\n",
pow_train_t->pow_train_score, pt_score_tmp);
/* mode decision */
if (pt_score_tmp == ENABLE_PT_SCORE) {
dm->is_disable_power_training = false;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable power training under dynamic.\n");
} else if (pt_score_tmp == DISABLE_PT_SCORE) {
dm->is_disable_power_training = true;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT due to noisy.\n");
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Final, score = %d, is_disable_power_training = %d\n",
pt_score_tmp, dm->is_disable_power_training);
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
} else {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to unknown pt state.\n");
return;
}
}
void
phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 i;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"0: Dynamic state\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"1: Enable PT\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"2: Disable PT\n");
} else {
for (i = 0; i < 10; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
}
}
if (var1[0] == 0) {
pow_train_t->force_power_training_state = DYNAMIC_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Dynamic state\n");
} else if (var1[0] == 1) {
pow_train_t->force_power_training_state = ENABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Enable PT\n");
} else if (var1[0] == 2) {
pow_train_t->force_power_training_state = DISABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Disable PT\n");
} else {
PDM_SNPF(out_len, used, output + used,
out_len - used, "Set Error\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif

86
hal/phydm/phydm_pow_train.h Normal file
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@@ -0,0 +1,86 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_POW_TRAIN_H__
#define __PHYDM_POW_TRAIN_H__
#define POW_TRAIN_VERSION "1.0" /* 2017.07.0141 Dino, Add phydm_pow_train.h*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#ifdef PHYDM_POWER_TRAINING_SUPPORT
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct phydm_pow_train_stuc {
u8 force_power_training_state;
u32 pow_train_score;
};
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
enum pow_train_state {
DYNAMIC_POW_TRAIN = 0,
ENABLE_POW_TRAIN = 1,
DISABLE_POW_TRAIN = 2
};
enum power_training_score {
DISABLE_PT_SCORE = 0,
KEEP_PRE_PT_SCORE = 1,
ENABLE_PT_SCORE = 2
};
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
phydm_update_power_training_state(
void *dm_void
);
void
phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
#endif

747
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPREDEFINE_H__
#define __PHYDMPREDEFINE_H__
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define PHYDM_CODE_BASE "PHYDM_V024"
#define PHYDM_RELEASE_DATE "20171213"
/*PHYDM API status*/
#define PHYDM_SET_FAIL 0
#define PHYDM_SET_SUCCESS 1
#define PHYDM_SET_NO_NEED 3
/*PHYDM Set/Revert*/
#define PHYDM_SET 1
#define PHYDM_REVERT 2
/* Max path of IC */
/*N-IC*/
#define MAX_PATH_NUM_8188E 1
#define MAX_PATH_NUM_8188F 1
#define MAX_PATH_NUM_8710B 1
#define MAX_PATH_NUM_8723B 1
#define MAX_PATH_NUM_8723D 1
#define MAX_PATH_NUM_8703B 1
#define MAX_PATH_NUM_8192E 2
#define MAX_PATH_NUM_8192F 2
#define MAX_PATH_NUM_8197F 2
#define MAX_PATH_NUM_8198F 4
/*AC-IC*/
#define MAX_PATH_NUM_8821A 1
#define MAX_PATH_NUM_8881A 1
#define MAX_PATH_NUM_8821C 1
#define MAX_PATH_NUM_8195B 1
#define MAX_PATH_NUM_8812A 2
#define MAX_PATH_NUM_8822B 2
#define MAX_PATH_NUM_8822C 2
#define MAX_PATH_NUM_8814A 4
#define MAX_PATH_NUM_8814B 4
#define MAX_PATH_NUM_8814C 4
/* Max RF path */
#define PHYDM_MAX_RF_PATH_N 2 /*For old N-series IC*/
#define PHYDM_MAX_RF_PATH 4
/* number of entry */
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
#ifdef DM_ODM_CE_MAC80211
/* defined in wifi.h (32+1) */
#else
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/
#endif
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define ASSOCIATE_ENTRY_NUM NUM_STAT
#define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)
#else
#define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)
#endif
/* -----MGN rate--------------------------------- */
enum ODM_MGN_RATE {
ODM_MGN_1M = 0x02,
ODM_MGN_2M = 0x04,
ODM_MGN_5_5M = 0x0B,
ODM_MGN_6M = 0x0C,
ODM_MGN_9M = 0x12,
ODM_MGN_11M = 0x16,
ODM_MGN_12M = 0x18,
ODM_MGN_18M = 0x24,
ODM_MGN_24M = 0x30,
ODM_MGN_36M = 0x48,
ODM_MGN_48M = 0x60,
ODM_MGN_54M = 0x6C,
ODM_MGN_MCS32 = 0x7F,
ODM_MGN_MCS0 = 0x80,
ODM_MGN_MCS1,
ODM_MGN_MCS2,
ODM_MGN_MCS3,
ODM_MGN_MCS4,
ODM_MGN_MCS5,
ODM_MGN_MCS6,
ODM_MGN_MCS7 = 0x87,
ODM_MGN_MCS8,
ODM_MGN_MCS9,
ODM_MGN_MCS10,
ODM_MGN_MCS11,
ODM_MGN_MCS12,
ODM_MGN_MCS13,
ODM_MGN_MCS14,
ODM_MGN_MCS15,
ODM_MGN_MCS16 = 0x90,
ODM_MGN_MCS17,
ODM_MGN_MCS18,
ODM_MGN_MCS19,
ODM_MGN_MCS20,
ODM_MGN_MCS21,
ODM_MGN_MCS22,
ODM_MGN_MCS23,
ODM_MGN_MCS24 = 0x98,
ODM_MGN_MCS25,
ODM_MGN_MCS26,
ODM_MGN_MCS27,
ODM_MGN_MCS28,
ODM_MGN_MCS29,
ODM_MGN_MCS30,
ODM_MGN_MCS31,
ODM_MGN_VHT1SS_MCS0 = 0xa0,
ODM_MGN_VHT1SS_MCS1,
ODM_MGN_VHT1SS_MCS2,
ODM_MGN_VHT1SS_MCS3,
ODM_MGN_VHT1SS_MCS4,
ODM_MGN_VHT1SS_MCS5,
ODM_MGN_VHT1SS_MCS6,
ODM_MGN_VHT1SS_MCS7,
ODM_MGN_VHT1SS_MCS8,
ODM_MGN_VHT1SS_MCS9,
ODM_MGN_VHT2SS_MCS0 = 0xaa,
ODM_MGN_VHT2SS_MCS1 = 0xab,
ODM_MGN_VHT2SS_MCS2,
ODM_MGN_VHT2SS_MCS3,
ODM_MGN_VHT2SS_MCS4,
ODM_MGN_VHT2SS_MCS5 = 0xaf,
ODM_MGN_VHT2SS_MCS6 = 0xb0,
ODM_MGN_VHT2SS_MCS7,
ODM_MGN_VHT2SS_MCS8,
ODM_MGN_VHT2SS_MCS9 = 0xb3,
ODM_MGN_VHT3SS_MCS0 = 0xb4,
ODM_MGN_VHT3SS_MCS1,
ODM_MGN_VHT3SS_MCS2,
ODM_MGN_VHT3SS_MCS3,
ODM_MGN_VHT3SS_MCS4,
ODM_MGN_VHT3SS_MCS5,
ODM_MGN_VHT3SS_MCS6,
ODM_MGN_VHT3SS_MCS7 = 0xbb,
ODM_MGN_VHT3SS_MCS8 = 0xbc,
ODM_MGN_VHT3SS_MCS9 = 0xbd,
ODM_MGN_VHT4SS_MCS0 = 0xbe,
ODM_MGN_VHT4SS_MCS1,
ODM_MGN_VHT4SS_MCS2,
ODM_MGN_VHT4SS_MCS3,
ODM_MGN_VHT4SS_MCS4,
ODM_MGN_VHT4SS_MCS5,
ODM_MGN_VHT4SS_MCS6,
ODM_MGN_VHT4SS_MCS7,
ODM_MGN_VHT4SS_MCS8,
ODM_MGN_VHT4SS_MCS9 = 0xc7,
ODM_MGN_UNKNOWN
};
#define ODM_MGN_MCS0_SG 0xc0
#define ODM_MGN_MCS1_SG 0xc1
#define ODM_MGN_MCS2_SG 0xc2
#define ODM_MGN_MCS3_SG 0xc3
#define ODM_MGN_MCS4_SG 0xc4
#define ODM_MGN_MCS5_SG 0xc5
#define ODM_MGN_MCS6_SG 0xc6
#define ODM_MGN_MCS7_SG 0xc7
#define ODM_MGN_MCS8_SG 0xc8
#define ODM_MGN_MCS9_SG 0xc9
#define ODM_MGN_MCS10_SG 0xca
#define ODM_MGN_MCS11_SG 0xcb
#define ODM_MGN_MCS12_SG 0xcc
#define ODM_MGN_MCS13_SG 0xcd
#define ODM_MGN_MCS14_SG 0xce
#define ODM_MGN_MCS15_SG 0xcf
/* -----DESC rate--------------------------------- */
#define ODM_RATEMCS15_SG 0x1c
#define ODM_RATEMCS32 0x20
enum phydm_ctrl_info_rate {
ODM_RATE1M = 0x00,
ODM_RATE2M = 0x01,
ODM_RATE5_5M = 0x02,
ODM_RATE11M = 0x03,
/* OFDM Rates, TxHT = 0 */
ODM_RATE6M = 0x04,
ODM_RATE9M = 0x05,
ODM_RATE12M = 0x06,
ODM_RATE18M = 0x07,
ODM_RATE24M = 0x08,
ODM_RATE36M = 0x09,
ODM_RATE48M = 0x0A,
ODM_RATE54M = 0x0B,
/* MCS Rates, TxHT = 1 */
ODM_RATEMCS0 = 0x0C,
ODM_RATEMCS1 = 0x0D,
ODM_RATEMCS2 = 0x0E,
ODM_RATEMCS3 = 0x0F,
ODM_RATEMCS4 = 0x10,
ODM_RATEMCS5 = 0x11,
ODM_RATEMCS6 = 0x12,
ODM_RATEMCS7 = 0x13,
ODM_RATEMCS8 = 0x14,
ODM_RATEMCS9 = 0x15,
ODM_RATEMCS10 = 0x16,
ODM_RATEMCS11 = 0x17,
ODM_RATEMCS12 = 0x18,
ODM_RATEMCS13 = 0x19,
ODM_RATEMCS14 = 0x1A,
ODM_RATEMCS15 = 0x1B,
ODM_RATEMCS16 = 0x1C,
ODM_RATEMCS17 = 0x1D,
ODM_RATEMCS18 = 0x1E,
ODM_RATEMCS19 = 0x1F,
ODM_RATEMCS20 = 0x20,
ODM_RATEMCS21 = 0x21,
ODM_RATEMCS22 = 0x22,
ODM_RATEMCS23 = 0x23,
ODM_RATEMCS24 = 0x24,
ODM_RATEMCS25 = 0x25,
ODM_RATEMCS26 = 0x26,
ODM_RATEMCS27 = 0x27,
ODM_RATEMCS28 = 0x28,
ODM_RATEMCS29 = 0x29,
ODM_RATEMCS30 = 0x2A,
ODM_RATEMCS31 = 0x2B,
ODM_RATEVHTSS1MCS0 = 0x2C,
ODM_RATEVHTSS1MCS1 = 0x2D,
ODM_RATEVHTSS1MCS2 = 0x2E,
ODM_RATEVHTSS1MCS3 = 0x2F,
ODM_RATEVHTSS1MCS4 = 0x30,
ODM_RATEVHTSS1MCS5 = 0x31,
ODM_RATEVHTSS1MCS6 = 0x32,
ODM_RATEVHTSS1MCS7 = 0x33,
ODM_RATEVHTSS1MCS8 = 0x34,
ODM_RATEVHTSS1MCS9 = 0x35,
ODM_RATEVHTSS2MCS0 = 0x36,
ODM_RATEVHTSS2MCS1 = 0x37,
ODM_RATEVHTSS2MCS2 = 0x38,
ODM_RATEVHTSS2MCS3 = 0x39,
ODM_RATEVHTSS2MCS4 = 0x3A,
ODM_RATEVHTSS2MCS5 = 0x3B,
ODM_RATEVHTSS2MCS6 = 0x3C,
ODM_RATEVHTSS2MCS7 = 0x3D,
ODM_RATEVHTSS2MCS8 = 0x3E,
ODM_RATEVHTSS2MCS9 = 0x3F,
ODM_RATEVHTSS3MCS0 = 0x40,
ODM_RATEVHTSS3MCS1 = 0x41,
ODM_RATEVHTSS3MCS2 = 0x42,
ODM_RATEVHTSS3MCS3 = 0x43,
ODM_RATEVHTSS3MCS4 = 0x44,
ODM_RATEVHTSS3MCS5 = 0x45,
ODM_RATEVHTSS3MCS6 = 0x46,
ODM_RATEVHTSS3MCS7 = 0x47,
ODM_RATEVHTSS3MCS8 = 0x48,
ODM_RATEVHTSS3MCS9 = 0x49,
ODM_RATEVHTSS4MCS0 = 0x4A,
ODM_RATEVHTSS4MCS1 = 0x4B,
ODM_RATEVHTSS4MCS2 = 0x4C,
ODM_RATEVHTSS4MCS3 = 0x4D,
ODM_RATEVHTSS4MCS4 = 0x4E,
ODM_RATEVHTSS4MCS5 = 0x4F,
ODM_RATEVHTSS4MCS6 = 0x50,
ODM_RATEVHTSS4MCS7 = 0x51,
ODM_RATEVHTSS4MCS8 = 0x52,
ODM_RATEVHTSS4MCS9 = 0x53,
};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
#else
#if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)
#elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)
#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)
#elif (RTL8812A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)
#elif (RTL8814A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)
#else
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define CONFIG_SFW_SUPPORTED
#endif
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* ODM_CMNINFO_INTERFACE */
enum odm_interface {
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
};
/*========[Run time IC flag] ===============================================================================]*/
enum phydm_ic {
ODM_RTL8188E = BIT(0),
ODM_RTL8812 = BIT(1),
ODM_RTL8821 = BIT(2),
ODM_RTL8192E = BIT(3),
ODM_RTL8723B = BIT(4),
ODM_RTL8814A = BIT(5),
ODM_RTL8881A = BIT(6),
ODM_RTL8822B = BIT(7),
ODM_RTL8703B = BIT(8),
ODM_RTL8195A = BIT(9),
ODM_RTL8188F = BIT(10),
ODM_RTL8723D = BIT(11),
ODM_RTL8197F = BIT(12),
ODM_RTL8821C = BIT(13),
ODM_RTL8814B = BIT(14),
ODM_RTL8198F = BIT(15),
ODM_RTL8710B = BIT(16),
ODM_RTL8192F = BIT(17),
ODM_RTL8822C = BIT(18),
ODM_RTL8195B = BIT(19)
};
#define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A | ODM_RTL8710B)
#define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
#define ODM_IC_N_3SS 0
#define ODM_IC_N_4SS (ODM_RTL8198F)
#define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195B)
#define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8822C)
#define ODM_IC_AC_3SS 0
#define ODM_IC_AC_4SS (ODM_RTL8814A | ODM_RTL8814B)
/*====the following macro DO NOT need to update when adding a new IC======= */
#define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS)
#define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS)
#define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS)
#define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS)
#define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
#define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
#define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS)
#define PHYDM_IC_ABOVE_4SS ODM_IC_4SS
#define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS | ODM_IC_N_4SS)
#define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS | ODM_IC_AC_3SS | ODM_IC_AC_4SS)
/*====================================================*/
#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)
/*[EDCCA]*/
#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
#define ODM_IC_GAIN_IDX_EDCCA (ODM_IC_11N_GAIN_IDX_EDCCA | ODM_IC_11AC_GAIN_IDX_EDCCA)
/*[Phy status type]*/
#define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B)
#define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B)
/*[FW Type]*/
#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F)
/*[LA mode]*/
#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F)
/*[BF]*/
#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F)
#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B | ODM_RTL8195B | ODM_RTL8198F)
#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F)
/*========[Compile time IC flag] ===============================================================================]*/
/*========[AC/N Support] ===========================*/
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
#define ODM_IC_11AC_SERIES_SUPPORT 1
#else
#define ODM_IC_11AC_SERIES_SUPPORT 0
#endif
#define ODM_IC_11N_SERIES_SUPPORT 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define ODM_IC_11AC_SERIES_SUPPORT 1
#define ODM_IC_11N_SERIES_SUPPORT 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#define ODM_IC_11AC_SERIES_SUPPORT 1
#define ODM_IC_11N_SERIES_SUPPORT 1
#else /*ODM_CE*/
#if ((RTL8188E_SUPPORT == 1) || \
(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \
(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
#define ODM_IC_11N_SERIES_SUPPORT 1
#define ODM_IC_11AC_SERIES_SUPPORT 0
#else
#define ODM_IC_11N_SERIES_SUPPORT 0
#define ODM_IC_11AC_SERIES_SUPPORT 1
#endif
#endif
/*===IC SS Compile Flag, prepare for code size reduction==============*/
#if ((RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) ||\
(RTL8723D_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\
(RTL8195A_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) || (RTL8195B_SUPPORT == 1))
#define PHYDM_COMPILE_IC_1SS
#endif
#if ((RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
#define PHYDM_COMPILE_IC_2SS
#endif
/*#define PHYDM_COMPILE_IC_3SS*/
#if ((RTL8814B_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8198F_SUPPORT == 1))
#define PHYDM_COMPILE_IC_4SS
#endif
/*==[ABOVE N-SS COMPILE FLAG]=============================*/
#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
#define PHYDM_COMPILE_ABOVE_1SS
#endif
#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
#define PHYDM_COMPILE_ABOVE_2SS
#endif
#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
#define PHYDM_COMPILE_ABOVE_3SS
#endif
#if (defined(PHYDM_COMPILE_IC_4SS))
#define PHYDM_COMPILE_ABOVE_4SS
#endif
/*========[New Phy-Status Support] =========================================================================]*/
#if (RTL8824B_SUPPORT == 1)
#define CONFIG_PHYSTS_3RD_TYPE 1
#else
#define CONFIG_PHYSTS_3RD_TYPE 0
#endif
#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) )
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1
#else
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0
#endif
/*==================================================================================================]*/
#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
#define PHYDM_COMMON_API_SUPPORT
#endif
#define CCK_RATE_NUM 4
#define OFDM_RATE_NUM 8
#define LEGACY_RATE_NUM 12
#define HT_RATE_NUM_4SS 32
#define VHT_RATE_NUM_4SS 40
#define HT_RATE_NUM_3SS 24
#define VHT_RATE_NUM_3SS 30
#define HT_RATE_NUM_2SS 16
#define VHT_RATE_NUM_2SS 20
#define HT_RATE_NUM_1SS 8
#define VHT_RATE_NUM_1SS 10
#if (defined(PHYDM_COMPILE_ABOVE_4SS))
#define HT_RATE_NUM HT_RATE_NUM_4SS
#define VHT_RATE_NUM VHT_RATE_NUM_4SS
#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
#define HT_RATE_NUM HT_RATE_NUM_3SS
#define VHT_RATE_NUM VHT_RATE_NUM_3SS
#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
#define HT_RATE_NUM HT_RATE_NUM_2SS
#define VHT_RATE_NUM VHT_RATE_NUM_2SS
#else
#define HT_RATE_NUM HT_RATE_NUM_1SS
#define VHT_RATE_NUM VHT_RATE_NUM_1SS
#endif
#define LOW_BW_RATE_NUM VHT_RATE_NUM
/* ODM_CMNINFO_CUT_VER */
enum odm_cut_version {
ODM_CUT_A = 0,
ODM_CUT_B = 1,
ODM_CUT_C = 2,
ODM_CUT_D = 3,
ODM_CUT_E = 4,
ODM_CUT_F = 5,
ODM_CUT_G = 6,
ODM_CUT_H = 7,
ODM_CUT_I = 8,
ODM_CUT_J = 9,
ODM_CUT_K = 10,
ODM_CUT_TEST = 15,
};
/* ODM_CMNINFO_FAB_VER */
enum odm_fab {
ODM_TSMC = 0,
ODM_UMC = 1,
};
/* ODM_CMNINFO_OP_MODE */
enum odm_operation_mode {
ODM_NO_LINK = BIT(0),
ODM_LINK = BIT(1),
ODM_SCAN = BIT(2),
ODM_POWERSAVE = BIT(3),
ODM_AP_MODE = BIT(4),
ODM_CLIENT_MODE = BIT(5),
ODM_AD_HOC = BIT(6),
ODM_WIFI_DIRECT = BIT(7),
ODM_WIFI_DISPLAY = BIT(8),
};
/* ODM_CMNINFO_WM_MODE */
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
enum odm_wireless_mode {
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT(0),
ODM_WM_G = BIT(1),
ODM_WM_A = BIT(2),
ODM_WM_N24G = BIT(3),
ODM_WM_N5G = BIT(4),
ODM_WM_AUTO = BIT(5),
ODM_WM_AC = BIT(6),
};
#else
enum odm_wireless_mode {
ODM_WM_UNKNOWN = 0x00,/*0x0*/
ODM_WM_A = BIT(0), /* 0x1*/
ODM_WM_B = BIT(1), /* 0x2*/
ODM_WM_G = BIT(2),/* 0x4*/
ODM_WM_AUTO = BIT(3),/* 0x8*/
ODM_WM_N24G = BIT(4),/* 0x10*/
ODM_WM_N5G = BIT(5),/* 0x20*/
ODM_WM_AC_5G = BIT(6),/* 0x40*/
ODM_WM_AC_24G = BIT(7),/* 0x80*/
ODM_WM_AC_ONLY = BIT(8),/* 0x100*/
ODM_WM_MAX = BIT(11)/* 0x800*/
};
#endif
/* ODM_CMNINFO_BAND */
enum odm_band_type {
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
ODM_BAND_2_4G = BIT(0),
ODM_BAND_5G = BIT(1),
#else
ODM_BAND_2_4G = 0,
ODM_BAND_5G,
ODM_BAND_ON_BOTH,
ODM_BANDMAX
#endif
};
/* ODM_CMNINFO_SEC_CHNL_OFFSET */
enum phydm_sec_chnl_offset {
PHYDM_DONT_CARE = 0,
PHYDM_BELOW = 1,
PHYDM_ABOVE = 2
};
/* ODM_CMNINFO_SEC_MODE */
enum odm_security {
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
ODM_SEC_TKIP = 2,
ODM_SEC_RESERVE = 3,
ODM_SEC_AESCCMP = 4,
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
ODM_SEC_SMS4 = 7,
};
/* ODM_CMNINFO_CHNL */
/* ODM_CMNINFO_BOARD_TYPE */
enum odm_board_type {
ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
};
enum odm_package_type {
ODM_PACKAGE_DEFAULT = 0,
ODM_PACKAGE_QFN68 = BIT(0),
ODM_PACKAGE_TFBGA90 = BIT(1),
ODM_PACKAGE_TFBGA79 = BIT(2),
};
enum odm_type_gpa {
TYPE_GPA0 = 0x0000,
TYPE_GPA1 = 0x0055,
TYPE_GPA2 = 0x00AA,
TYPE_GPA3 = 0x00FF,
TYPE_GPA4 = 0x5500,
TYPE_GPA5 = 0x5555,
TYPE_GPA6 = 0x55AA,
TYPE_GPA7 = 0x55FF,
TYPE_GPA8 = 0xAA00,
TYPE_GPA9 = 0xAA55,
TYPE_GPA10 = 0xAAAA,
TYPE_GPA11 = 0xAAFF,
TYPE_GPA12 = 0xFF00,
TYPE_GPA13 = 0xFF55,
TYPE_GPA14 = 0xFFAA,
TYPE_GPA15 = 0xFFFF,
};
enum odm_type_apa {
TYPE_APA0 = 0x0000,
TYPE_APA1 = 0x0055,
TYPE_APA2 = 0x00AA,
TYPE_APA3 = 0x00FF,
TYPE_APA4 = 0x5500,
TYPE_APA5 = 0x5555,
TYPE_APA6 = 0x55AA,
TYPE_APA7 = 0x55FF,
TYPE_APA8 = 0xAA00,
TYPE_APA9 = 0xAA55,
TYPE_APA10 = 0xAAAA,
TYPE_APA11 = 0xAAFF,
TYPE_APA12 = 0xFF00,
TYPE_APA13 = 0xFF55,
TYPE_APA14 = 0xFFAA,
TYPE_APA15 = 0xFFFF,
};
enum odm_type_glna {
TYPE_GLNA0 = 0x0000,
TYPE_GLNA1 = 0x0055,
TYPE_GLNA2 = 0x00AA,
TYPE_GLNA3 = 0x00FF,
TYPE_GLNA4 = 0x5500,
TYPE_GLNA5 = 0x5555,
TYPE_GLNA6 = 0x55AA,
TYPE_GLNA7 = 0x55FF,
TYPE_GLNA8 = 0xAA00,
TYPE_GLNA9 = 0xAA55,
TYPE_GLNA10 = 0xAAAA,
TYPE_GLNA11 = 0xAAFF,
TYPE_GLNA12 = 0xFF00,
TYPE_GLNA13 = 0xFF55,
TYPE_GLNA14 = 0xFFAA,
TYPE_GLNA15 = 0xFFFF,
};
enum odm_type_alna {
TYPE_ALNA0 = 0x0000,
TYPE_ALNA1 = 0x0055,
TYPE_ALNA2 = 0x00AA,
TYPE_ALNA3 = 0x00FF,
TYPE_ALNA4 = 0x5500,
TYPE_ALNA5 = 0x5555,
TYPE_ALNA6 = 0x55AA,
TYPE_ALNA7 = 0x55FF,
TYPE_ALNA8 = 0xAA00,
TYPE_ALNA9 = 0xAA55,
TYPE_ALNA10 = 0xAAAA,
TYPE_ALNA11 = 0xAAFF,
TYPE_ALNA12 = 0xFF00,
TYPE_ALNA13 = 0xFF55,
TYPE_ALNA14 = 0xFFAA,
TYPE_ALNA15 = 0xFFFF,
};
#define PAUSE_FAIL 0
#define PAUSE_SUCCESS 1
enum odm_parameter_init {
ODM_PRE_SETTING = 0,
ODM_POST_SETTING = 1,
ODM_INIT_FW_SETTING
};
enum phydm_pause_type {
PHYDM_PAUSE = 1, /*Pause & Set new value*/
PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/
PHYDM_RESUME = 3
};
enum phydm_pause_level {
PHYDM_PAUSE_RELEASE = -1,
PHYDM_PAUSE_LEVEL_0 = 0, /* Low Priority function */
PHYDM_PAUSE_LEVEL_1 = 1, /* Middle Priority function */
PHYDM_PAUSE_LEVEL_2 = 2, /* High priority function (ex: Check hang function) */
PHYDM_PAUSE_LEVEL_3 = 3, /* Debug function (the highest priority) */
PHYDM_PAUSE_MAX_NUM = 4
};
enum phydm_dis_hw_fun {
HW_FUN_DIS = 0, /*Disable a cetain HW function & backup the original value*/
HW_FUN_RESUME = 1 /*Revert */
};
#endif

405
hal/phydm/phydm_precomp.h Normal file
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@@ -0,0 +1,405 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "phydm_types.h"
#include "phydm_features.h"
#include "halrf/halrf_features.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" /* We need to include mp_precomp.h due to batch file setting. */
#else
#define TEST_FALG___ 1
#endif
/* 2 Config Flags and Structs - defined by each ODM type */
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../wifi.h"
#include "rtl_phydm.h"
#endif
#define __PACK
#define __WLAN_ATTRIB_PACK__
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "mp_precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#define __PACK
#define __WLAN_ATTRIB_PACK__
#endif
/* 2 OutSrc Header Files */
#include "phydm.h"
#include "phydm_hwconfig.h"
#include "phydm_phystatus.h"
#include "phydm_debug.h"
#include "phydm_regdefine11ac.h"
#include "phydm_regdefine11n.h"
#include "phydm_interface.h"
#include "phydm_reg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211)
void
phy_set_tx_power_limit(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
enum hal_status
rtw_phydm_fw_iqk(
struct dm_struct *dm,
u8 clear,
u8 segment
);
enum hal_status
rtw_phydm_cfg_phy_para(
struct dm_struct *dm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum rf_path e_rf_path,
u32 delay_time
);
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#define RTL8703B_SUPPORT 0
#define RTL8188F_SUPPORT 0
#define RTL8723D_SUPPORT 0
#endif
/* JJ ADD 20161014 */
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP|ODM_IOT))
#define RTL8710B_SUPPORT 0
#endif
#if RTL8188E_SUPPORT == 1
#define RTL8188E_T_SUPPORT 1
#ifdef CONFIG_SFW_SUPPORTED
#define RTL8188E_S_SUPPORT 1
#else
#define RTL8188E_S_SUPPORT 0
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#define RTL8195B_SUPPORT 0 /*Just for PHYDM API development*/
#define RTL8198F_SUPPORT 0 /*Just for PHYDM API development*/
#endif
#if (RTL8188E_SUPPORT == 1)
#include "rtl8188e/hal8188erateadaptive.h" /* for RA,Power training */
#include "rtl8188e/halhwimg8188e_mac.h"
#include "rtl8188e/halhwimg8188e_rf.h"
#include "rtl8188e/halhwimg8188e_bb.h"
#include "rtl8188e/phydm_regconfig8188e.h"
#include "rtl8188e/phydm_rtl8188e.h"
#include "rtl8188e/hal8188ereg.h"
#include "rtl8188e/version_rtl8188e.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188e_hal.h"
#include "halrf/rtl8188e/halrf_8188e_ce.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8188e/halrf_8188e_win.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8188e/halrf_8188e_ap.h"
#endif
#endif /* 88E END */
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8192e/halrf_8192e_win.h" /*FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8192e/halrf_8192e_ap.h" /*FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8192e/halrf_8192e_ce.h" /*FOR_8192E_IQK*/
#endif
#include "rtl8192e/phydm_rtl8192e.h" /* FOR_8192E_IQK */
#include "rtl8192e/version_rtl8192e.h"
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8192e/halhwimg8192e_bb.h"
#include "rtl8192e/halhwimg8192e_mac.h"
#include "rtl8192e/halhwimg8192e_rf.h"
#include "rtl8192e/phydm_regconfig8192e.h"
#include "rtl8192e/hal8192ereg.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8192e_hal.h"
#endif
#endif /* 92E END */
#if (RTL8812A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8812a/halrf_8812a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8812a/halrf_8812a_ap.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8812a/halrf_8812a_ce.h"
#endif
/* #include "halrf/rtl8812a/halrf_8812a.h" */ /* FOR_8812_IQK */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8812a/halhwimg8812a_bb.h"
#include "rtl8812a/halhwimg8812a_mac.h"
#include "rtl8812a/halhwimg8812a_rf.h"
#include "rtl8812a/phydm_regconfig8812a.h"
#include "rtl8812a/phydm_rtl8812a.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8812a_hal.h"
#endif
#include "rtl8812a/version_rtl8812a.h"
#endif /* 8812 END */
#if (RTL8814A_SUPPORT == 1)
#include "rtl8814a/halhwimg8814a_mac.h"
#include "rtl8814a/halhwimg8814a_rf.h"
#include "rtl8814a/halhwimg8814a_bb.h"
#include "rtl8814a/version_rtl8814a.h"
#include "rtl8814a/phydm_rtl8814a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8814a/halrf_8814a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8814a/halrf_8814a_ce.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8814a/halrf_8814a_ap.h"
#endif
#include "rtl8814a/phydm_regconfig8814a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8814a_hal.h"
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#endif /* 8814 END */
#if (RTL8881A_SUPPORT == 1)/* FOR_8881_IQK */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
#else
#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
#endif
/* #include "rtl8881a/HalHWImg8881A_BB.h" */
/* #include "rtl8881a/HalHWImg8881A_MAC.h" */
/* #include "rtl8881a/HalHWImg8881A_RF.h" */
/* #include "rtl8881a/odm_RegConfig8881A.h" */
#endif
#if (RTL8723B_SUPPORT == 1)
#include "rtl8723b/halhwimg8723b_mac.h"
#include "rtl8723b/halhwimg8723b_rf.h"
#include "rtl8723b/halhwimg8723b_bb.h"
#include "rtl8723b/phydm_regconfig8723b.h"
#include "rtl8723b/phydm_rtl8723b.h"
#include "rtl8723b/hal8723breg.h"
#include "rtl8723b/version_rtl8723b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8723b/halrf_8723b_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8723b/halrf_8723b_ce.h"
#include "rtl8723b/halhwimg8723b_mp.h"
#include "rtl8723b_hal.h"
#else
#include "halrf/rtl8723b/halrf_8723b_ap.h"
#endif
#endif
#if (RTL8821A_SUPPORT == 1)
#include "rtl8821a/halhwimg8821a_mac.h"
#include "rtl8821a/halhwimg8821a_rf.h"
#include "rtl8821a/halhwimg8821a_bb.h"
#include "rtl8821a/phydm_regconfig8821a.h"
#include "rtl8821a/phydm_rtl8821a.h"
#include "rtl8821a/version_rtl8821a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8821a/halrf_8821a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8821a/halrf_8821a_ce.h"
#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*for IQK*/
#include "halrf/rtl8812a/halrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/
#include "rtl8812a_hal.h"
#else
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#include "../halmac/halmac_reg2.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "rtl8822b/halhwimg8822b_mac.h"
#include "rtl8822b/halhwimg8822b_rf.h"
#include "rtl8822b/halhwimg8822b_bb.h"
#include "rtl8822b/phydm_regconfig8822b.h"
#include "halrf/rtl8822b/halrf_8822b.h"
#include "rtl8822b/phydm_rtl8822b.h"
#include "rtl8822b/phydm_hal_api8822b.h"
#include "rtl8822b/version_rtl8822b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../halmac/halmac_reg_8822b.h"
#else
#include <hal_data.h> /* struct HAL_DATA_TYPE */
#include <rtl8822b_hal.h> /* RX_SMOOTH_FACTOR, reg definition and etc.*/
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#endif
#endif
#if (RTL8703B_SUPPORT == 1)
#include "rtl8703b/phydm_regconfig8703b.h"
#include "rtl8703b/halhwimg8703b_mac.h"
#include "rtl8703b/halhwimg8703b_rf.h"
#include "rtl8703b/halhwimg8703b_bb.h"
#include "halrf/rtl8703b/halrf_8703b.h"
#include "rtl8703b/version_rtl8703b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8703b_hal.h"
#endif
#endif
#if (RTL8188F_SUPPORT == 1)
#include "rtl8188f/halhwimg8188f_mac.h"
#include "rtl8188f/halhwimg8188f_rf.h"
#include "rtl8188f/halhwimg8188f_bb.h"
#include "rtl8188f/hal8188freg.h"
#include "rtl8188f/phydm_rtl8188f.h"
#include "rtl8188f/phydm_regconfig8188f.h"
#include "halrf/rtl8188f/halrf_8188f.h" /* for IQK,LCK,Power-tracking */
#include "rtl8188f/version_rtl8188f.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188f_hal.h"
#endif
#endif
#if (RTL8723D_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8723d/halhwimg8723d_bb.h"
#include "rtl8723d/halhwimg8723d_mac.h"
#include "rtl8723d/halhwimg8723d_rf.h"
#include "rtl8723d/phydm_regconfig8723d.h"
#include "rtl8723d/hal8723dreg.h"
#include "rtl8723d/phydm_rtl8723d.h"
#include "halrf/rtl8723d/halrf_8723d.h"
#include "rtl8723d/version_rtl8723d.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8723d_hal.h"
#endif
#endif /* 8723D End */
/* JJ ADD 20161014 */
#if (RTL8710B_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8710b/halhwimg8710b_bb.h"
#include "rtl8710b/halhwimg8710b_mac.h"
#include "rtl8710b/halhwimg8710b_rf.h"
#include "rtl8710b/phydm_regconfig8710b.h"
#include "rtl8710b/hal8710breg.h"
#include "rtl8710b/phydm_rtl8710b.h"
#include "halrf/rtl8710b/halrf_8710b.h"
#include "rtl8710b/version_rtl8710b.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8710b_hal.h"
#endif
#endif /* 8710B End */
#if (RTL8197F_SUPPORT == 1)
#include "rtl8197f/halhwimg8197f_mac.h"
#include "rtl8197f/halhwimg8197f_rf.h"
#include "rtl8197f/halhwimg8197f_bb.h"
#include "rtl8197f/phydm_hal_api8197f.h"
#include "rtl8197f/version_rtl8197f.h"
#include "rtl8197f/phydm_rtl8197f.h"
#include "rtl8197f/phydm_regconfig8197f.h"
#include "halrf/rtl8197f/halrf_8197f.h"
#include "halrf/rtl8197f/halrf_iqk_8197f.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "rtl8821c/phydm_hal_api8821c.h"
#include "rtl8821c/halhwimg8821c_mac.h"
#include "rtl8821c/halhwimg8821c_rf.h"
#include "rtl8821c/halhwimg8821c_bb.h"
#include "rtl8821c/phydm_regconfig8821c.h"
#include "halrf/rtl8821c/halrf_8821c.h"
#include "rtl8821c/version_rtl8821c.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8821c_hal.h"
#endif
#endif
#if (RTL8195B_SUPPORT == 1)
#include "rtl8195b/phydm_hal_api8195b.h"
#endif
#if (RTL8198F_SUPPORT == 1)
#include "rtl8198f/phydm_hal_api8198F.h"
#endif
#endif /* __ODM_PRECOMP_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_PRIMARY_CCA
void
phydm_write_dynamic_cca(
void *dm_void,
u8 curr_mf_state
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca;
if (primary_cca->mf_state == curr_mf_state)
return;
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (curr_mf_state == MF_USC_LSC) {
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), MF_USC_LSC);
odm_set_bb_reg(dm, 0xc84, 0xf0000000, primary_cca->cca_th_40m_bkp); /*40M OFDM MF CCA threshold*/
} else {
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), curr_mf_state);
odm_set_bb_reg(dm, 0xc84, 0xf0000000, 0); /*40M OFDM MF CCA threshold*/
}
}
primary_cca->mf_state = curr_mf_state;
PHYDM_DBG(dm, DBG_PRI_CCA,
"Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", ((curr_mf_state == MF_USC_LSC)?"D":((curr_mf_state == MF_LSC)?"L":"U")), curr_mf_state);
}
void
phydm_primary_cca_reset(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca;
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
primary_cca->mf_state = 0xff;
primary_cca->pre_bw = (enum channel_width)0xff;
phydm_write_dynamic_cca(dm, MF_USC_LSC);
}
void
phydm_primary_cca_11n(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca;
enum channel_width curr_bw = (enum channel_width)*dm->band_width;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
if (!dm->is_linked) { /* is_linked==False */
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
if (primary_cca->pri_cca_is_become_linked == true) {
phydm_primary_cca_reset(dm);
primary_cca->pri_cca_is_become_linked = dm->is_linked;
}
return;
} else {
if (primary_cca->pri_cca_is_become_linked == false) {
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
primary_cca->pri_cca_is_become_linked = dm->is_linked;
}
}
if (curr_bw != primary_cca->pre_bw) {
PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
primary_cca->pre_bw = curr_bw;
if (curr_bw == CHANNEL_WIDTH_40) {
if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {/* Primary CH @ upper sideband*/
PHYDM_DBG(dm, DBG_PRI_CCA, "BW40M, Primary CH at USB\n");
phydm_write_dynamic_cca(dm, MF_USC);
} else { /*Primary CH @ lower sideband*/
PHYDM_DBG(dm, DBG_PRI_CCA, "BW40M, Primary CH at LSB\n");
phydm_write_dynamic_cca(dm, MF_LSC);
}
} else {
PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
phydm_primary_cca_reset(dm);
}
}
}
#if 0
#if (RTL8188E_SUPPORT == 1)
void
odm_dynamic_primary_cca_8188e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sta_info *entry;
struct cmn_sta_info *sta;
struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca);
boolean client_40mhz = false, client_tmp = false; /* connected client BW */
boolean is_connected = false; /* connected or not */
u8 client_40mhz_pre = 0;
u32 counter = 0;
u8 delay = 1;
u64 cur_tx_ok_cnt;
u64 cur_rx_ok_cnt;
u8 sec_ch_offset = *(dm->sec_ch_offset);
u8 i;
if (!dm->is_linked)
return;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
if (*(dm->band_width) == CHANNEL_WIDTH_20) { /*curr bw*/
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0);
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE)
sec_ch_offset = sec_ch_offset % 2 + 1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */
#endif
PHYDM_DBG(dm, DBG_PRI_CCA, "Second CH Offset = %d\n", sec_ch_offset);
/* 3 Check Current WLAN Traffic */
cur_tx_ok_cnt = dm->tx_tp;
cur_rx_ok_cnt = dm->rx_tp;
/* ==================Debug Message==================== */
PHYDM_DBG(dm, DBG_PRI_CCA, "TP = %llu\n", cur_tx_ok_cnt + cur_rx_ok_cnt);
PHYDM_DBG(dm, DBG_PRI_CCA, "is_BW40 = %d\n", *(dm->band_width));
PHYDM_DBG(dm, DBG_PRI_CCA, "BW_LSC = %d\n", false_alm_cnt->cnt_bw_lsc);
PHYDM_DBG(dm, DBG_PRI_CCA, "BW_USC = %d\n", false_alm_cnt->cnt_bw_usc);
PHYDM_DBG(dm, DBG_PRI_CCA, "CCA OFDM = %d\n", false_alm_cnt->cnt_ofdm_cca);
PHYDM_DBG(dm, DBG_PRI_CCA, "CCA CCK = %d\n", false_alm_cnt->cnt_cck_cca);
PHYDM_DBG(dm, DBG_PRI_CCA, "OFDM FA = %d\n", false_alm_cnt->cnt_ofdm_fail);
PHYDM_DBG(dm, DBG_PRI_CCA, "CCK FA = %d\n", false_alm_cnt->cnt_cck_fail);
/* ================================================ */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (ACTING_AS_AP(dm->adapter)) /* primary cca process only do at AP mode */
#endif
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHYDM_DBG(dm, DBG_PRI_CCA, "ACTING as AP mode=%d\n", ACTING_AS_AP(dm->adapter));
/* 3 To get entry's connection and BW infomation status. */
for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
if (IsAPModeExist(dm->adapter) && GetFirstExtAdapter(dm->adapter) != NULL)
entry = AsocEntry_EnumStation(GetFirstExtAdapter(dm->adapter), i);
else
entry = AsocEntry_EnumStation(GetDefaultAdapter(dm->adapter), i);
if (entry != NULL) {
client_tmp = entry->BandWidth; /* client BW */
PHYDM_DBG(dm, DBG_PRI_CCA, "Client_BW=%d\n", client_tmp);
if (client_tmp > client_40mhz)
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
if (entry->bAssociated) {
is_connected = true; /* client is connected or not */
break;
}
} else
break;
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
/* 3 To get entry's connection and BW infomation status. */
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (is_sta_active(sta)) {
client_tmp = sta->bw_mode;
if (client_tmp > client_40mhz)
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
is_connected = true;
}
}
#endif
PHYDM_DBG(dm, DBG_PRI_CCA, "is_connected=%d\n", is_connected);
PHYDM_DBG(dm, DBG_PRI_CCA, "Is Client 40MHz=%d\n", client_40mhz);
/* 1 Monitor whether the interference exists or not */
if (primary_cca->monitor_flag == 1) {
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_lsc > false_alm_cnt->cnt_bw_usc + 500)) {
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
primary_cca->intf_type = 1;
primary_cca->pri_cca_flag = 1;
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT7, 2); /* USC MF */
if (primary_cca->dup_rts_flag == 1)
primary_cca->dup_rts_flag = 0;
} else {
primary_cca->intf_type = 2;
if (primary_cca->dup_rts_flag == 0)
primary_cca->dup_rts_flag = 1;
}
} else { /* interferecne disappear */
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_usc > false_alm_cnt->cnt_bw_lsc + 500)) {
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
primary_cca->intf_type = 1;
primary_cca->pri_cca_flag = 1;
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT7, 1); /* LSC MF */
if (primary_cca->dup_rts_flag == 1)
primary_cca->dup_rts_flag = 0;
} else {
primary_cca->intf_type = 2;
if (primary_cca->dup_rts_flag == 0)
primary_cca->dup_rts_flag = 1;
}
} else { /* interferecne disappear */
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
}
primary_cca->monitor_flag = 0;
}
/* 1 Dynamic Primary CCA Main Function */
if (primary_cca->monitor_flag == 0) {
if (*(dm->band_width) == CHANNEL_WIDTH_40) { /* if RFBW==40M mode which require to process primary cca */
/* 2 STA is NOT Connected */
if (!is_connected) {
PHYDM_DBG(dm, DBG_PRI_CCA, "STA NOT Connected!!!!\n");
if (primary_cca->pri_cca_flag == 1) { /* reset primary cca when STA is disconnected */
primary_cca->pri_cca_flag = 0;
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0);
}
if (primary_cca->dup_rts_flag == 1) /* reset Duplicate RTS when STA is disconnected */
primary_cca->dup_rts_flag = 0;
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
} else {
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
} else {
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
}
PHYDM_DBG(dm, DBG_PRI_CCA, "primary_cca=%d\n", primary_cca->pri_cca_flag);
PHYDM_DBG(dm, DBG_PRI_CCA, "Intf_Type=%d\n", primary_cca->intf_type);
}
/* 2 STA is Connected */
else {
if (client_40mhz == 0) /* 3 */ { /* client BW = 20MHz */
if (primary_cca->pri_cca_flag == 0) {
primary_cca->pri_cca_flag = 1;
if (sec_ch_offset == 1)
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 2);
else if (sec_ch_offset == 2)
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 1);
}
PHYDM_DBG(dm, DBG_PRI_CCA, "STA Connected 20M!!! primary_cca=%d\n", primary_cca->pri_cca_flag);
} else /* 3 */ { /* client BW = 40MHz */
if (primary_cca->intf_flag == 1) { /* interference is detected!! */
if (primary_cca->intf_type == 1) {
if (primary_cca->pri_cca_flag != 1) {
primary_cca->pri_cca_flag = 1;
if (sec_ch_offset == 1)
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 2);
else if (sec_ch_offset == 2)
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 1);
}
} else if (primary_cca->intf_type == 2) {
if (primary_cca->dup_rts_flag != 1)
primary_cca->dup_rts_flag = 1;
}
} else { /* if intf_flag==0 */
if ((cur_tx_ok_cnt + cur_rx_ok_cnt) < 1) { /* idle mode or TP traffic is very low */
if (sec_ch_offset == 1) {
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
}
} else if (sec_ch_offset == 2) {
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
}
}
} else { /* TP Traffic is High */
if (sec_ch_offset == 1) {
if (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + 500)) {
if (delay == 0) { /* add delay to avoid interference occurring abruptly, jump one time */
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
delay = 1;
} else
delay = 0;
}
} else if (sec_ch_offset == 2) {
if (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + 500)) {
if (delay == 0) { /* add delay to avoid interference occurring abruptly */
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
delay = 1;
} else
delay = 0;
}
}
}
}
PHYDM_DBG(dm, DBG_PRI_CCA, "Primary CCA=%d\n", primary_cca->pri_cca_flag);
PHYDM_DBG(dm, DBG_PRI_CCA, "Duplicate RTS=%d\n", primary_cca->dup_rts_flag);
}
} /* end of connected */
}
}
/* 1 Dynamic Primary CCA Monitor counter */
if ((primary_cca->pri_cca_flag == 1) || (primary_cca->dup_rts_flag == 1)) {
if (client_40mhz == 0) { /* client=20M no need to monitor primary cca flag */
client_40mhz_pre = client_40mhz;
return;
}
counter++;
PHYDM_DBG(dm, DBG_PRI_CCA, "counter=%d\n", counter);
if ((counter == 30) || ((client_40mhz - client_40mhz_pre) == 1)) { /* Every 60 sec to monitor one time */
primary_cca->monitor_flag = 1; /* monitor flag is triggered!!!!! */
if (primary_cca->pri_cca_flag == 1) {
primary_cca->pri_cca_flag = 0;
odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0);
}
counter = 0;
}
}
}
client_40mhz_pre = client_40mhz;
}
#endif
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_dynamic_primary_cca_mp_8192e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
PADAPTER adapter = (PADAPTER)dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct phydm_fa_struct *false_alm_cnt = &(dm->false_alm_cnt);
struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca);
u64 OFDM_CCA, OFDM_FA, bw_usc_cnt, bw_lsc_cnt;
u8 sec_ch_offset;
static u8 count_down = PRI_CCA_MONITOR_TIME;
if (!dm->is_linked)
return;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
OFDM_CCA = false_alm_cnt->cnt_ofdm_cca;
OFDM_FA = false_alm_cnt->cnt_ofdm_fail;
bw_usc_cnt = false_alm_cnt->cnt_bw_usc;
bw_lsc_cnt = false_alm_cnt->cnt_bw_lsc;
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: OFDM CCA=%d\n", OFDM_CCA);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: OFDM FA=%d\n", OFDM_FA);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: BW_USC=%d\n", bw_usc_cnt);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: BW_LSC=%d\n", bw_lsc_cnt);
sec_ch_offset = *(dm->sec_ch_offset); /* NIC: 2: sec is below, 1: sec is above */
if (IsAPModeExist(adapter)) {
phydm_write_dynamic_cca(dm, MF_USC_LSC);
return;
}
if (*(dm->band_width) != CHANNEL_WIDTH_40)
return;
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Cont Down= %d\n", count_down);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Primary_CCA_flag=%d\n", primary_cca->pri_cca_flag);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Intf_Type=%d\n", primary_cca->intf_type);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Intf_flag=%d\n", primary_cca->intf_flag);
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Duplicate RTS Flag=%d\n", primary_cca->dup_rts_flag);
if (primary_cca->pri_cca_flag == 0) {
if (sec_ch_offset == SECOND_CH_AT_LSB) { /* Primary channel is above NOTE: duplicate CTS can remove this condition */
if ((OFDM_CCA > OFDMCCA_TH) && (bw_lsc_cnt > (bw_usc_cnt + bw_ind_bias))
&& (OFDM_FA > (OFDM_CCA >> 1))) {
primary_cca->intf_type = 1;
primary_cca->intf_flag = 1;
phydm_write_dynamic_cca(dm, MF_USC);
primary_cca->pri_cca_flag = 1;
} else if ((OFDM_CCA > OFDMCCA_TH) && (bw_lsc_cnt > (bw_usc_cnt + bw_ind_bias))
&& (OFDM_FA < (OFDM_CCA >> 1))) {
primary_cca->intf_type = 2;
primary_cca->intf_flag = 1;
phydm_write_dynamic_cca(dm, MF_USC);
primary_cca->pri_cca_flag = 1;
primary_cca->dup_rts_flag = 1;
hal_data->RTSEN = 1;
} else {
primary_cca->intf_type = 0;
primary_cca->intf_flag = 0;
phydm_write_dynamic_cca(dm, MF_USC_LSC);
hal_data->RTSEN = 0;
primary_cca->dup_rts_flag = 0;
}
} else if (sec_ch_offset == SECOND_CH_AT_USB) {
if ((OFDM_CCA > OFDMCCA_TH) && (bw_usc_cnt > (bw_lsc_cnt + bw_ind_bias))
&& (OFDM_FA > (OFDM_CCA >> 1))) {
primary_cca->intf_type = 1;
primary_cca->intf_flag = 1;
phydm_write_dynamic_cca(dm, MF_LSC);
primary_cca->pri_cca_flag = 1;
} else if ((OFDM_CCA > OFDMCCA_TH) && (bw_usc_cnt > (bw_lsc_cnt + bw_ind_bias))
&& (OFDM_FA < (OFDM_CCA >> 1))) {
primary_cca->intf_type = 2;
primary_cca->intf_flag = 1;
phydm_write_dynamic_cca(dm, MF_LSC);
primary_cca->pri_cca_flag = 1;
primary_cca->dup_rts_flag = 1;
hal_data->RTSEN = 1;
} else {
primary_cca->intf_type = 0;
primary_cca->intf_flag = 0;
phydm_write_dynamic_cca(dm, MF_USC_LSC);
hal_data->RTSEN = 0;
primary_cca->dup_rts_flag = 0;
}
}
} else { /* primary_cca->pri_cca_flag==1 */
count_down--;
if (count_down == 0) {
count_down = PRI_CCA_MONITOR_TIME;
primary_cca->pri_cca_flag = 0;
phydm_write_dynamic_cca(dm, MF_USC_LSC); /* default */
hal_data->RTSEN = 0;
primary_cca->dup_rts_flag = 0;
primary_cca->intf_type = 0;
primary_cca->intf_flag = 0;
}
}
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
void
odm_intf_detection(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fa_struct *false_alm_cnt = &(dm->false_alm_cnt);
struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca);
if ((false_alm_cnt->cnt_ofdm_cca > OFDMCCA_TH)
&& (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + bw_ind_bias))) {
primary_cca->intf_flag = 1;
primary_cca->ch_offset = 1; /* 1:LSC, 2:USC */
if (false_alm_cnt->cnt_ofdm_fail > (false_alm_cnt->cnt_ofdm_cca >> 1))
primary_cca->intf_type = 1;
else
primary_cca->intf_type = 2;
} else if ((false_alm_cnt->cnt_ofdm_cca > OFDMCCA_TH)
&& (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + bw_ind_bias))) {
primary_cca->intf_flag = 1;
primary_cca->ch_offset = 2; /* 1:LSC, 2:USC */
if (false_alm_cnt->cnt_ofdm_fail > (false_alm_cnt->cnt_ofdm_cca >> 1))
primary_cca->intf_type = 1;
else
primary_cca->intf_type = 2;
} else {
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
primary_cca->ch_offset = 0;
}
}
void
odm_dynamic_primary_cca_ap_8192e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca);
u8 i;
static u32 count_down = PRI_CCA_MONITOR_TIME;
u8 STA_BW = false, STA_BW_pre = false, STA_BW_TMP = false;
boolean is_connected = false;
u8 sec_ch_offset;
u8 cur_mf_state;
struct cmn_sta_info *entry;
if (!dm->is_linked)
return;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
sec_ch_offset = *(dm->sec_ch_offset); /* AP: 1: sec is below, 2: sec is above */
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
entry = dm->phydm_sta_info[i];
if (is_sta_active(entry)) {
STA_BW_TMP = entry->bw_mode;
if (STA_BW_TMP > STA_BW)
STA_BW = STA_BW_TMP;
is_connected = true;
}
}
if (*(dm->band_width) == CHANNEL_WIDTH_40) {
if (primary_cca->pri_cca_flag == 0) {
if (is_connected) {
if (STA_BW == CHANNEL_WIDTH_20) { /* 2 STA BW=20M */
primary_cca->pri_cca_flag = 1;
if (sec_ch_offset == 1) {
cur_mf_state = MF_USC;
phydm_write_dynamic_cca(dm, cur_mf_state);
} else if (sec_ch_offset == 2) {
cur_mf_state = MF_USC;
phydm_write_dynamic_cca(dm, cur_mf_state);
}
} else { /* 2 STA BW=40M */
if (primary_cca->intf_flag == 0)
odm_intf_detection(dm);
else { /* intf_flag = 1 */
if (primary_cca->intf_type == 1) {
if (primary_cca->ch_offset == 1) {
cur_mf_state = MF_USC;
if (sec_ch_offset == 1) /* AP, 1: primary is above 2: primary is below */
phydm_write_dynamic_cca(dm, cur_mf_state);
} else if (primary_cca->ch_offset == 2) {
cur_mf_state = MF_LSC;
if (sec_ch_offset == 2)
phydm_write_dynamic_cca(dm, cur_mf_state);
}
} else if (primary_cca->intf_type == 2)
PHYDM_DBG(dm, DBG_PRI_CCA, "92E: primary_cca->intf_type = 2\n");
}
}
} else /* disconnected interference detection */
odm_intf_detection(dm); /* end of disconnected */
} else { /* primary_cca->pri_cca_flag == 1 */
if (STA_BW == 0) {
STA_BW_pre = STA_BW;
return;
}
count_down--;
if ((count_down == 0) || ((STA_BW & STA_BW_pre) != 1)) {
count_down = PRI_CCA_MONITOR_TIME;
primary_cca->pri_cca_flag = 0;
primary_cca->intf_type = 0;
primary_cca->intf_flag = 0;
cur_mf_state = MF_USC_LSC;
phydm_write_dynamic_cca(dm, cur_mf_state); /* default */
}
}
STA_BW_pre = STA_BW;
} else {
/* 2 Reset */
phydm_primary_cca_init(dm);
cur_mf_state = MF_USC_LSC;
phydm_write_dynamic_cca(dm, cur_mf_state);
count_down = PRI_CCA_MONITOR_TIME;
}
}
#endif
#endif /* RTL8192E_SUPPORT == 1 */
#endif
#endif
boolean
odm_dynamic_primary_cca_dup_rts(
void *dm_void
)
{
#ifdef PHYDM_PRIMARY_CCA
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca;
return primary_cca->dup_rts_flag;
#else
return 0;
#endif
}
void
phydm_primary_cca_init(
void *dm_void
)
{
#ifdef PHYDM_PRIMARY_CCA
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
primary_cca->monitor_flag = 0;
primary_cca->pri_cca_flag = 0;
primary_cca->ch_offset = 0;
#endif
primary_cca->mf_state = 0xff;
primary_cca->pre_bw = (enum channel_width)0xff;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
primary_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, 0xc84, 0xf0000000);
#endif
}
void
phydm_primary_cca(
void *dm_void
)
{
#ifdef PHYDM_PRIMARY_CCA
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
return;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
phydm_primary_cca_11n(dm);
#endif
}

126
hal/phydm/phydm_primary_cca.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_PRIMARYCCA_H__
#define __PHYDM_PRIMARYCCA_H__
#define PRIMARYCCA_VERSION "1.0" /*2017.03.23, Dino*/
/*============================================================*/
/*Definition */
/*============================================================*/
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define SECOND_CH_AT_LSB 2 /*primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
#define SECOND_CH_AT_USB 1 /*primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define SECOND_CH_AT_LSB 2 /*primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
#define SECOND_CH_AT_USB 1 /*primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
#define SECOND_CH_AT_LSB 1 /*primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/
#define SECOND_CH_AT_USB 2 /*primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/
#endif
#define OFDMCCA_TH 500
#define bw_ind_bias 500
#define PRI_CCA_MONITOR_TIME 30
#ifdef PHYDM_PRIMARY_CCA
/*============================================================*/
/*structure and define*/
/*============================================================*/
enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
MF_USC_LSC = 0,
MF_LSC = 1,
MF_USC = 2
};
struct phydm_pricca_struct {
#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
u8 pri_cca_flag;
u8 intf_flag;
u8 intf_type;
u8 monitor_flag;
u8 ch_offset;
#endif
u8 dup_rts_flag;
u8 cca_th_40m_bkp; /*c84[31:28]*/
enum channel_width pre_bw;
u8 pri_cca_is_become_linked;
u8 mf_state;
};
/*============================================================*/
/*function prototype*/
/*============================================================*/
#if 0
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_dynamic_primary_cca_mp_8192e(
void *dm_void
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
void
odm_dynamic_primary_cca_ap_8192e(
void *dm_void
);
#endif
#endif
#if (RTL8188E_SUPPORT == 1)
void
odm_dynamic_primary_cca_8188e(
void *dm_void
);
#endif
#endif
#endif /*#ifdef PHYDM_PRIMARY_CCA*/
boolean
odm_dynamic_primary_cca_dup_rts(
void *dm_void
);
void
phydm_primary_cca_init(
void *dm_void
);
void
phydm_primary_cca(
void *dm_void
);
#endif /*#ifndef __PHYDM_PRIMARYCCA_H__*/

402
hal/phydm/phydm_psd.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
//============================================================
// include files
//============================================================
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_PSD_TOOL
u32
phydm_get_psd_data(
void *dm_void,
u32 psd_tone_idx,
u32 igi
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u32 psd_report = 0;
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/
ODM_delay_us(10);
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, 0xffff);
psd_report = odm_convert_to_db(psd_report) + igi;
return psd_report;
}
u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127};
u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67};
void
phydm_psd(
void *dm_void,
u32 igi,
u16 start_point,
u16 stop_point
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u32 i = 0, mod_tone_idx;
u32 t = 0;
u16 fft_max_half_bw;
u32 psd_igi_a_reg;
u32 psd_igi_b_reg;
u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
u8 ag_rf_mode_reg = 0;
u8 rf_reg18_9_8 = 0;
u32 psd_result_tmp = 0;
u8 psd_result = 0;
u8 psd_result_cali_tone[7] = {0};
u8 psd_result_cali_val[7] = {0};
u8 noise_table_idx = 0;
u8 set_result;
if (dm->support_ic_type == ODM_RTL8821) {
odm_move_memory(dm, psd_result_cali_tone, psd_result_cali_tone_8821, 7);
odm_move_memory(dm, psd_result_cali_val, psd_result_cali_val_8821, 7);
}
dm_psd_table->psd_in_progress = 1;
/*[Stop DIG]*/
dm->support_ability &= ~(ODM_BB_DIG);
dm->support_ability &= ~(ODM_BB_FA_CNT);
PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
psd_igi_a_reg = 0xc50;
psd_igi_b_reg = 0xe50;
} else {
psd_igi_a_reg = 0xc50;
psd_igi_b_reg = 0xc58;
}
/*[back up IGI]*/
dm_psd_table->initial_gain_backup = odm_get_bb_reg(dm, psd_igi_a_reg, 0xff);
odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/
odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/
ODM_delay_us(10);
if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
return;
}
/*[Set IGI]*/
odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi);
odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi);
/*[Backup RF Reg]*/
dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK);
if (psd_fc_channel > 14) {
rf_reg18_9_8 = 1;
if (36 <= psd_fc_channel && psd_fc_channel <= 64)
ag_rf_mode_reg = 0x1;
else if (100 <= psd_fc_channel && psd_fc_channel <= 140)
ag_rf_mode_reg = 0x3;
else if (140 < psd_fc_channel)
ag_rf_mode_reg = 0x5;
}
/* RF path-a */
odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/
odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0x300, rf_reg18_9_8);
odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xc00, dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/
/* RF path-b */
odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/
odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0x300, rf_reg18_9_8);
odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xc00, dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/
PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n", odm_get_bb_reg(dm, 0xc50, MASKDWORD));
/*PHYDM_DBG(dm, ODM_COMP_API, "RF0x0=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK));*/
PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK));
/*[Stop 3-wires]*/
phydm_stop_3_wire(dm, PHYDM_SET);
ODM_delay_us(10);
if (stop_point > (dm_psd_table->fft_smp_point-1))
stop_point = (dm_psd_table->fft_smp_point-1);
if (start_point > (dm_psd_table->fft_smp_point-1))
start_point = (dm_psd_table->fft_smp_point-1);
if (start_point > stop_point)
stop_point = start_point;
for (i = start_point; i <= stop_point; i++ ) {
fft_max_half_bw = (dm_psd_table->fft_smp_point)>>1;
if (i < fft_max_half_bw) {
mod_tone_idx = i + fft_max_half_bw;
} else {
mod_tone_idx = i - fft_max_half_bw;
}
psd_result_tmp = 0;
for (t = 0; t < dm_psd_table->sw_avg_time; t++) {
psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx, igi);
/**/
}
psd_result = (u8)((psd_result_tmp/dm_psd_table->sw_avg_time)) - dm_psd_table->psd_pwr_common_offset;
if( dm_psd_table->fft_smp_point == 128 && (dm_psd_table->noise_k_en)) {
if (i > psd_result_cali_tone[noise_table_idx]) {
noise_table_idx ++;
}
if (noise_table_idx > 6)
noise_table_idx = 6;
if (psd_result >= psd_result_cali_val[noise_table_idx])
psd_result = psd_result - psd_result_cali_val[noise_table_idx];
else
psd_result = 0;
dm_psd_table->psd_result[i] = psd_result;
}
PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result);
}
/*[Start 3-wires]*/
phydm_stop_3_wire(dm, PHYDM_REVERT);
ODM_delay_us(10);
/*[Revert Reg]*/
set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, dm_psd_table->initial_gain_backup);
odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, dm_psd_table->initial_gain_backup);
odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, dm_psd_table->rf_0x18_bkp);
odm_set_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK, dm_psd_table->rf_0x18_bkp_b);
PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
dm->support_ability |= ODM_BB_DIG;
dm->support_ability |= ODM_BB_FA_CNT;
dm_psd_table->psd_in_progress = 0;
}
void
phydm_psd_para_setting(
void *dm_void,
u8 sw_avg_time,
u8 hw_avg_time,
u8 i_q_setting,
u16 fft_smp_point,
u8 ant_sel,
u8 psd_input,
u8 channel,
u8 noise_k_en
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u8 fft_smp_point_idx = 0;
dm_psd_table->fft_smp_point = fft_smp_point;
if (sw_avg_time == 0)
sw_avg_time = 1;
dm_psd_table->sw_avg_time = sw_avg_time;
dm_psd_table->psd_fc_channel = channel;
dm_psd_table->noise_k_en = noise_k_en;
if (fft_smp_point == 128)
fft_smp_point_idx = 0;
else if (fft_smp_point == 256)
fft_smp_point_idx = 1;
else if (fft_smp_point == 512)
fft_smp_point_idx = 2;
else if (fft_smp_point == 1024)
fft_smp_point_idx = 3;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, 0x910, BIT(11) | BIT(10), i_q_setting);
odm_set_bb_reg(dm, 0x910, BIT(13) | BIT(12), hw_avg_time);
odm_set_bb_reg(dm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx);
odm_set_bb_reg(dm, 0x910, BIT(17) | BIT(16), ant_sel);
odm_set_bb_reg(dm, 0x910, BIT(23), psd_input);
#if 0
} else { /*ODM_IC_11N_SERIES*/
#endif
}
/*bw = (*dm->band_width); //ODM_BW20M */
/*channel = *(dm->channel);*/
}
void
phydm_psd_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
dm_psd_table->psd_in_progress = false;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
dm_psd_table->psd_reg = 0x910;
dm_psd_table->psd_report_reg = 0xF44;
if (ODM_IC_11AC_2_SERIES)
dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
else
dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
} else {
dm_psd_table->psd_reg = 0x808;
dm_psd_table->psd_report_reg = 0x8B4;
dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
}
if (dm->support_ic_type == ODM_RTL8812)
dm_psd_table->psd_pwr_common_offset = 0;
else if (dm->support_ic_type == ODM_RTL8821)
dm_psd_table->psd_pwr_common_offset = 0;
else
dm_psd_table->psd_pwr_common_offset = 0;
phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
}
void
phydm_psd_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{1} {IGI(hex)} {start_point} {stop_point}\n");
goto out;
}
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if (var1[0] == 0) {
for (i = 1; i < 10; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
}
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8]);
phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]);
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
PDM_SNPF(out_len, used, output + used, out_len - used,
"IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
var1[1], var1[2], var1[3]);
dm->debug_components |= ODM_COMP_API;
phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]);
dm->debug_components &= (~ODM_COMP_API);
}
out:
*_used = used;
*_out_len = out_len;
}
u8
phydm_get_psd_result_table(
void *dm_void,
int index
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u8 temp_result = 0;
if(index<128)
temp_result = dm_psd_table->psd_result[index];
return temp_result;
}
#endif

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hal/phydm/phydm_psd.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPSD_H__
#define __PHYDMPSD_H__
/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/
#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */
#ifdef CONFIG_PSD_TOOL
struct psd_info {
u8 psd_in_progress;
u32 psd_reg;
u32 psd_report_reg;
u8 psd_pwr_common_offset;
u16 sw_avg_time;
u16 fft_smp_point;
u32 initial_gain_backup;
u32 rf_0x18_bkp;
u32 rf_0x18_bkp_b;
u16 psd_fc_channel;
u32 psd_bw_rf_reg;
u8 psd_result[128];
u8 noise_k_en;
};
u32
phydm_get_psd_data(
void *dm_void,
u32 psd_tone_idx,
u32 igi
);
void
phydm_psd_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void
phydm_psd(
void *dm_void,
u32 igi,
u16 start_point,
u16 stop_point
);
void
phydm_psd_para_setting(
void *dm_void,
u8 sw_avg_time,
u8 hw_avg_time,
u8 i_q_setting,
u16 fft_smp_point,
u8 ant_sel,
u8 psd_input,
u8 channel,
u8 noise_k_en
);
void
phydm_psd_init(
void *dm_void
);
u8
phydm_get_psd_result_table(
void *dm_void,
int index
);
#endif
#endif

2441
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453
hal/phydm/phydm_rainfo.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
/*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/
/*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/
/*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/
/*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/
/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
/*#define RAINFO_VERSION "4.3"*/ /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */
#define RAINFO_VERSION "5.0" /*2017.04.20 Dino, the 3rd PHYDM reform*/
#define FORCED_UPDATE_RAMASK_PERIOD 5
#define H2C_MAX_LENGTH 7
#define RA_FLOOR_UP_GAP 3
#define RA_FLOOR_TABLE_SIZE 7
#define ACTIVE_TP_THRESHOLD 1
#define RA_RETRY_DESCEND_NUM 2
#define RA_RETRY_LIMIT_LOW 4
#define RA_RETRY_LIMIT_HIGH 32
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define RA_FIRST_MACID 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RA_FIRST_MACID 0
#define WIN_DEFAULT_PORT_MACID 0
#define WIN_BT_PORT_MACID 2
#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
#define RA_FIRST_MACID 0
#endif
enum phydm_ra_dbg_para {
RADBG_PCR_TH_OFFSET = 0,
RADBG_RTY_PENALTY = 1,
RADBG_N_HIGH = 2,
RADBG_N_LOW = 3,
RADBG_TRATE_UP_TABLE = 4,
RADBG_TRATE_DOWN_TABLE = 5,
RADBG_TRYING_NECESSARY = 6,
RADBG_TDROPING_NECESSARY = 7,
RADBG_RATE_UP_RTY_RATIO = 8,
RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
RADBG_DEBUG_MONITOR1 = 0xc,
RADBG_DEBUG_MONITOR2 = 0xd,
RADBG_DEBUG_MONITOR3 = 0xe,
RADBG_DEBUG_MONITOR4 = 0xf,
RADBG_DEBUG_MONITOR5 = 0x10,
NUM_RA_PARA
};
enum phydm_wireless_mode {
PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
PHYDM_WIRELESS_MODE_A = 0x01,
PHYDM_WIRELESS_MODE_B = 0x02,
PHYDM_WIRELESS_MODE_G = 0x04,
PHYDM_WIRELESS_MODE_AUTO = 0x08,
PHYDM_WIRELESS_MODE_N_24G = 0x10,
PHYDM_WIRELESS_MODE_N_5G = 0x20,
PHYDM_WIRELESS_MODE_AC_5G = 0x40,
PHYDM_WIRELESS_MODE_AC_24G = 0x80,
PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
PHYDM_WIRELESS_MODE_MAX = 0x800,
PHYDM_WIRELESS_MODE_ALL = 0xFFFF
};
enum phydm_rateid_idx {
PHYDM_BGN_40M_2SS = 0,
PHYDM_BGN_40M_1SS = 1,
PHYDM_BGN_20M_2SS = 2,
PHYDM_BGN_20M_1SS = 3,
PHYDM_GN_N2SS = 4,
PHYDM_GN_N1SS = 5,
PHYDM_BG = 6,
PHYDM_G = 7,
PHYDM_B_20M = 8,
PHYDM_ARFR0_AC_2SS = 9,
PHYDM_ARFR1_AC_1SS = 10,
PHYDM_ARFR2_AC_2G_1SS = 11,
PHYDM_ARFR3_AC_2G_2SS = 12,
PHYDM_ARFR4_AC_3SS = 13,
PHYDM_ARFR5_N_3SS = 14
};
#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */
struct _odm_ra_info_ {
u8 rate_id;
u32 rate_mask;
u32 ra_use_rate;
u8 rate_sgi;
u8 rssi_sta_ra;
u8 pre_rssi_sta_ra;
u8 sgi_enable;
u8 decision_rate;
u8 pre_rate;
u8 highest_rate;
u8 lowest_rate;
u32 nsc_up;
u32 nsc_down;
u16 RTY[5];
u32 TOTAL;
u16 DROP;
u8 active;
u16 rpt_time;
u8 ra_waiting_counter;
u8 ra_pending_counter;
u8 ra_drop_after_down;
#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
u8 pt_active; /* on or off */
u8 pt_try_state; /* 0 trying state, 1 for decision state */
u8 pt_stage; /* 0~6 */
u8 pt_stop_count; /* Stop PT counter */
u8 pt_pre_rate; /* if rate change do PT */
u8 pt_pre_rssi; /* if RSSI change 5% do PT */
u8 pt_mode_ss; /* decide whitch rate should do PT */
u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */
u8 pt_smooth_factor;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
u8 rate_down_counter;
u8 rate_up_counter;
u8 rate_direction;
u8 bounding_type;
u8 bounding_counter;
u8 bounding_learning_time;
u8 rate_down_start_time;
#endif
};
#endif
struct ra_table {
u8 firstconnect;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
boolean PT_collision_pre;
#endif
#if (defined(CONFIG_RA_DBG_CMD))
boolean is_ra_dbg_init;
u8 RTY_P[ODM_NUM_RATE_IDX];
u8 RTY_P_default[ODM_NUM_RATE_IDX];
boolean RTY_P_modify_note[ODM_NUM_RATE_IDX];
u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
boolean RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
boolean RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
boolean ra_para_feedback_req;
u8 para_idx;
u8 rate_idx;
u8 value;
u16 value_16;
u8 rate_length;
#endif
/*u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
u8 mu1_rate[30];
u8 highest_client_tx_order;
u16 highest_client_tx_rate_order;
u8 power_tracking_flag;
u8 RA_threshold_offset;
u8 RA_offset_direction;
u8 up_ramask_cnt; /*force update_ra_mask counter*/
u8 up_ramask_cnt_tmp; /*Just for debug, should be removed latter*/
#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
u8 retry_descend_num;
u8 retrylimit_low;
u8 retrylimit_high;
#endif
u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */
void (*record_ra_info)(void *dm_void, u8 macid, struct cmn_sta_info *sta, u64 ra_mask);
};
void
phydm_h2C_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
#if (defined(CONFIG_RA_DBG_CMD))
void
odm_RA_debug(
void *dm_void,
u32 *const dm_value
);
void
odm_ra_para_adjust_init(
void *dm_void
);
#endif
void
phydm_ra_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len
);
void
odm_c2h_ra_para_report_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
void
odm_ra_para_adjust(
void *dm_void
);
void
phydm_ra_dynamic_retry_count(
void *dm_void
);
void
phydm_ra_dynamic_retry_limit(
void *dm_void
);
void
phydm_print_rate(
void *dm_void,
u8 rate,
u32 dbg_component
);
void
phydm_c2h_ra_report_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
u8
phydm_rate_order_compute(
void *dm_void,
u8 rate_idx
);
void
phydm_ra_info_watchdog(
void *dm_void
);
void
phydm_ra_info_init(
void *dm_void
);
void
phydm_modify_RA_PCR_threshold(
void *dm_void,
u8 RA_offset_direction,
u8 RA_threshold_offset
);
u8
phydm_vht_en_mapping(
void *dm_void,
u32 wireless_mode
);
u8
phydm_rate_id_mapping(
void *dm_void,
u32 wireless_mode,
u8 rf_type,
u8 bw
);
void
phydm_update_hal_ra_mask(
void *dm_void,
u32 wireless_mode,
u8 rf_type,
u8 BW,
u8 mimo_ps_enable,
u8 disable_cck_rate,
u32 *ratr_bitmap_msb_in,
u32 *ratr_bitmap_in,
u8 tx_rate_level
);
void
phydm_refresh_rate_adaptive_mask(
void *dm_void
);
u8
phydm_rssi_lv_dec(
void *dm_void,
u32 rssi,
u8 ratr_state
);
void
odm_ra_post_action_on_assoc(
void *dm
);
u8
odm_find_rts_rate(
void *dm_void,
u8 tx_rate,
boolean is_erp_protect
);
void
phydm_show_sta_info(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
u8
phydm_get_plcp(
void *dm_void,
u16 macid
);
#ifdef PHYDM_3RD_REFORM_RA_MASK
void
phydm_ra_registed(
void *dm_void,
u8 macid,
u8 rssi_from_assoc
);
void
phydm_ra_offline(
void *dm_void,
u8 macid
);
void
phydm_ra_mask_watchdog(
void *dm_void
);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_refresh_basic_rate_mask(
void *dm_void
);
void
odm_update_init_rate_work_item_callback(
void *context
);
void
odm_refresh_ldpc_rts_mp(
void *adapter,
struct dm_struct *dm,
u8 m_mac_id,
u8 iot_peer,
s32 undecorated_smoothed_pwdb
);
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
void
phydm_gen_ramask_h2c_AP(
void *dm_void,
struct rtl8192cd_priv *priv,
struct sta_info *entry,
u8 rssi_level
);
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
#if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
void
phydm_ra_dynamic_rate_id_on_assoc(
void *dm_void,
u8 wireless_mode,
u8 init_rate_id
);
void
phydm_ra_dynamic_rate_id_init(
void *dm_void
);
void
phydm_update_rate_id(
void *dm_void,
u8 rate,
u8 platform_macid
);
#endif
#endif /*#ifndef __ODMRAINFO_H__*/

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hal/phydm/phydm_reg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* File Name: odm_reg.h
*
* Description:
*
* This file is for general register definition.
*
*
* ************************************************************ */
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
/*
* Register Definition
* */
/* MAC REG */
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
/* LTE_COEX */
#define REG_LTECOEX_CTRL 0x07C0
#define REG_LTECOEX_WRITE_DATA 0x07C4
#define REG_LTECOEX_READ_DATA 0x07C8
#define REG_LTECOEX_PATH_CONTROL 0x70
/* BB REG */
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
/* RF REG */
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
#define ODM_RF_T_METER 0x24
#define ODM_RF_T_METER_92D 0x42
#define ODM_RF_T_METER_88E 0x42
#define ODM_RF_T_METER_92E 0x42
#define ODM_RF_T_METER_8812 0x42
#define REG_RF_TX_GAIN_OFFSET 0x55
/* ant Detect Reg */
#define ODM_DPDT 0x300
/* PSD Init */
#define ODM_PSDREG 0x808
/* 92D path Div */
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
/*
* Bitmap Definition
* */
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
/* TX AGC */
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8
#endif
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8
#endif
#define is_tx_agc_byte0_jaguar 0xff
#define is_tx_agc_byte1_jaguar 0xff00
#define is_tx_agc_byte2_jaguar 0xff0000
#define is_tx_agc_byte3_jaguar 0xff000000
#endif
#define BIT_FA_RESET BIT(0)
#endif

103
hal/phydm/phydm_regdefine11ac.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
/* 2 RF REG LIST */
/* 2 BB REG LIST
* PAGE 8 */
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_BB_TX_PATH_11AC 0x80c
#define ODM_REG_BB_ATC_11AC 0x860
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
#define ODM_REG_DBG_RPT_11AC 0x8fc
/* PAGE 9 */
#define ODM_REG_EDCCA_DOWN_OPT 0x900
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_CCX_PERIOD_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_CLM_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
/* PAGE A */
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
/* PAGE B */
#define ODM_REG_RST_RPT_11AC 0xB58
/* PAGE C */
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
/* PAGE E */
#define ODM_REG_IGI_B_11AC 0xE50
#define ODM_REG_TRMUX_11AC_B 0xE08
/* PAGE F */
#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC
#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC
#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0
#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4
#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_CLM_RESULT_11AC 0xfa4
#define ODM_REG_NHM_CNT_11AC 0xfa8
#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
/* PAGE 18 */
#define ODM_REG_IGI_C_11AC 0x1850
/* PAGE 1A */
#define ODM_REG_IGI_D_11AC 0x1A50
/* 2 MAC REG LIST */
#define ODM_REG_RESP_TX_11AC 0x6D8
/* DIG Related */
#define ODM_BIT_IGI_11AC 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#define ODM_BIT_BB_TX_PATH_11AC 0xF
#define ODM_BIT_BB_ATC_11AC BIT(14)
#endif

219
hal/phydm/phydm_regdefine11n.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
/* 2 RF REG LIST */
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
/* 2 BB REG LIST
* PAGE 8 */
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
#define ODM_REG_RX_DEFAULT_A_11N 0x858
#define ODM_REG_RX_DEFAULT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_CCX_PERIOD_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_CLM_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_TH8_11N 0xe28
#define ODM_REG_CLM_READY_11N 0x8b4
#define ODM_REG_CLM_RESULT_11N 0x8d0
#define ODM_REG_NHM_CNT_11N 0x8d8
/* For struct acs_info, Jeffery, 2014-12-26 */
#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
/* PAGE 9 */
#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_BB_TX_PATH_11N 0x90c
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
#define ODM_REG_RX_DFIR_MOD_97F 0x948
#define ODM_REG_SOML_97F 0x998
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_ANT_SEL_11N 0xA04
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
#define ODM_REG_RXCK_RFMOD 0xBB0
#define ODM_REG_EDCCA_DCNF_97F 0xBC0
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_BB_AGC_SET_2_11N 0xc74
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_BB_RX_ANT_11N 0xD04
#define ODM_REG_BB_ATC_11N 0xD2C
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
/* PAGE E */
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_EDCCA_DCNF_11N 0xE24
#define ODM_REG_TAP_UPD_97F 0xE24
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_PAGE_B1_97F 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
/* PAGE F */
#define ODM_REG_PAGE_F_RST_11N 0xF14
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
#define ODM_REG_HT_CRC32_CNT_11N 0xF90
#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
/* 2 MAC REG LIST */
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/* DIG Related */
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
#define ODM_BIT_BB_RX_PATH_11N 0xF
#define ODM_BIT_BB_TX_PATH_11N 0xF
#define ODM_BIT_BB_ATC_11N BIT(11)
#endif

563
hal/phydm/phydm_regtable.h Normal file
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#define R_0x0 0x0
#define R_0x00 0x00
#define R_0x0140 0x0140
#define R_0x040 0x040
#define R_0x10 0x10
#define R_0x1080 0x1080
#define R_0x14c0 0x14c0
#define R_0x14c4 0x14c4
#define R_0x14c8 0x14c8
#define R_0x14cc 0x14cc
#define R_0x1518 0x1518
#define R_0x1684 0x1684
#define R_0x1688 0x1688
#define R_0x168c 0x168c
#define R_0x1700 0x1700
#define R_0x1704 0x1704
#define R_0x1800 0x1800
#define R_0x183c 0x183c
#define R_0x1840 0x1840
#define R_0x1844 0x1844
#define R_0x1848 0x1848
#define R_0x188c 0x188c
#define R_0x1894 0x1894
#define R_0x18ac 0x18ac
#define R_0x1900 0x1900
#define R_0x1904 0x1904
#define R_0x1908 0x1908
#define R_0x1918 0x1918
#define R_0x191c 0x191c
#define R_0x1928 0x1928
#define R_0x1950 0x1950
#define R_0x1954 0x1954
#define R_0x195c 0x195c
#define R_0x1984 0x1984
#define R_0x1988 0x1988
#define R_0x198c 0x198c
#define R_0x1990 0x1990
#define R_0x1991 0x1991
#define R_0x1998 0x1998
#define R_0x19a8 0x19a8
#define R_0x19d4 0x19d4
#define R_0x19d8 0x19d8
#define R_0x19e0 0x19e0
#define R_0x19f0 0x19f0
#define R_0x19f8 0x19f8
#define R_0x1a00 0x1a00
#define R_0x1a04 0x1a04
#define R_0x1a24 0x1a24
#define R_0x1a28 0x1a28
#define R_0x1a2c 0x1a2c
#define R_0x1a5c 0x1a5c
#define R_0x1a84 0x1a84
#define R_0x1a8c 0x1a8c
#define R_0x1a94 0x1a94
#define R_0x1aac 0x1aac
#define R_0x1abc 0x1abc
#define R_0x1ac0 0x1ac0
#define R_0x1b00 0x1b00
#define R_0x1b08 0x1b08
#define R_0x1b0c 0x1b0c
#define R_0x1b2c 0x1b2c
#define R_0x1b38 0x1b38
#define R_0x1b3c 0x1b3c
#define R_0x1b8c 0x1b8c
#define R_0x1b98 0x1b98
#define R_0x1bc8 0x1bc8
#define R_0x1bcc 0x1bcc
#define R_0x1bd0 0x1bd0
#define R_0x1bd4 0x1bd4
#define R_0x1bd8 0x1bd8
#define R_0x1bf0 0x1bf0
#define R_0x1bfc 0x1bfc
#define R_0x1c28 0x1c28
#define R_0x1c38 0x1c38
#define R_0x1c3c 0x1c3c
#define R_0x1c68 0x1c68
#define R_0x1c74 0x1c74
#define R_0x1c78 0x1c78
#define R_0x1c7c 0x1c7c
#define R_0x1c90 0x1c90
#define R_0x1c94 0x1c94
#define R_0x1c98 0x1c98
#define R_0x1c9c 0x1c9c
#define R_0x1ca0 0x1ca0
#define R_0x1cb8 0x1cb8
#define R_0x1cf8 0x1cf8
#define R_0x1d70 0x1d70
#define R_0x1e2c 0x1e2c
#define R_0x1e5c 0x1e5c
#define R_0x1eb4 0x1eb4
#define R_0x2c04 0x2c04
#define R_0x2c08 0x2c08
#define R_0x2c10 0x2c10
#define R_0x2c14 0x2c14
#define R_0x2d00 0x2d00
#define R_0x2d04 0x2d04
#define R_0x2d08 0x2d08
#define R_0x2d10 0x2d10
#define R_0x2d20 0x2d20
#define R_0x2de8 0x2de8
#define R_0x300 0x300
#define R_0x38 0x38
#define R_0x40 0x40
#define R_0x4000 0x4000
#define R_0x4008 0x4008
#define R_0x4018 0x4018
#define R_0x401c 0x401c
#define R_0x4028 0x4028
#define R_0x4100 0x4100
#define R_0x413c 0x413c
#define R_0x4140 0x4140
#define R_0x4144 0x4144
#define R_0x4148 0x4148
#define R_0x430 0x430
#define R_0x434 0x434
#define R_0x44 0x44
#define R_0x444 0x444
#define R_0x448 0x448
#define R_0x450 0x450
#define R_0x454 0x454
#define R_0x49c 0x49c
#define R_0x4a0 0x4a0
#define R_0x4a4 0x4a4
#define R_0x4a8 0x4a8
#define R_0x4c 0x4c
#define R_0x4c8 0x4c8
#define R_0x4cc 0x4cc
#define R_0x5000 0x5000
#define R_0x5008 0x5008
#define R_0x5018 0x5018
#define R_0x501c 0x501c
#define R_0x5028 0x5028
#define R_0x5100 0x5100
#define R_0x5108 0x5108
#define R_0x5118 0x5118
#define R_0x511c 0x511c
#define R_0x5128 0x5128
#define R_0x520 0x520
#define R_0x5200 0x5200
#define R_0x522 0x522
#define R_0x523c 0x523c
#define R_0x5240 0x5240
#define R_0x5244 0x5244
#define R_0x5248 0x5248
#define R_0x5300 0x5300
#define R_0x533c 0x533c
#define R_0x5340 0x5340
#define R_0x5344 0x5344
#define R_0x5348 0x5348
#define R_0x550 0x550
#define R_0x551 0x551
#define R_0x568 0x568
#define R_0x588 0x588
#define R_0x604 0x604
#define R_0x608 0x608
#define R_0x60f 0x60f
#define R_0x64 0x64
#define R_0x66 0x66
#define R_0x660 0x660
#define R_0x668 0x668
#define R_0x688 0x688
#define R_0x6a0 0x6a0
#define R_0x6d8 0x6d8
#define R_0x6dc 0x6dc
#define R_0x70 0x70
#define R_0x74 0x74
#define R_0x764 0x764
#define R_0x7b0 0x7b0
#define R_0x7b4 0x7b4
#define R_0x7c0 0x7c0
#define R_0x7c4 0x7c4
#define R_0x7c8 0x7c8
#define R_0x7cc 0x7cc
#define R_0x7f0 0x7f0
#define R_0x7f4 0x7f4
#define R_0x7f8 0x7f8
#define R_0x7fc 0x7fc
#define R_0x800 0x800
#define R_0x804 0x804
#define R_0x808 0x808
#define R_0x80c 0x80c
#define R_0x810 0x810
#define R_0x814 0x814
#define R_0x818 0x818
#define R_0x820 0x820
#define R_0x824 0x824
#define R_0x828 0x828
#define R_0x82c 0x82c
#define R_0x830 0x830
#define R_0x834 0x834
#define R_0x838 0x838
#define R_0x83c 0x83c
#define R_0x840 0x840
#define R_0x848 0x848
#define R_0x850 0x850
#define R_0x854 0x854
#define R_0x858 0x858
#define R_0x860 0x860
#define R_0x864 0x864
#define R_0x86c 0x86c
#define R_0x870 0x870
#define R_0x874 0x874
#define R_0x878 0x878
#define R_0x87c 0x87c
#define R_0x880 0x880
#define R_0x884 0x884
#define R_0x888 0x888
#define R_0x88c 0x88c
#define R_0x890 0x890
#define R_0x894 0x894
#define R_0x898 0x898
#define R_0x89c 0x89c
#define R_0x8a0 0x8a0
#define R_0x8a4 0x8a4
#define R_0x8ac 0x8ac
#define R_0x8b4 0x8b4
#define R_0x8c4 0x8c4
#define R_0x8c8 0x8c8
#define R_0x8cc 0x8cc
#define R_0x8d0 0x8d0
#define R_0x8d4 0x8d4
#define R_0x8d8 0x8d8
#define R_0x8dc 0x8dc
#define R_0x8f0 0x8f0
#define R_0x8f8 0x8f8
#define R_0x8fc 0x8fc
#define R_0x900 0x900
#define R_0x908 0x908
#define R_0x90c 0x90c
#define R_0x910 0x910
#define R_0x914 0x914
#define R_0x918 0x918
#define R_0x91c 0x91c
#define R_0x920 0x920
#define R_0x924 0x924
#define R_0x92c 0x92c
#define R_0x930 0x930
#define R_0x934 0x934
#define R_0x938 0x938
#define R_0x93c 0x93c
#define R_0x940 0x940
#define R_0x944 0x944
#define R_0x948 0x948
#define R_0x94c 0x94c
#define R_0x950 0x950
#define R_0x958 0x958
#define R_0x95c 0x95c
#define R_0x970 0x970
#define R_0x974 0x974
#define R_0x978 0x978
#define R_0x97c 0x97c
#define R_0x98c 0x98c
#define R_0x990 0x990
#define R_0x994 0x994
#define R_0x998 0x998
#define R_0x9a0 0x9a0
#define R_0x9a4 0x9a4
#define R_0x9ac 0x9ac
#define R_0x9b0 0x9b0
#define R_0x9b4 0x9b4
#define R_0x9cc 0x9cc
#define R_0x9d0 0x9d0
#define R_0x9e4 0x9e4
#define R_0xa0 0xa0
#define R_0xa00 0xa00
#define R_0xa04 0xa04
#define R_0xa08 0xa08
#define R_0xa0c 0xa0c
#define R_0xa10 0xa10
#define R_0xa14 0xa14
#define R_0xa20 0xa20
#define R_0xa24 0xa24
#define R_0xa28 0xa28
#define R_0xa2c 0xa2c
#define R_0xa70 0xa70
#define R_0xa74 0xa74
#define R_0xa78 0xa78
#define R_0xa8 0xa8
#define R_0xa80 0xa80
#define R_0xa84 0xa84
#define R_0xa9c 0xa9c
#define R_0xaa8 0xaa8
#define R_0xaac 0xaac
#define R_0xab4 0xab4
#define R_0xabc 0xabc
#define R_0xac8 0xac8
#define R_0xacc 0xacc
#define R_0xad0 0xad0
#define R_0xb0 0xb0
#define R_0xb00 0xb00
#define R_0xb04 0xb04
#define R_0xb07 0xb07
#define R_0xb08 0xb08
#define R_0xb0c 0xb0c
#define R_0xb10 0xb10
#define R_0xb14 0xb14
#define R_0xb18 0xb18
#define R_0xb1c 0xb1c
#define R_0xb20 0xb20
#define R_0xb24 0xb24
#define R_0xb28 0xb28
#define R_0xb2b 0xb2b
#define R_0xb2c 0xb2c
#define R_0xb30 0xb30
#define R_0xb34 0xb34
#define R_0xb38 0xb38
#define R_0xb3c 0xb3c
#define R_0xb40 0xb40
#define R_0xb44 0xb44
#define R_0xb48 0xb48
#define R_0xb54 0xb54
#define R_0xb58 0xb58
#define R_0xb60 0xb60
#define R_0xb64 0xb64
#define R_0xb68 0xb68
#define R_0xb6a 0xb6a
#define R_0xb6c 0xb6c
#define R_0xb6e 0xb6e
#define R_0xb70 0xb70
#define R_0xb74 0xb74
#define R_0xb77 0xb77
#define R_0xb78 0xb78
#define R_0xb7c 0xb7c
#define R_0xb80 0xb80
#define R_0xb84 0xb84
#define R_0xb88 0xb88
#define R_0xb8c 0xb8c
#define R_0xb90 0xb90
#define R_0xb94 0xb94
#define R_0xb98 0xb98
#define R_0xb9b 0xb9b
#define R_0xb9c 0xb9c
#define R_0xba0 0xba0
#define R_0xba4 0xba4
#define R_0xba8 0xba8
#define R_0xbac 0xbac
#define R_0xbad 0xbad
#define R_0xbc0 0xbc0
#define R_0xbc4 0xbc4
#define R_0xbc8 0xbc8
#define R_0xbcc 0xbcc
#define R_0xbd8 0xbd8
#define R_0xbdc 0xbdc
#define R_0xbe0 0xbe0
#define R_0xbe4 0xbe4
#define R_0xbe8 0xbe8
#define R_0xbec 0xbec
#define R_0xbf0 0xbf0
#define R_0xbf4 0xbf4
#define R_0xbf8 0xbf8
#define R_0xc00 0xc00
#define R_0xc04 0xc04
#define R_0xc08 0xc08
#define R_0xc0c 0xc0c
#define R_0xc10 0xc10
#define R_0xc14 0xc14
#define R_0xc1c 0xc1c
#define R_0xc20 0xc20
#define R_0xc24 0xc24
#define R_0xc30 0xc30
#define R_0xc38 0xc38
#define R_0xc3c 0xc3c
#define R_0xc40 0xc40
#define R_0xc44 0xc44
#define R_0xc4c 0xc4c
#define R_0xc50 0xc50
#define R_0xc54 0xc54
#define R_0xc58 0xc58
#define R_0xc5c 0xc5c
#define R_0xc6c 0xc6c
#define R_0xc70 0xc70
#define R_0xc74 0xc74
#define R_0xc78 0xc78
#define R_0xc7c 0xc7c
#define R_0xc80 0xc80
#define R_0xc84 0xc84
#define R_0xc88 0xc88
#define R_0xc8c 0xc8c
#define R_0xc90 0xc90
#define R_0xc94 0xc94
#define R_0xc9c 0xc9c
#define R_0xca0 0xca0
#define R_0xca4 0xca4
#define R_0xca8 0xca8
#define R_0xcac 0xcac
#define R_0xcb0 0xcb0
#define R_0xcb4 0xcb4
#define R_0xcb8 0xcb8
#define R_0xcbc 0xcbc
#define R_0xcbd 0xcbd
#define R_0xcbe 0xcbe
#define R_0xcc4 0xcc4
#define R_0xcc8 0xcc8
#define R_0xccc 0xccc
#define R_0xcd0 0xcd0
#define R_0xcd4 0xcd4
#define R_0xcd8 0xcd8
#define R_0xce0 0xce0
#define R_0xce4 0xce4
#define R_0xce8 0xce8
#define R_0xd00 0xd00
#define R_0xd04 0xd04
#define R_0xd0c 0xd0c
#define R_0xd10 0xd10
#define R_0xd14 0xd14
#define R_0xd2c 0xd2c
#define R_0xd30 0xd30
#define R_0xd40 0xd40
#define R_0xd44 0xd44
#define R_0xd48 0xd48
#define R_0xd4c 0xd4c
#define R_0xd50 0xd50
#define R_0xd54 0xd54
#define R_0xd5c 0xd5c
#define R_0xd6c 0xd6c
#define R_0xd7c 0xd7c
#define R_0xd80 0xd80
#define R_0xd84 0xd84
#define R_0xd8c 0xd8c
#define R_0xd90 0xd90
#define R_0xd94 0xd94
#define R_0xdac 0xdac
#define R_0xdb0 0xdb0
#define R_0xdb4 0xdb4
#define R_0xdb8 0xdb8
#define R_0xdbc 0xdbc
#define R_0xdcc 0xdcc
#define R_0xdd0 0xdd0
#define R_0xdd4 0xdd4
#define R_0xdd8 0xdd8
#define R_0xde0 0xde0
#define R_0xdec 0xdec
#define R_0xdf4 0xdf4
#define R_0xe00 0xe00
#define R_0xe04 0xe04
#define R_0xe08 0xe08
#define R_0xe10 0xe10
#define R_0xe14 0xe14
#define R_0xe1c 0xe1c
#define R_0xe20 0xe20
#define R_0xe24 0xe24
#define R_0xe28 0xe28
#define R_0xe30 0xe30
#define R_0xe34 0xe34
#define R_0xe38 0xe38
#define R_0xe3c 0xe3c
#define R_0xe40 0xe40
#define R_0xe44 0xe44
#define R_0xe48 0xe48
#define R_0xe4c 0xe4c
#define R_0xe50 0xe50
#define R_0xe54 0xe54
#define R_0xe5c 0xe5c
#define R_0xe64 0xe64
#define R_0xe70 0xe70
#define R_0xe80 0xe80
#define R_0xe84 0xe84
#define R_0xe8c 0xe8c
#define R_0xe90 0xe90
#define R_0xe94 0xe94
#define R_0xe98 0xe98
#define R_0xe9c 0xe9c
#define R_0xea0 0xea0
#define R_0xea4 0xea4
#define R_0xea8 0xea8
#define R_0xeac 0xeac
#define R_0xeb0 0xeb0
#define R_0xeb4 0xeb4
#define R_0xeb8 0xeb8
#define R_0xebc 0xebc
#define R_0xec0 0xec0
#define R_0xec4 0xec4
#define R_0xec8 0xec8
#define R_0xecc 0xecc
#define R_0xed4 0xed4
#define R_0xee8 0xee8
#define R_0xf0 0xf0
#define R_0xf08 0xf08
#define R_0xf0c 0xf0c
#define R_0xf10 0xf10
#define R_0xf14 0xf14
#define R_0xf20 0xf20
#define R_0xf2c 0xf2c
#define R_0xf30 0xf30
#define R_0xf34 0xf34
#define R_0xf4 0xf4
#define R_0xf44 0xf44
#define R_0xf48 0xf48
#define R_0xf4c 0xf4c
#define R_0xf80 0xf80
#define R_0xf84 0xf84
#define R_0xf88 0xf88
#define R_0xf8c 0xf8c
#define R_0xf90 0xf90
#define R_0xf94 0xf94
#define R_0xf98 0xf98
#define R_0xfa0 0xfa0
#define R_0xfa4 0xfa4
#define R_0xfbc 0xfbc
#define R_0xfc0 0xfc0
#define R_0xfc4 0xfc4
#define R_0xfc8 0xfc8
#define R_0xfcc 0xfcc
#define R_0xfd0 0xfd0
#define R_0xff0 0xff0
#define RF_0x0 0x0
#define RF_0x00 0x00
#define RF_0x08 0x08
#define RF_0x0c 0x0c
#define RF_0x0d 0x0d
#define RF_0x1 0x1
#define RF_0x18 0x18
#define RF_0x1bf0 0x1bf0
#define RF_0x2 0x2
#define RF_0x3 0x3
#define RF_0x30 0x30
#define RF_0x31 0x31
#define RF_0x32 0x32
#define RF_0x33 0x33
#define RF_0x35 0x35
#define RF_0x3e 0x3e
#define RF_0x3f 0x3f
#define RF_0x4 0x4
#define RF_0x42 0x42
#define RF_0x43 0x43
#define RF_0x51 0x51
#define RF_0x52 0x52
#define RF_0x54 0x54
#define RF_0x55 0x55
#define RF_0x56 0x56
#define RF_0x58 0x58
#define RF_0x5c 0x5c
#define RF_0x61 0x61
#define RF_0x64 0x64
#define RF_0x65 0x65
#define RF_0x66 0x66
#define RF_0x75 0x75
#define RF_0x76 0x76
#define RF_0x78 0x78
#define RF_0x7f 0x7f
#define RF_0x8 0x8
#define RF_0x80 0x80
#define RF_0x81 0x81
#define RF_0x86 0x86
#define RF_0x8d 0x8d
#define RF_0x8f 0x8f
#define RF_0xae 0xae
#define RF_0xb0 0xb0
#define RF_0xb8 0xb8
#define RF_0xbc 0xbc
#define RF_0xbe 0xbe
#define RF_0xc4 0xc4
#define RF_0xc9 0xc9
#define RF_0xca 0xca
#define RF_0xcc 0xcc
#define RF_0xd 0xd
#define RF_0xdd 0xdd
#define RF_0xde 0xde
#define RF_0xdf 0xdf
#define RF_0xed 0xed
#define RF_0xee 0xee
#define RF_0xef 0xef
#define RF_0xf5 0xf5

450
hal/phydm/phydm_rssi_monitor.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_SUPPORT_RSSI_MONITOR
#ifdef PHYDM_3RD_REFORM_RSSI_MONOTOR
void
phydm_rssi_monitor_h2c(
void *dm_void,
u8 macid
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_t = &dm->dm_ra_table;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct ra_sta_info *ra = NULL;
u8 h2c_val[H2C_MAX_LENGTH] = {0};
u8 stbc_en, ldpc_en;
u8 bf_en = 0;
u8 is_rx, is_tx;
if (is_sta_active(sta)) {
ra = &sta->ra_info;
} else {
PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s invalid sta_info\n", __func__);
return;
}
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id);
is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;
is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;
stbc_en = (sta->stbc_en) ? 1 : 0;
ldpc_en = (sta->ldpc_en) ? 1 : 0;
#ifdef CONFIG_BEAMFORMING
if ((sta->bf_info.ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
(sta->bf_info.vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
bf_en = 1;
}
#endif
if (ra_t->RA_threshold_offset != 0) {
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst = (( %s%d ))\n",
((ra_t->RA_offset_direction) ? "+" : "-"), ra_t->RA_threshold_offset);
}
h2c_val[0] = sta->mac_id;
h2c_val[1] = 0;
h2c_val[2] = sta->rssi_stat.rssi;
h2c_val[3] = is_rx | (stbc_en << 1) | ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);
h2c_val[4] = (ra_t->RA_threshold_offset & 0x7f) | ((ra_t->RA_offset_direction & 0x1) << 7);
h2c_val[5] = 0;
h2c_val[6] = 0;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]);
#if (RTL8188E_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8188E)
odm_ra_set_rssi_8188e(dm, (u8)(sta->mac_id & 0xFF), sta->rssi_stat.rssi & 0x7F);
else
#endif
{
odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c_val);
}
}
void
phydm_calculate_rssi_min_max(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta;
s8 rssi_max_tmp = 0, rssi_min_tmp = 100;
u8 i;
u8 sta_cnt = 0;
if (!dm->is_linked)
return;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (is_sta_active(sta)) {
sta_cnt++;
if (sta->rssi_stat.rssi < rssi_min_tmp)
rssi_min_tmp = sta->rssi_stat.rssi;
if (sta->rssi_stat.rssi > rssi_max_tmp)
rssi_max_tmp = sta->rssi_stat.rssi;
/*[Send RSSI to FW]*/
if (sta->ra_info.disable_ra == false)
phydm_rssi_monitor_h2c(dm, i);
if (sta_cnt == dm->number_linked_client)
break;
}
}
dm->rssi_max = (u8)rssi_max_tmp;
dm->rssi_min = (u8)rssi_min_tmp;
}
#endif
#if 0/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
s32
phydm_find_minimum_rssi(
struct dm_struct *dm,
void *adapter,
boolean *is_link_temp
)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
PMGNT_INFO mgnt_info = &adapter->MgntInfo;
boolean act_as_ap = ACTING_AS_AP(adapter);
/* 1.Determine the minimum RSSI */
if ((!mgnt_info->bMediaConnect) ||
(act_as_ap && (hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/
hal_data->MinUndecoratedPWDBForDM = 0;
*is_link_temp = false;
} else
*is_link_temp = true;
if (mgnt_info->bMediaConnect) { /* Default port*/
if (act_as_ap || mgnt_info->mIbss) {
hal_data->MinUndecoratedPWDBForDM = hal_data->EntryMinUndecoratedSmoothedPWDB;
/**/
} else {
hal_data->MinUndecoratedPWDBForDM = GET_DEFAULT_RSSI(mgnt_info);
/**/
}
} else { /* associated entry pwdb*/
hal_data->MinUndecoratedPWDBForDM = hal_data->EntryMinUndecoratedSmoothedPWDB;
/**/
}
return hal_data->MinUndecoratedPWDBForDM;
}
void
odm_rssi_monitor_check_mp(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
u8 h2c_parameter[H2C_0X42_LENGTH] = {0};
u32 i;
boolean is_ext_ra_info = true;
u8 cmdlen = H2C_0X42_LENGTH;
u8 tx_bf_en = 0, stbc_en = 0;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct sta_info *entry = NULL;
s32 tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
PMGNT_INFO mgnt_info = &adapter->MgntInfo;
PMGNT_INFO p_default_mgnt_info = &adapter->MgntInfo;
u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
#if (BEAMFORMING_SUPPORT == 1)
#ifndef BEAMFORMING_VERSION_1
enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
#endif
#endif
void *loop_adapter = GetDefaultAdapter(adapter);
if (dm->support_ic_type == ODM_RTL8188E) {
is_ext_ra_info = false;
cmdlen = 3;
}
while (loop_adapter) {
if (loop_adapter != NULL) {
mgnt_info = &loop_adapter->MgntInfo;
cur_tx_ok_cnt = loop_adapter->TxStats.NumTxBytesUnicast - mgnt_info->lastTxOkCnt;
cur_rx_ok_cnt = loop_adapter->RxStats.NumRxBytesUnicast - mgnt_info->lastRxOkCnt;
mgnt_info->lastTxOkCnt = cur_tx_ok_cnt;
mgnt_info->lastRxOkCnt = cur_rx_ok_cnt;
}
for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
if (IsAPModeExist(loop_adapter)) {
if (GetFirstExtAdapter(loop_adapter) != NULL &&
GetFirstExtAdapter(loop_adapter) == loop_adapter)
entry = AsocEntry_EnumStation(loop_adapter, i);
else if (GetFirstGOPort(loop_adapter) != NULL &&
IsFirstGoAdapter(loop_adapter))
entry = AsocEntry_EnumStation(loop_adapter, i);
} else {
if (GetDefaultAdapter(loop_adapter) == loop_adapter)
entry = AsocEntry_EnumStation(loop_adapter, i);
}
if (entry != NULL) {
if (entry->bAssociated) {
RT_DISP_ADDR(FDM, DM_PWDB, ("entry->mac_addr ="), GET_STA_INFO(entry).mac_addr);
RT_DISP(FDM, DM_PWDB, ("entry->rssi = 0x%x(%d)\n",
GET_STA_INFO(entry).rssi_stat.rssi, GET_STA_INFO(entry).rssi_stat.rssi));
/* 2 BF_en */
#if (BEAMFORMING_SUPPORT == 1)
#ifndef BEAMFORMING_VERSION_1
beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, GET_STA_INFO(entry).mac_id);
if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
tx_bf_en = 1;
#else
if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), entry))
tx_bf_en = 1;
#endif
#endif
/* 2 STBC_en */
if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) ||
TEST_FLAG(entry->HTInfo.STBC, STBC_HT_ENABLE_TX))
stbc_en = 1;
if (GET_STA_INFO(entry).rssi_stat.rssi < tmp_entry_min_pwdb)
tmp_entry_min_pwdb = GET_STA_INFO(entry).rssi_stat.rssi;
if (GET_STA_INFO(entry).rssi_stat.rssi > tmp_entry_max_pwdb)
tmp_entry_max_pwdb = GET_STA_INFO(entry).rssi_stat.rssi;
h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) | (ra_tab->RA_offset_direction << 7);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_threshold_offset = (( %s%d ))\n", ((ra_tab->RA_threshold_offset == 0) ? " " : ((ra_tab->RA_offset_direction) ? "+" : "-")), ra_tab->RA_threshold_offset);
if (is_ext_ra_info) {
if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
h2c_parameter[3] |= RAINFO_BE_RX_STATE;
if (tx_bf_en)
h2c_parameter[3] |= RAINFO_BF_STATE;
else {
if (stbc_en)
h2c_parameter[3] |= RAINFO_STBC_STATE;
}
if (dm->noisy_decision)
h2c_parameter[3] |= RAINFO_NOISY_STATE;
else
h2c_parameter[3] &= (~RAINFO_NOISY_STATE);
if (dm->h2c_rarpt_connect) {
h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "h2c_rarpt_connect = (( %d ))\n", dm->h2c_rarpt_connect);
}
}
h2c_parameter[2] = (u8)(GET_STA_INFO(entry).rssi_stat.rssi & 0xFF);
/* h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */
h2c_parameter[0] = (GET_STA_INFO(entry).mac_id);
odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
}
} else
break;
}
loop_adapter = GetNextExtAdapter(loop_adapter);
}
/*Default port*/
if (tmp_entry_max_pwdb != 0) { /* If associated entry is found */
hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb;
RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmp_entry_max_pwdb, tmp_entry_max_pwdb));
} else
hal_data->EntryMaxUndecoratedSmoothedPWDB = 0;
if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */
hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb;
RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb));
} else
hal_data->EntryMinUndecoratedSmoothedPWDB = 0;
/* Default porti sent RSSI to FW */
if (hal_data->bUseRAMask) {
PHYDM_DBG(dm, DBG_RSSI_MNTR, "1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n",
WIN_DEFAULT_PORT_MACID, GET_DEFAULT_RSSI(mgnt_info), hal_data->ra_rpt_linked);
if (GET_DEFAULT_RSSI(mgnt_info) > 0) {
PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_default_mgnt_info);
PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_default_mgnt_info);
/* BF_en*/
#if (BEAMFORMING_SUPPORT == 1)
#ifndef BEAMFORMING_VERSION_1
beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, p_default_mgnt_info->m_mac_id);
if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
tx_bf_en = 1;
#else
if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL))
tx_bf_en = 1;
#endif
#endif
/* STBC_en*/
if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) ||
TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX))
stbc_en = 1;
h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) | (ra_tab->RA_offset_direction << 7);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_threshold_offset = (( %s%d ))\n", ((ra_tab->RA_threshold_offset == 0) ? " " : ((ra_tab->RA_offset_direction) ? "+" : "-")), ra_tab->RA_threshold_offset);
if (is_ext_ra_info) {
if (tx_bf_en)
h2c_parameter[3] |= RAINFO_BF_STATE;
else {
if (stbc_en)
h2c_parameter[3] |= RAINFO_STBC_STATE;
}
if (dm->h2c_rarpt_connect) {
h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "h2c_rarpt_connect = (( %d ))\n", dm->h2c_rarpt_connect);
}
if (dm->noisy_decision == 1) {
h2c_parameter[3] |= RAINFO_NOISY_STATE;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "[RSSIMonitorCheckMP] Send H2C to FW\n");
} else
h2c_parameter[3] &= (~RAINFO_NOISY_STATE);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3]);
}
h2c_parameter[2] = (u8)(GET_DEFAULT_RSSI(mgnt_info) & 0xFF);
/*h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/
h2c_parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/
odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
}
} else
PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)GET_DEFAULT_RSSI(mgnt_info));
{
void *loop_adapter = GetDefaultAdapter(adapter);
boolean default_pointer_value, *is_link_temp = &default_pointer_value;
s32 global_rssi_min = 0xFF, local_rssi_min;
boolean is_link = false;
while (loop_adapter) {
local_rssi_min = phydm_find_minimum_rssi(dm, loop_adapter, is_link_temp);
/* dbg_print("hal_data->is_linked=%d, local_rssi_min=%d\n", hal_data->is_linked, local_rssi_min); */
if (*is_link_temp)
is_link = true;
if ((local_rssi_min < global_rssi_min) && (*is_link_temp))
global_rssi_min = local_rssi_min;
loop_adapter = GetNextExtAdapter(loop_adapter);
}
hal_data->bLinked = is_link;
dm->is_linked = is_link;
dm->rssi_min = (u8)((is_link) ? global_rssi_min : 0);
}
}
#endif
void
phydm_rssi_monitor_check(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
return;
if ((dm->phydm_sys_up_time % 2) == 1) /*for AP watchdog period = 1 sec*/
return;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
phydm_calculate_rssi_min_max(dm);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n",
dm->rssi_max, dm->rssi_min);
}
void
phydm_rssi_monitor_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
ra_tab->firstconnect = false;
dm->rssi_max = 0;
dm->rssi_min = 0;
}
#endif

75
hal/phydm/phydm_rssi_monitor.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_RSSI_MONITOR_H__
#define __PHYDM_RSSI_MONITOR_H__
#define RSSI_MONITOR_VERSION "1.0" /* 2017.05.011 Dino, Add phydm_rssi_monitor.h*/
/* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
#define H2C_0X42_LENGTH 5
#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX*/ /* ULDL */
#define RAINFO_STBC_STATE BIT(1)
#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
/*#define RAINFO_SHURTCUT_STATE BIT(3)*/
/*#define RAINFO_SHURTCUT_FLAG BIT(4)*/
#define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
#define RAINFO_BF_STATE BIT(6)
#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
void
phydm_rssi_monitor_check(
void *dm_void
);
void
phydm_rssi_monitor_init(
void *dm_void
);
#endif

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