220 lines
4.9 KiB
C
220 lines
4.9 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8188E_SUPPORT == 1)
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void
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odm_config_rf_reg_8188e(
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struct dm_struct *dm,
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u32 addr,
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u32 data,
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enum rf_path RF_PATH,
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u32 reg_addr
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)
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{
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#ifndef SMP_SYNC
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unsigned long x;
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#endif
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struct rtl8192cd_priv *priv = dm->priv;
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#endif
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if (addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else {
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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SAVE_INT_AND_CLI(x);
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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RESTORE_INT(x);
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#else
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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#endif
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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}
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}
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void
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odm_config_rf_radio_a_8188e(
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struct dm_struct *dm,
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u32 addr,
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u32 data
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)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data);
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}
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void
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odm_config_rf_radio_b_8188e(
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struct dm_struct *dm,
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u32 addr,
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u32 data
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)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data);
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}
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void
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odm_config_mac_8188e(
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struct dm_struct *dm,
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u32 addr,
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u8 data
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)
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{
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odm_write_1byte(dm, addr, data);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data);
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}
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void
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odm_config_bb_agc_8188e(
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struct dm_struct *dm,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data);
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}
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void
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odm_config_bb_phy_reg_pg_8188e(
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struct dm_struct *dm,
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u32 band,
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u32 rf_path,
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u32 tx_num,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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if (addr == 0xfe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else {
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data);
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#endif
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}
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}
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void
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odm_config_bb_txpwr_lmt_8188e(
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struct dm_struct *dm,
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u8 *regulation,
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u8 *band,
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u8 *bandwidth,
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u8 *rate_section,
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u8 *rf_path,
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u8 *channel,
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u8 *power_limit
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_SetTxPowerLimit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#endif
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}
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void
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odm_config_bb_phy_8188e(
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struct dm_struct *dm,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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if (addr == 0xfe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else {
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if (addr == 0xa24)
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dm->rf_calibrate_info.rega24 = data;
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data);
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}
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}
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#endif
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