472 lines
12 KiB
C
472 lines
12 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/* ************************************************************
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* include files
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef PHYDM_SUPPORT_CCKPD
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void
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phydm_write_cck_cca_th_new_cs_ratio(
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void *dm_void,
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u8 cca_th,
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u8 cca_th_aaa
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
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PHYDM_DBG(dm, DBG_CCKPD, "[New] pd_th=0x%x, cs_ratio=0x%x\n\n", cca_th, cca_th_aaa);
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if (cckpd_t->cur_cck_cca_thres != cca_th) {
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cckpd_t->cur_cck_cca_thres = cca_th;
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odm_set_bb_reg(dm, 0xa08, 0xf0000, cca_th);
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cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
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}
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if (cckpd_t->cck_cca_th_aaa != cca_th_aaa) {
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cckpd_t->cck_cca_th_aaa = cca_th_aaa;
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odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cca_th_aaa);
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cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
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}
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}
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void
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phydm_write_cck_cca_th(
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void *dm_void,
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u8 cca_th
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
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PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cca_th);
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if (cckpd_t->cur_cck_cca_thres != cca_th) {
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odm_write_1byte(dm, ODM_REG(CCK_CCA, dm), cca_th);
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cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
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}
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cckpd_t->cur_cck_cca_thres = cca_th;
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}
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void
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phydm_set_cckpd_val(
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void *dm_void,
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u32 *val_buf,
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u8 val_len
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (val_len != 2) {
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PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=2\n");
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return;
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}
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/*val_buf[0]: 0xa0a*/
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/*val_buf[1]: 0xaaa*/
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if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) {
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phydm_write_cck_cca_th_new_cs_ratio(dm, (u8)val_buf[0], (u8)val_buf[1]);
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} else {
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phydm_write_cck_cca_th(dm, (u8)val_buf[0]);
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}
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}
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boolean
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phydm_stop_cck_pd_th(
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void *dm_void
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) {
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PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n");
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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#ifdef MCR_WIRELESS_EXTEND
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phydm_write_cck_cca_th(dm, 0x43);
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#endif
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#endif
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return true;
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}
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if (dm->pause_ability & ODM_BB_CCK_PD) {
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PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n", dm->pause_lv_table.lv_cckpd);
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return true;
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}
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#if 0/*(DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))*/
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if (dm->ext_lna)
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return true;
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#endif
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return false;
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}
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void
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phydm_cckpd(
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void *dm_void
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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u8 cur_cck_cca_th= cckpd_t->cur_cck_cca_thres;
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if (dm->is_linked) {
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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/*Add hp_hw_id condition due to 22B LPS power consumption issue and [PCIE-1596]*/
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if (dm->hp_hw_id && (dm->traffic_load == TRAFFIC_ULTRA_LOW))
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cur_cck_cca_th = 0x40;
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else if (dm->rssi_min > 35)
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cur_cck_cca_th = 0xcd;
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else if (dm->rssi_min > 20) {
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if (cckpd_t->cck_fa_ma > 500)
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cur_cck_cca_th = 0xcd;
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else if (cckpd_t->cck_fa_ma < 250)
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cur_cck_cca_th = 0x83;
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} else {
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if((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) && (cckpd_t->cck_fa_ma > 200))
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cur_cck_cca_th = 0xc3; /*for ASUS OTA test*/
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else
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cur_cck_cca_th = 0x83;
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}
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#else /*ODM_AP*/
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if (dig_t->cur_ig_value > 0x32)
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cur_cck_cca_th = 0xed;
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else if (dig_t->cur_ig_value > 0x2a)
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cur_cck_cca_th = 0xdd;
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else if (dig_t->cur_ig_value > 0x24)
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cur_cck_cca_th = 0xcd;
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else
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cur_cck_cca_th = 0x83;
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#endif
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} else {
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if (cckpd_t->cck_fa_ma > 1000)
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cur_cck_cca_th = 0x83;
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else if (cckpd_t->cck_fa_ma < 500)
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cur_cck_cca_th = 0x40;
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}
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phydm_write_cck_cca_th(dm, cur_cck_cca_th);
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/*PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cur_cck_cca_th);*/
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}
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void
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phydm_cckpd_new_cs_ratio(
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void *dm_void
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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u8 pd_th = 0, cs_ration = 0, cs_2r_offset = 0;
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u8 igi_curr = dig_t->cur_ig_value;
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u8 en_2rcca;
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boolean is_update = true;
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PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
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en_2rcca = (u8)(odm_get_bb_reg(dm, 0xa2c, BIT(18)) && odm_get_bb_reg(dm, 0xa2c, BIT(22)));
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if (dm->is_linked) {
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if ((igi_curr > 0x38) && (dm->rssi_min > 32)) {
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cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP * 2;
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cs_2r_offset = 5;
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pd_th = 0xd;
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} else if ((igi_curr > 0x2a) && (dm->rssi_min > 32)) {
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cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP;
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cs_2r_offset = 4;
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pd_th = 0xd;
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} else if ((igi_curr > 0x24) || (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
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cs_ration = dig_t->aaa_default + AAA_BASE;
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cs_2r_offset = 3;
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pd_th = 0xd;
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} else if ((igi_curr <= 0x24) || (dm->rssi_min < 22)) {
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if (cckpd_t->cck_fa_ma > 1000) {
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cs_ration = dig_t->aaa_default + AAA_STEP;
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cs_2r_offset = 1;
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pd_th = 0x7;
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} else if (cckpd_t->cck_fa_ma < 500) {
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cs_ration = dig_t->aaa_default;
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pd_th = 0x3;
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} else {
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is_update = false;
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cs_ration = cckpd_t->cck_cca_th_aaa;
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pd_th = cckpd_t->cur_cck_cca_thres;
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}
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}
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} else {
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if (cckpd_t->cck_fa_ma > 1000) {
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cs_ration = dig_t->aaa_default + AAA_STEP;
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cs_2r_offset = 1;
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pd_th = 0x7;
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} else if (cckpd_t->cck_fa_ma < 500) {
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cs_ration = dig_t->aaa_default;
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pd_th = 0x3;
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} else {
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is_update = false;
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cs_ration = cckpd_t->cck_cca_th_aaa;
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pd_th = cckpd_t->cur_cck_cca_thres;
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}
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}
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if (en_2rcca)
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cs_ration = (cs_ration >= cs_2r_offset) ? (cs_ration - cs_2r_offset) : 0;
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PHYDM_DBG(dm, DBG_CCKPD,
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"[New] cs_ratio=0x%x, pd_th=0x%x\n", cs_ration, pd_th);
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if (is_update) {
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cckpd_t->cur_cck_cca_thres = pd_th;
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cckpd_t->cck_cca_th_aaa = cs_ration;
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odm_set_bb_reg(dm, 0xa08, 0xf0000, pd_th);
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odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cs_ration);
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}
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/*phydm_write_cck_cca_th_new_cs_ratio(dm, pd_th, cs_ration);*/
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}
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#endif
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void
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phydm_cck_pd_th(
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void *dm_void
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)
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{
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#ifdef PHYDM_SUPPORT_CCKPD
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_fa_struct *fa_t= &dm->false_alm_cnt;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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u32 cnt_cck_fail_tmp = fa_t->cnt_cck_fail;
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
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#endif
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PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
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if (phydm_stop_cck_pd_th(dm) == true)
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return;
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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cnt_cck_fail_tmp = (dm->original_dig_restore) ? (fa_t->cnt_cck_fail) : (fa_acc_t->cnt_cck_fail_1sec);
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#endif
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if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
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cckpd_t->cck_fa_ma = cnt_cck_fail_tmp;
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else {
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cckpd_t->cck_fa_ma = ((cckpd_t->cck_fa_ma << 1) +
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cckpd_t->cck_fa_ma + cnt_cck_fail_tmp) >> 2;
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}
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PHYDM_DBG(dm, DBG_CCKPD, "CCK FA=%d\n", cckpd_t->cck_fa_ma);
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if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC)
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phydm_cckpd_new_cs_ratio(dm);
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else
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phydm_cckpd(dm);
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#endif
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}
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void
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odm_pause_cck_packet_detection(
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void *dm_void,
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enum phydm_pause_type pause_type,
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enum phydm_pause_level pause_lv,
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u8 cck_pd_th
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)
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{
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#ifdef PHYDM_SUPPORT_CCKPD
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
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s8 max_level;
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u8 i;
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PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
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if ((cckpd_t->pause_bitmap == 0) &&
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(!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT)))) {
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PHYDM_DBG(dm, DBG_CCKPD, "Return: not support\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Return: Wrong LV !\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Set pause{Type, LV, val} = {%d, %d, 0x%x}\n",
|
||
|
|
pause_type, pause_lv, cck_pd_th);
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "pause LV=0x%x\n", cckpd_t->pause_bitmap);
|
||
|
|
|
||
|
|
for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n",
|
||
|
|
i, cckpd_t->pause_cckpd_value[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (pause_type) {
|
||
|
|
case PHYDM_PAUSE:
|
||
|
|
{
|
||
|
|
/* Disable CCK PD */
|
||
|
|
dm->support_ability &= ~ODM_BB_CCK_PD;
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Pause CCK PD th\n");
|
||
|
|
|
||
|
|
/* Backup original CCK PD threshold decided by CCK PD mechanism */
|
||
|
|
if (cckpd_t->pause_bitmap == 0) {
|
||
|
|
|
||
|
|
cckpd_t->cckpd_bkp = cckpd_t->cur_cck_cca_thres;
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "cckpd_bkp=0x%x\n",
|
||
|
|
cckpd_t->cckpd_bkp);
|
||
|
|
}
|
||
|
|
|
||
|
|
cckpd_t->pause_bitmap |= BIT(pause_lv); /* Update pause level */
|
||
|
|
cckpd_t->pause_cckpd_value[pause_lv] = cck_pd_th;
|
||
|
|
|
||
|
|
/* Write new CCK PD threshold */
|
||
|
|
if (BIT(pause_lv + 1) > cckpd_t->pause_bitmap) {
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "> ori pause LV=0x%x\n",
|
||
|
|
cckpd_t->pause_bitmap);
|
||
|
|
|
||
|
|
phydm_write_cck_cca_th(dm, cck_pd_th);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case PHYDM_RESUME:
|
||
|
|
{
|
||
|
|
/* check if the level is illegal or not */
|
||
|
|
if ((cckpd_t->pause_bitmap & (BIT(pause_lv))) != 0) {
|
||
|
|
|
||
|
|
cckpd_t->pause_bitmap &= (~(BIT(pause_lv)));
|
||
|
|
cckpd_t->pause_cckpd_value[pause_lv] = 0;
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Resume CCK PD\n");
|
||
|
|
} else {
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Wrong resume LV\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Resume CCKPD */
|
||
|
|
if (cckpd_t->pause_bitmap == 0) {
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Revert bkp_CCKPD=0x%x\n",
|
||
|
|
cckpd_t->cckpd_bkp);
|
||
|
|
|
||
|
|
phydm_write_cck_cca_th(dm, cckpd_t->cckpd_bkp);
|
||
|
|
dm->support_ability |= ODM_BB_CCK_PD;/* Enable CCKPD */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (BIT(pause_lv) <= cckpd_t->pause_bitmap)
|
||
|
|
break;
|
||
|
|
|
||
|
|
/* Calculate the maximum level now */
|
||
|
|
for (max_level = (pause_lv - 1); max_level >= 0; max_level--) {
|
||
|
|
if (cckpd_t->pause_bitmap & BIT(max_level))
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* write CCKPD of lower level */
|
||
|
|
phydm_write_cck_cca_th(dm, cckpd_t->pause_cckpd_value[max_level]);
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Write CCKPD=0x%x for max_LV=%d\n",
|
||
|
|
cckpd_t->pause_cckpd_value[max_level], max_level);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
default:
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "Wrong type\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "New pause bitmap=0x%x\n",
|
||
|
|
cckpd_t->pause_bitmap);
|
||
|
|
|
||
|
|
for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
|
||
|
|
PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n",
|
||
|
|
i, cckpd_t->pause_cckpd_value[i]);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_cck_pd_init(
|
||
|
|
void *dm_void
|
||
|
|
)
|
||
|
|
{
|
||
|
|
#ifdef PHYDM_SUPPORT_CCKPD
|
||
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||
|
|
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
|
||
|
|
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
|
||
|
|
|
||
|
|
cckpd_t->cur_cck_cca_thres = 0;
|
||
|
|
cckpd_t->cck_cca_th_aaa = 0;
|
||
|
|
|
||
|
|
cckpd_t->pause_bitmap = 0;
|
||
|
|
|
||
|
|
if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) {
|
||
|
|
dig_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
|
||
|
|
dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000);
|
||
|
|
cckpd_t->cck_cca_th_aaa = dig_t->aaa_default;
|
||
|
|
cckpd_t->cur_cck_cca_thres = dig_t->a0a_default;
|
||
|
|
} else {
|
||
|
|
dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000);
|
||
|
|
cckpd_t->cur_cck_cca_thres = dig_t->a0a_default;
|
||
|
|
}
|
||
|
|
|
||
|
|
odm_memory_set(dm, cckpd_t->pause_cckpd_value, 0, PHYDM_PAUSE_MAX_NUM);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
|