455 lines
13 KiB
C
455 lines
13 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2013 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include <rtw_odm.h>
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#include <hal_data.h>
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u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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struct dm_struct *podmpriv = &pHalData->odmpriv;
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u32 result = 0;
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switch (ops) {
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case HAL_PHYDM_DIS_ALL_FUNC:
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podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
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halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
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break;
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case HAL_PHYDM_FUNC_SET:
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podmpriv->support_ability |= ability;
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break;
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case HAL_PHYDM_FUNC_CLR:
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podmpriv->support_ability &= ~(ability);
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break;
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case HAL_PHYDM_ABILITY_BK:
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/* dm flag backup*/
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podmpriv->bk_support_ability = podmpriv->support_ability;
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pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
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break;
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case HAL_PHYDM_ABILITY_RESTORE:
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/* restore dm flag */
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podmpriv->support_ability = podmpriv->bk_support_ability;
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halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
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break;
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case HAL_PHYDM_ABILITY_SET:
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podmpriv->support_ability = ability;
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break;
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case HAL_PHYDM_ABILITY_GET:
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result = podmpriv->support_ability;
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break;
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}
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return result;
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}
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/* set ODM_CMNINFO_IC_TYPE based on chip_type */
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void rtw_odm_init_ic_type(_adapter *adapter)
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{
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struct dm_struct *odm = adapter_to_phydm(adapter);
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u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
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rtw_warn_on(!ic_type);
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odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
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}
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void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
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{
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RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
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}
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#define RTW_ADAPTIVITY_EN_DISABLE 0
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#define RTW_ADAPTIVITY_EN_ENABLE 1
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void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
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_RTW_PRINT_SEL(sel, "DISABLE\n");
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else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
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_RTW_PRINT_SEL(sel, "ENABLE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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#define RTW_ADAPTIVITY_MODE_NORMAL 0
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#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
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void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
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if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
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_RTW_PRINT_SEL(sel, "NORMAL\n");
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else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
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_RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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#define RTW_ADAPTIVITY_DML_DISABLE 0
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#define RTW_ADAPTIVITY_DML_ENABLE 1
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void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DML_");
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if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE)
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_RTW_PRINT_SEL(sel, "DISABLE\n");
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else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE)
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_RTW_PRINT_SEL(sel, "ENABLE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff);
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}
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void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
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{
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rtw_odm_adaptivity_ver_msg(sel, adapter);
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rtw_odm_adaptivity_en_msg(sel, adapter);
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rtw_odm_adaptivity_mode_msg(sel, adapter);
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rtw_odm_adaptivity_dml_msg(sel, adapter);
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rtw_odm_adaptivity_dc_backoff_msg(sel, adapter);
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}
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bool rtw_odm_adaptivity_needed(_adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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struct mlme_priv *mlme = &adapter->mlmepriv;
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bool ret = _FALSE;
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
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ret = _TRUE;
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return ret;
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}
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void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
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{
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struct dm_struct *odm = adapter_to_phydm(adapter);
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rtw_odm_adaptivity_config_msg(sel, adapter);
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RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n"
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, "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable");
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RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n"
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, (u8)odm->th_l2h_ini
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, odm->th_edcca_hl_diff
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, (u8)odm->th_l2h_ini_mode2
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, odm->th_edcca_hl_diff_mode2
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, odm->edcca_enable
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);
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RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag");
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RTW_PRINT_SEL(sel, "%-15x %-9x\n"
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, odm->adaptivity_enable
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, odm->adaptivity_flag
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);
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}
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void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable)
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{
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struct dm_struct *odm = adapter_to_phydm(adapter);
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odm->th_l2h_ini = th_l2h_ini;
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odm->th_edcca_hl_diff = th_edcca_hl_diff;
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odm->th_l2h_ini_mode2 = th_l2h_ini_mode2;
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odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2;
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odm->edcca_enable = edcca_enable;
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}
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void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
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{
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struct dm_struct *odm = adapter_to_phydm(adapter);
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RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
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HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
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}
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void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
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{
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
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_irqL irqL;
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switch (type) {
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case RT_IQK_SPINLOCK:
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_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
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default:
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break;
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}
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}
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void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
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{
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
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_irqL irqL;
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switch (type) {
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case RT_IQK_SPINLOCK:
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_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
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default:
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break;
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}
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}
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inline u8 rtw_odm_get_dfs_domain(_adapter *adapter)
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{
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#ifdef CONFIG_DFS_MASTER
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struct dm_struct *pDM_Odm = adapter_to_phydm(adapter);
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return pDM_Odm->dfs_region_domain;
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#else
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return PHYDM_DFS_DOMAIN_UNKNOWN;
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#endif
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}
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inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter)
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{
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#ifdef CONFIG_DFS_MASTER
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return rtw_odm_get_dfs_domain(adapter) == PHYDM_DFS_DOMAIN_UNKNOWN;
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#else
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return 1;
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#endif
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}
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#ifdef CONFIG_DFS_MASTER
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inline VOID rtw_odm_radar_detect_reset(_adapter *adapter)
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{
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phydm_radar_detect_reset(adapter_to_phydm(adapter));
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}
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inline VOID rtw_odm_radar_detect_disable(_adapter *adapter)
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{
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phydm_radar_detect_disable(adapter_to_phydm(adapter));
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}
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/* called after ch, bw is set */
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inline VOID rtw_odm_radar_detect_enable(_adapter *adapter)
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{
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phydm_radar_detect_enable(adapter_to_phydm(adapter));
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}
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inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
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{
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return phydm_radar_detect(adapter_to_phydm(adapter));
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}
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#endif /* CONFIG_DFS_MASTER */
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void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
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{
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#ifndef DBG_RX_PHYSTATUS_CHINFO
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#define DBG_RX_PHYSTATUS_CHINFO 0
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#endif
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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_adapter *adapter = rframe->u.hdr.adapter;
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struct dm_struct *phydm = adapter_to_phydm(adapter);
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struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
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u8 *wlanhdr = get_recvframe_data(rframe);
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if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
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/*
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* 8723D:
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* type_0(CCK)
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* l_rxsc
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* is filled with primary channel SC, not real rxsc.
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* 0:LSC, 1:USC
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* type_1(OFDM)
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* rf_mode
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* RF bandwidth when RX
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* l_rxsc(legacy), ht_rxsc
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* see below RXSC N-series
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* type_2(Not used)
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*/
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/*
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* 8821C, 8822B:
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* type_0(CCK)
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* l_rxsc
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* is filled with primary channel SC, not real rxsc.
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* 0:LSC, 1:USC
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* type_1(OFDM)
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* rf_mode
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* RF bandwidth when RX
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* l_rxsc(legacy), ht_rxsc
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* see below RXSC AC-series
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* type_2(Not used)
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*/
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if ((*phys & 0xf) == 0) {
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struct phy_status_rpt_jaguar2_type0 *phys_t0 = (struct phy_status_rpt_jaguar2_type0 *)phys;
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if (DBG_RX_PHYSTATUS_CHINFO) {
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RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
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, *phys & 0xf
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, MAC_ARG(get_ta(wlanhdr))
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, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
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, HDATA_RATE(attrib->data_rate)
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, phys_t0->band, phys_t0->channel, phys_t0->rxsc
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);
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}
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} else if ((*phys & 0xf) == 1) {
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struct phy_status_rpt_jaguar2_type1 *phys_t1 = (struct phy_status_rpt_jaguar2_type1 *)phys;
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u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
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u8 pkt_cch = 0;
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u8 pkt_bw = CHANNEL_WIDTH_20;
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#if ODM_IC_11N_SERIES_SUPPORT
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if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
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/* RXSC N-series */
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#define RXSC_DUP 0
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#define RXSC_LSC 1
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#define RXSC_USC 2
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#define RXSC_40M 3
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static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
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if (phys_t1->rf_mode == 0) {
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pkt_cch = phys_t1->channel;
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pkt_bw = CHANNEL_WIDTH_20;
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} else if (phys_t1->rf_mode == 1) {
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if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
|
||
|
|
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||
|
|
pkt_bw = CHANNEL_WIDTH_20;
|
||
|
|
} else if (rxsc == RXSC_40M) {
|
||
|
|
pkt_cch = phys_t1->channel;
|
||
|
|
pkt_bw = CHANNEL_WIDTH_40;
|
||
|
|
}
|
||
|
|
} else
|
||
|
|
rtw_warn_on(1);
|
||
|
|
|
||
|
|
goto type1_end;
|
||
|
|
}
|
||
|
|
#endif /* ODM_IC_11N_SERIES_SUPPORT */
|
||
|
|
|
||
|
|
#if ODM_IC_11AC_SERIES_SUPPORT
|
||
|
|
if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||
|
|
/* RXSC AC-series */
|
||
|
|
#define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
|
||
|
|
|
||
|
|
#define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
|
||
|
|
#define RXSC_L20M_OF_160M 6
|
||
|
|
#define RXSC_L20M_OF_80M 4
|
||
|
|
#define RXSC_L20M_OF_40M 2
|
||
|
|
#define RXSC_U20M_OF_40M 1
|
||
|
|
#define RXSC_U20M_OF_80M 3
|
||
|
|
#define RXSC_U20M_OF_160M 5
|
||
|
|
#define RXSC_UU20M_OF_160M 7
|
||
|
|
|
||
|
|
#define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
|
||
|
|
#define RXSC_L40M_OF_80M 10
|
||
|
|
#define RXSC_U40M_OF_80M 9
|
||
|
|
#define RXSC_U40M_OF_160M 11
|
||
|
|
|
||
|
|
#define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
|
||
|
|
#define RXSC_U80M_OF_160M 13
|
||
|
|
|
||
|
|
static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
|
||
|
|
|
||
|
|
if (phys_t1->rf_mode > 3) {
|
||
|
|
/* invalid rf_mode */
|
||
|
|
rtw_warn_on(1);
|
||
|
|
goto type1_end;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (phys_t1->rf_mode == 0) {
|
||
|
|
/* RF 20MHz */
|
||
|
|
pkt_cch = phys_t1->channel;
|
||
|
|
pkt_bw = CHANNEL_WIDTH_20;
|
||
|
|
goto type1_end;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (rxsc == 0) {
|
||
|
|
/* RF and RX with same BW */
|
||
|
|
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||
|
|
pkt_cch = phys_t1->channel;
|
||
|
|
pkt_bw = phys_t1->rf_mode;
|
||
|
|
}
|
||
|
|
goto type1_end;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
|
||
|
|
|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
|
||
|
|
|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
|
||
|
|
) {
|
||
|
|
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||
|
|
pkt_bw = CHANNEL_WIDTH_20;
|
||
|
|
} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
|
||
|
|
|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
|
||
|
|
) {
|
||
|
|
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||
|
|
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||
|
|
pkt_bw = CHANNEL_WIDTH_40;
|
||
|
|
}
|
||
|
|
} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
|
||
|
|
) {
|
||
|
|
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||
|
|
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||
|
|
pkt_bw = CHANNEL_WIDTH_80;
|
||
|
|
}
|
||
|
|
} else
|
||
|
|
rtw_warn_on(1);
|
||
|
|
|
||
|
|
}
|
||
|
|
#endif /* ODM_IC_11AC_SERIES_SUPPORT */
|
||
|
|
|
||
|
|
type1_end:
|
||
|
|
if (DBG_RX_PHYSTATUS_CHINFO) {
|
||
|
|
RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
|
||
|
|
, *phys & 0xf
|
||
|
|
, MAC_ARG(get_ta(wlanhdr))
|
||
|
|
, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
|
||
|
|
, HDATA_RATE(attrib->data_rate)
|
||
|
|
, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
|
||
|
|
, pkt_cch, pkt_bw
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* for now, only return cneter channel of 20MHz packet */
|
||
|
|
if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
|
||
|
|
attrib->ch = pkt_cch;
|
||
|
|
|
||
|
|
} else {
|
||
|
|
struct phy_status_rpt_jaguar2_type2 *phys_t2 = (struct phy_status_rpt_jaguar2_type2 *)phys;
|
||
|
|
|
||
|
|
if (DBG_RX_PHYSTATUS_CHINFO) {
|
||
|
|
RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
|
||
|
|
, *phys & 0xf
|
||
|
|
, MAC_ARG(get_ta(wlanhdr))
|
||
|
|
, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
|
||
|
|
, HDATA_RATE(attrib->data_rate)
|
||
|
|
, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
|
||
|
|
);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
|
||
|
|
|
||
|
|
}
|
||
|
|
|