Jimmy
5094c7bcee
Bring the five-panel hex portal online with a browser 3D/schematic preview, Pi SPI backends, and renamed multi-panel Pico UDP firmware. Co-authored-by: Cursor <cursoragent@cursor.com>
139 lines
3.9 KiB
Python
139 lines
3.9 KiB
Python
"""LED matrix layout defaults."""
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from __future__ import annotations
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import os
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from typing import Literal
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MATRIX_WIDTH = 45
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MATRIX_HEIGHT = 9
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MATRIX_PIXELS = MATRIX_WIDTH * MATRIX_HEIGHT # 405
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# --- Hexagonal portal -------------------------------------------------------
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# Bottom face = floor (no LEDs). Panels 0–4 numbered clockwise from bottom-left.
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# Panel 2 is the top face. All five panels are Pico UDP adapters.
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#
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# Viewed from outside:
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#
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# [2] TOP
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# [1] [3]
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# top-left top-right
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#
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# [0] [4]
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# bottom-left bottom-right
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#
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# Floor (no LEDs) is below.
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TOP_PANEL_INDEX = 2
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PORTAL_PANEL_ORDER_CLOCKWISE: tuple[int, ...] = (0, 1, 2, 3, 4)
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SIDE_PANEL_ORDER: tuple[int, ...] = (0, 1, 3, 4)
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PANEL_POSITION_BY_INDEX: dict[int, str] = {
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0: "bottom-left",
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1: "top-left",
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2: "top",
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3: "top-right",
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4: "bottom-right",
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}
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PortalFace = Literal["top", "side", "floor"]
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PANEL_FACE_BY_INDEX: dict[int, PortalFace] = {
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2: "top",
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0: "side",
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1: "side",
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3: "side",
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4: "side",
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}
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# Per-panel width (height is always 9 rows). Edit to match your hardware.
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# Panel 4 may still be 38 or 39 — run: panel_sync_test.py --test width --panel-index 4
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PANEL_HEIGHT = 9
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PANEL_WIDTH_BY_INDEX: dict[int, int] = {
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0: 39,
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1: 45,
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2: 45,
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3: 45,
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4: 39,
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}
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DEFAULT_PANEL_WIDTH = 45
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PANEL_COUNT = 5
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# Panels driven in-process by the animation script (SPI/PIO on this Pi).
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LOCAL_PANEL_INDICES: frozenset[int] = frozenset()
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# Optional: Pi UDP→SPI bridge panels (examples/panel_spi_bridge.py). Empty = all Pico.
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PI_BRIDGE_PANEL_INDICES: frozenset[int] = frozenset()
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# Optional: two panels on one Pico (GP27 + GP28).
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# Example — panels 0 and 1 on 10.1.1.10, strips 0 and 1:
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# PANEL_HOST_BY_INDEX = {0: "10.1.1.10", 1: "10.1.1.10"}
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# PANEL_STRIP_BY_INDEX = {0: 0, 1: 1}
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# PANEL_WS2812_PIN_BY_INDEX = {0: 28, 1: 27}
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PANEL_HOST_BY_INDEX: dict[int, str] = {}
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PANEL_STRIP_BY_INDEX: dict[int, int] = {}
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PANEL_WS2812_PIN_BY_INDEX: dict[int, int] = {}
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# Optional SPI bus override per panel index (Pi 5: 0 = GPIO 10, 1 = GPIO 20).
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PANEL_SPI_BUS_BY_INDEX: dict[int, int] = {}
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# SPI data line: bus 0 = GPIO 10 (MOSI), bus 1 = GPIO 20 (SPI1 MOSI)
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MATRIX_SPI_BUS = 0
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MATRIX_SPI_DEVICE = 0
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# One continuous chain on a single data pin; rows all run left → right.
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MATRIX_ROWS_PER_STRIP = None
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MATRIX_SERPENTINE = "none" # use "rows" for zigzag / serpentine wiring
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# Set True if DIN enters at the bottom row instead of the top.
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MATRIX_FLIP_Y = False
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MATRIX_BRIGHTNESS = 0.25
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# Optional wire reorder for direct SPI tests only (set PORTAL_WIRE_ORDER env).
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# UDP/bridge/firmware pass logical RGB through unchanged (default rgb = no swap).
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WIRE_ORDER = os.environ.get("PORTAL_WIRE_ORDER", "rgb").lower()
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def panel_width(panel_index: int) -> int:
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return PANEL_WIDTH_BY_INDEX.get(panel_index, DEFAULT_PANEL_WIDTH)
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def panel_layout(panel_index: int) -> tuple[int, int]:
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return panel_width(panel_index), PANEL_HEIGHT
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def panel_pixel_count(panel_index: int) -> int:
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w, h = panel_layout(panel_index)
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return w * h
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def panel_face(panel_index: int) -> PortalFace | None:
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return PANEL_FACE_BY_INDEX.get(panel_index)
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def panel_label(panel_index: int) -> str:
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face = panel_face(panel_index)
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pos = PANEL_POSITION_BY_INDEX.get(panel_index)
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if face == "top":
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return f"panel {panel_index} (top / Pi)"
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if pos:
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return f"panel {panel_index} ({pos})"
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if face == "side":
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return f"panel {panel_index} (side wall)"
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return f"panel {panel_index}"
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def matrix_pixel_index(
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x: int,
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y: int,
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width: int = MATRIX_WIDTH,
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height: int = MATRIX_HEIGHT,
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*,
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serpentine: str = MATRIX_SERPENTINE,
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flip_y: bool = MATRIX_FLIP_Y,
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) -> int:
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"""Map (x, y) to strip index. Default: every row left → right."""
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if flip_y:
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y = height - 1 - y
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col = x
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if serpentine == "rows" and y % 2 == 1:
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col = width - 1 - x
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return y * width + col
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