Add ESP32-C3 SPI slave with ESP-NOW, Raspberry Pi test tools, and updated project structure
- ESP32-C3 SPI slave project with ESP-NOW broadcast functionality - Raspberry Pi SPI master test tools and CLI for JSON communication - Merged src/ directory from full branch with lighting controller code - Updated Pipfile with system install scripts and ESP32 monitoring - Added comprehensive test suite for SPI communication
This commit is contained in:
Pi User
10558
esp32/build/bootloader/config/kconfig_menus.json
Normal file
10558
esp32/build/bootloader/config/kconfig_menus.json
Normal file
File diff suppressed because it is too large
Load Diff
788
esp32/build/bootloader/config/sdkconfig.cmake
Normal file
788
esp32/build/bootloader/config/sdkconfig.cmake
Normal file
File diff suppressed because one or more lines are too long
576
esp32/build/bootloader/config/sdkconfig.h
Normal file
576
esp32/build/bootloader/config/sdkconfig.h
Normal file
@@ -0,0 +1,576 @@
|
||||
/*
|
||||
* Automatically generated file. DO NOT EDIT.
|
||||
* Espressif IoT Development Framework (ESP-IDF) 6.0.0 Configuration Header
|
||||
*/
|
||||
#pragma once
|
||||
#define CONFIG_SOC_ADC_SUPPORTED 1
|
||||
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
|
||||
#define CONFIG_SOC_UART_SUPPORTED 1
|
||||
#define CONFIG_SOC_GDMA_SUPPORTED 1
|
||||
#define CONFIG_SOC_UHCI_SUPPORTED 1
|
||||
#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
|
||||
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
|
||||
#define CONFIG_SOC_TWAI_SUPPORTED 1
|
||||
#define CONFIG_SOC_BT_SUPPORTED 1
|
||||
#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
|
||||
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
|
||||
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
|
||||
#define CONFIG_SOC_XT_WDT_SUPPORTED 1
|
||||
#define CONFIG_SOC_PHY_SUPPORTED 1
|
||||
#define CONFIG_SOC_WIFI_SUPPORTED 1
|
||||
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG 1
|
||||
#define CONFIG_SOC_EFUSE_SUPPORTED 1
|
||||
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTED 1
|
||||
#define CONFIG_SOC_RMT_SUPPORTED 1
|
||||
#define CONFIG_SOC_SDM_SUPPORTED 1
|
||||
#define CONFIG_SOC_GPSPI_SUPPORTED 1
|
||||
#define CONFIG_SOC_LEDC_SUPPORTED 1
|
||||
#define CONFIG_SOC_I2C_SUPPORTED 1
|
||||
#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
|
||||
#define CONFIG_SOC_SUPPORT_COEXISTENCE 1
|
||||
#define CONFIG_SOC_AES_SUPPORTED 1
|
||||
#define CONFIG_SOC_MPI_SUPPORTED 1
|
||||
#define CONFIG_SOC_SHA_SUPPORTED 1
|
||||
#define CONFIG_SOC_HMAC_SUPPORTED 1
|
||||
#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1
|
||||
#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1
|
||||
#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1
|
||||
#define CONFIG_SOC_MEMPROT_SUPPORTED 1
|
||||
#define CONFIG_SOC_BOD_SUPPORTED 1
|
||||
#define CONFIG_SOC_CLK_TREE_SUPPORTED 1
|
||||
#define CONFIG_SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define CONFIG_SOC_WDT_SUPPORTED 1
|
||||
#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
|
||||
#define CONFIG_SOC_RNG_SUPPORTED 1
|
||||
#define CONFIG_SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
#define CONFIG_SOC_DEEP_SLEEP_SUPPORTED 1
|
||||
#define CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT 1
|
||||
#define CONFIG_SOC_PM_SUPPORTED 1
|
||||
#define CONFIG_SOC_XTAL_SUPPORT_40M 1
|
||||
#define CONFIG_SOC_AES_SUPPORT_DMA 1
|
||||
#define CONFIG_SOC_AES_GDMA 1
|
||||
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
|
||||
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
|
||||
#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_PERIPH_NUM 2
|
||||
#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 5
|
||||
#define CONFIG_SOC_ADC_ATTEN_NUM 4
|
||||
#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 1
|
||||
#define CONFIG_SOC_ADC_PATT_LEN_MAX 8
|
||||
#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
|
||||
#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
|
||||
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
|
||||
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
|
||||
#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
|
||||
#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
|
||||
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
|
||||
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
|
||||
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
|
||||
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
|
||||
#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1
|
||||
#define CONFIG_SOC_ADC_SHARED_POWER 1
|
||||
#define CONFIG_SOC_APB_BACKUP_DMA 1
|
||||
#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1
|
||||
#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1
|
||||
#define CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE 0x4000
|
||||
#define CONFIG_SOC_CPU_CORES_NUM 1
|
||||
#define CONFIG_SOC_CPU_INTR_NUM 32
|
||||
#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1
|
||||
#define CONFIG_SOC_CPU_HAS_CSR_PC 1
|
||||
#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 8
|
||||
#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 8
|
||||
#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000
|
||||
#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 3072
|
||||
#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
|
||||
#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
|
||||
#define CONFIG_SOC_AHB_GDMA_VERSION 1
|
||||
#define CONFIG_SOC_GDMA_NUM_GROUPS_MAX 1
|
||||
#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
#define CONFIG_SOC_GPIO_PORT 1
|
||||
#define CONFIG_SOC_GPIO_PIN_COUNT 22
|
||||
#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
|
||||
#define CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
|
||||
#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
|
||||
#define CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
|
||||
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 21
|
||||
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 21
|
||||
#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK 0
|
||||
#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT 6
|
||||
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0
|
||||
#define CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX 1
|
||||
#define CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM 3
|
||||
#define CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP 1
|
||||
#define CONFIG_SOC_I2C_NUM 1
|
||||
#define CONFIG_SOC_HP_I2C_NUM 1
|
||||
#define CONFIG_SOC_I2C_FIFO_LEN 32
|
||||
#define CONFIG_SOC_I2C_CMD_REG_NUM 8
|
||||
#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
|
||||
#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS 1
|
||||
#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
|
||||
#define CONFIG_SOC_I2C_SUPPORT_RTC 1
|
||||
#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
|
||||
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
|
||||
#define CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE 1
|
||||
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS 1
|
||||
#define CONFIG_SOC_I2S_NUM 1
|
||||
#define CONFIG_SOC_I2S_HW_VERSION_2 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_XTAL 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PCM2PDM 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1
|
||||
#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
|
||||
#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 1
|
||||
#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
|
||||
#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1
|
||||
#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
|
||||
#define CONFIG_SOC_LEDC_TIMER_NUM 4
|
||||
#define CONFIG_SOC_LEDC_CHANNEL_NUM 6
|
||||
#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 14
|
||||
#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
|
||||
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1
|
||||
#define CONFIG_SOC_MMU_PERIPH_NUM 1
|
||||
#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
|
||||
#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
|
||||
#define CONFIG_SOC_RMT_GROUPS 1
|
||||
#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 2
|
||||
#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 2
|
||||
#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4
|
||||
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
|
||||
#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_ASYNC_STOP 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_XTAL 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_APB 1
|
||||
#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1
|
||||
#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128
|
||||
#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 108
|
||||
#define CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1
|
||||
#define CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND 1
|
||||
#define CONFIG_SOC_RTCIO_PIN_COUNT 0
|
||||
#define CONFIG_SOC_MPI_MEM_BLOCKS_NUM 4
|
||||
#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
|
||||
#define CONFIG_SOC_RSA_MAX_BIT_LEN 3072
|
||||
#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
|
||||
#define CONFIG_SOC_SHA_SUPPORT_DMA 1
|
||||
#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
|
||||
#define CONFIG_SOC_SHA_GDMA 1
|
||||
#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
|
||||
#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
|
||||
#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
|
||||
#define CONFIG_SOC_SPI_PERIPH_NUM 2
|
||||
#define CONFIG_SOC_SPI_MAX_CS_NUM 6
|
||||
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
|
||||
#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1
|
||||
#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1
|
||||
#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
|
||||
#define CONFIG_SOC_SPI_SUPPORT_CLK_APB 1
|
||||
#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1
|
||||
#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
|
||||
#define CONFIG_SOC_SPI_SCT_SUPPORTED 1
|
||||
#define CONFIG_SOC_SPI_SCT_REG_NUM 14
|
||||
#define CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX 1
|
||||
#define CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA
|
||||
#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
|
||||
#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1
|
||||
#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1
|
||||
#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
|
||||
#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
|
||||
#define CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
|
||||
#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
|
||||
#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2
|
||||
#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3
|
||||
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32
|
||||
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20
|
||||
#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1
|
||||
#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1
|
||||
#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1
|
||||
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32
|
||||
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16
|
||||
#define CONFIG_SOC_MWDT_SUPPORT_XTAL 1
|
||||
#define CONFIG_SOC_TWAI_CONTROLLER_NUM 1
|
||||
#define CONFIG_SOC_TWAI_MASK_FILTER_NUM 1
|
||||
#define CONFIG_SOC_TWAI_CLK_SUPPORT_APB 1
|
||||
#define CONFIG_SOC_TWAI_BRP_MIN 2
|
||||
#define CONFIG_SOC_TWAI_BRP_MAX 16384
|
||||
#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1
|
||||
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
|
||||
#define CONFIG_SOC_EFUSE_DIS_PAD_JTAG 1
|
||||
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
|
||||
#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
|
||||
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
|
||||
#define CONFIG_SOC_EFUSE_DIS_ICACHE 1
|
||||
#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1
|
||||
#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
|
||||
#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
|
||||
#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 32
|
||||
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
|
||||
#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 512
|
||||
#define CONFIG_SOC_UART_NUM 2
|
||||
#define CONFIG_SOC_UART_HP_NUM 2
|
||||
#define CONFIG_SOC_UART_FIFO_LEN 128
|
||||
#define CONFIG_SOC_UART_BITRATE_MAX 5000000
|
||||
#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1
|
||||
#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
|
||||
#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
|
||||
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
|
||||
#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1
|
||||
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE 1
|
||||
#define CONFIG_SOC_UHCI_NUM 1
|
||||
#define CONFIG_SOC_COEX_HW_PTI 1
|
||||
#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21
|
||||
#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192
|
||||
#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
|
||||
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_WIFI_PD 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_BT_PD 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
|
||||
#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1
|
||||
#define CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL 1
|
||||
#define CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA 1
|
||||
#define CONFIG_SOC_PM_MODEM_PD_BY_SW 1
|
||||
#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1
|
||||
#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1
|
||||
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
|
||||
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
|
||||
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 1
|
||||
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1
|
||||
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL 1
|
||||
#define CONFIG_SOC_WIFI_HW_TSF 1
|
||||
#define CONFIG_SOC_WIFI_FTM_SUPPORT 1
|
||||
#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1
|
||||
#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1
|
||||
#define CONFIG_SOC_WIFI_CSI_SUPPORT 1
|
||||
#define CONFIG_SOC_WIFI_MESH_SUPPORT 1
|
||||
#define CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW 1
|
||||
#define CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND 1
|
||||
#define CONFIG_SOC_BLE_SUPPORTED 1
|
||||
#define CONFIG_SOC_BLE_MESH_SUPPORTED 1
|
||||
#define CONFIG_SOC_BLE_50_SUPPORTED 1
|
||||
#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1
|
||||
#define CONFIG_SOC_BLUFI_SUPPORTED 1
|
||||
#define CONFIG_SOC_PHY_COMBO_MODULE 1
|
||||
#define CONFIG_IDF_CMAKE 1
|
||||
#define CONFIG_IDF_TOOLCHAIN "gcc"
|
||||
#define CONFIG_IDF_TOOLCHAIN_GCC 1
|
||||
#define CONFIG_IDF_TARGET_ARCH_RISCV 1
|
||||
#define CONFIG_IDF_TARGET_ARCH "riscv"
|
||||
#define CONFIG_IDF_TARGET "esp32c3"
|
||||
#define CONFIG_IDF_INIT_VERSION "6.0.0"
|
||||
#define CONFIG_IDF_TARGET_ESP32C3 1
|
||||
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005
|
||||
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
|
||||
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
|
||||
#define CONFIG_APP_BUILD_BOOTLOADER 1
|
||||
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
|
||||
#define CONFIG_BOOTLOADER_COMPILE_TIME_DATE 1
|
||||
#define CONFIG_BOOTLOADER_PROJECT_VER 1
|
||||
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
|
||||
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
|
||||
#define CONFIG_BOOTLOADER_LOG_VERSION_1 1
|
||||
#define CONFIG_BOOTLOADER_LOG_VERSION 1
|
||||
#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
|
||||
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
|
||||
#define CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS 1
|
||||
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT_EN 1
|
||||
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT 1
|
||||
#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 80
|
||||
#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
|
||||
#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
|
||||
#define CONFIG_BOOTLOADER_WDT_ENABLE 1
|
||||
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
|
||||
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
|
||||
#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1
|
||||
#define CONFIG_SECURE_BOOT_V2_PREFERRED 1
|
||||
#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1
|
||||
#define CONFIG_APP_COMPILE_TIME_DATE 1
|
||||
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
|
||||
#define CONFIG_ESP_ROM_HAS_CRC_LE 1
|
||||
#define CONFIG_ESP_ROM_HAS_CRC_BE 1
|
||||
#define CONFIG_ESP_ROM_HAS_MZ_CRC32 1
|
||||
#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1
|
||||
#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1
|
||||
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 3
|
||||
#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1
|
||||
#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1
|
||||
#define CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV 1
|
||||
#define CONFIG_ESP_ROM_GET_CLK_FREQ 1
|
||||
#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1
|
||||
#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1
|
||||
#define CONFIG_ESP_ROM_HAS_SPI_FLASH 1
|
||||
#define CONFIG_ESP_ROM_HAS_SPI_FLASH_MMAP 1
|
||||
#define CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG 1
|
||||
#define CONFIG_ESP_ROM_HAS_NEWLIB 1
|
||||
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
|
||||
#define CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME 1
|
||||
#define CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE 1
|
||||
#define CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT 1
|
||||
#define CONFIG_ESP_ROM_HAS_SW_FLOAT 1
|
||||
#define CONFIG_ESP_ROM_USB_OTG_NUM -1
|
||||
#define CONFIG_ESP_ROM_HAS_VERSION 1
|
||||
#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
|
||||
#define CONFIG_ESP_ROM_CONSOLE_OUTPUT_SECONDARY 1
|
||||
#define CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY 1
|
||||
#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1
|
||||
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
|
||||
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
|
||||
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
|
||||
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
|
||||
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
|
||||
#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
|
||||
#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
|
||||
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
|
||||
#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
|
||||
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
|
||||
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
|
||||
#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
|
||||
#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
|
||||
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
|
||||
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
|
||||
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
|
||||
#define CONFIG_PARTITION_TABLE_MD5 1
|
||||
#define CONFIG_COMPILER_OPTIMIZATION_DEBUG 1
|
||||
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
|
||||
#define CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB 1
|
||||
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
|
||||
#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1
|
||||
#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1
|
||||
#define CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS 1
|
||||
#define CONFIG_COMPILER_RT_LIB_GCCLIB 1
|
||||
#define CONFIG_COMPILER_RT_LIB_NAME "gcc"
|
||||
#define CONFIG_COMPILER_ORPHAN_SECTIONS_ERROR 1
|
||||
#define CONFIG_COMPILER_CXX_GLIBCXX_CONSTEXPR_NO_CHANGE 1
|
||||
#define CONFIG_EFUSE_MAX_BLK_LEN 256
|
||||
#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
|
||||
#define CONFIG_ESP32C3_REV_MIN_3 1
|
||||
#define CONFIG_ESP32C3_REV_MIN_FULL 3
|
||||
#define CONFIG_ESP_REV_MIN_FULL 3
|
||||
#define CONFIG_ESP32C3_REV_MAX_FULL 199
|
||||
#define CONFIG_ESP_REV_MAX_FULL 199
|
||||
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
|
||||
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
|
||||
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
|
||||
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
|
||||
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
|
||||
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
|
||||
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1
|
||||
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES 4
|
||||
#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR 1
|
||||
#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4
|
||||
#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
|
||||
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
|
||||
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
|
||||
#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1
|
||||
#define CONFIG_RTC_CLK_SRC_INT_RC 1
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
#define CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM 1
|
||||
#define CONFIG_ESP_REGI2C_CTRL_FUNC_IN_IRAM 1
|
||||
#define CONFIG_GDMA_CTRL_FUNC_IN_IRAM 1
|
||||
#define CONFIG_GDMA_ISR_HANDLER_IN_IRAM 1
|
||||
#define CONFIG_GDMA_OBJ_DRAM_SAFE 1
|
||||
#define CONFIG_XTAL_FREQ_40 1
|
||||
#define CONFIG_XTAL_FREQ 40
|
||||
#define CONFIG_ESP_BROWNOUT_DET 1
|
||||
#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1
|
||||
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
|
||||
#define CONFIG_ESP_BROWNOUT_USE_INTR 1
|
||||
#define CONFIG_ESP_INTR_IN_IRAM 1
|
||||
#define CONFIG_LIBC_NEWLIB 1
|
||||
#define CONFIG_LIBC_MISC_IN_IRAM 1
|
||||
#define CONFIG_LIBC_LOCKS_PLACE_IN_IRAM 1
|
||||
#define CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT 1
|
||||
#define CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS 1
|
||||
#define CONFIG_LIBC_ASSERT_BUFFER_SIZE 200
|
||||
#define CONFIG_ESP_ROM_PRINT_IN_IRAM 1
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#define CONFIG_ESP_SYSTEM_IN_IRAM 1
|
||||
#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
|
||||
#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0
|
||||
#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1
|
||||
#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1
|
||||
#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1
|
||||
#define CONFIG_ESP_SYSTEM_NO_BACKTRACE 1
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT 1
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT_PMS 1
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT_PMS_LOCK 1
|
||||
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
|
||||
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304
|
||||
#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584
|
||||
#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1
|
||||
#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0
|
||||
#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
|
||||
#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
|
||||
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
|
||||
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 1
|
||||
#define CONFIG_ESP_CONSOLE_UART 1
|
||||
#define CONFIG_ESP_CONSOLE_UART_NUM 0
|
||||
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM 0
|
||||
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
|
||||
#define CONFIG_ESP_INT_WDT 1
|
||||
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
|
||||
#define CONFIG_ESP_TASK_WDT_EN 1
|
||||
#define CONFIG_ESP_TASK_WDT_INIT 1
|
||||
#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
|
||||
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
|
||||
#define CONFIG_ESP_DEBUG_OCDAWARE 1
|
||||
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
|
||||
#define CONFIG_ESP_SYSTEM_HW_STACK_GUARD 1
|
||||
#define CONFIG_ESP_SYSTEM_HW_PC_RECORD 1
|
||||
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
|
||||
#define CONFIG_FREERTOS_UNICORE 1
|
||||
#define CONFIG_FREERTOS_HZ 100
|
||||
#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1
|
||||
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
|
||||
#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
|
||||
#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
|
||||
#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
|
||||
#define CONFIG_FREERTOS_USE_TIMERS 1
|
||||
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME "Tmr Svc"
|
||||
#define CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY 1
|
||||
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY 0x7FFFFFFF
|
||||
#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1
|
||||
#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048
|
||||
#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10
|
||||
#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
|
||||
#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1
|
||||
#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
|
||||
#define CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS 1
|
||||
#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
|
||||
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
|
||||
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
|
||||
#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1
|
||||
#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1
|
||||
#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1
|
||||
#define CONFIG_FREERTOS_PORT 1
|
||||
#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
|
||||
#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1
|
||||
#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1
|
||||
#define CONFIG_FREERTOS_NUMBER_OF_CORES 1
|
||||
#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1
|
||||
#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2
|
||||
#define CONFIG_HAL_GPIO_USE_ROM_IMPL 1
|
||||
#define CONFIG_LOG_VERSION_1 1
|
||||
#define CONFIG_LOG_VERSION 1
|
||||
#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
|
||||
#define CONFIG_LOG_DEFAULT_LEVEL 3
|
||||
#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
|
||||
#define CONFIG_LOG_MAXIMUM_LEVEL 3
|
||||
#define CONFIG_LOG_DYNAMIC_LEVEL_CONTROL 1
|
||||
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST 1
|
||||
#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
|
||||
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE 31
|
||||
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
|
||||
#define CONFIG_LOG_MODE_TEXT_EN 1
|
||||
#define CONFIG_LOG_MODE_TEXT 1
|
||||
#define CONFIG_LOG_IN_IRAM 1
|
||||
#define CONFIG_MMU_PAGE_SIZE_64KB 1
|
||||
#define CONFIG_MMU_PAGE_MODE "64KB"
|
||||
#define CONFIG_MMU_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1
|
||||
#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1
|
||||
#define CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US 50
|
||||
#define CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM 1
|
||||
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
|
||||
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
|
||||
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
|
||||
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
|
||||
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
|
||||
#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
|
||||
#define CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1
|
||||
#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
|
||||
|
||||
/* List of deprecated options */
|
||||
#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
|
||||
#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
|
||||
#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
|
||||
#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT CONFIG_COMPILER_OPTIMIZATION_DEBUG
|
||||
#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
|
||||
#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
|
||||
#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
|
||||
#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
|
||||
#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
|
||||
#define CONFIG_ESP32C3_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
|
||||
#define CONFIG_ESP32C3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
|
||||
#define CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
|
||||
#define CONFIG_ESP32C3_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
|
||||
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
|
||||
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
|
||||
#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
|
||||
#define CONFIG_ESP32C3_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT
|
||||
#define CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_PMS_LOCK
|
||||
#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
|
||||
#define CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC
|
||||
#define CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT
|
||||
#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR CONFIG_ESP_BROWNOUT_USE_INTR
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_PMS_LOCK
|
||||
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_VIA_TEE CONFIG_ESP_SYSTEM_MEMPROT
|
||||
#define CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT CONFIG_ESP_SYSTEM_MEMPROT
|
||||
#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
|
||||
#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
|
||||
#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
|
||||
#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
|
||||
#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
|
||||
#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
|
||||
#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
|
||||
#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
|
||||
#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD
|
||||
#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT
|
||||
#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
|
||||
#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL
|
||||
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
|
||||
#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM
|
||||
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
|
||||
#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE
|
||||
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
|
||||
#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
|
||||
#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
|
||||
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
||||
#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
|
||||
#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
|
||||
#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY
|
||||
#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
|
||||
681
esp32/build/bootloader/config/sdkconfig.json
Normal file
681
esp32/build/bootloader/config/sdkconfig.json
Normal file
@@ -0,0 +1,681 @@
|
||||
{
|
||||
"APP_BUILD_BOOTLOADER": true,
|
||||
"APP_BUILD_GENERATE_BINARIES": true,
|
||||
"APP_BUILD_TYPE_APP_2NDBOOT": true,
|
||||
"APP_BUILD_TYPE_RAM": false,
|
||||
"APP_BUILD_USE_FLASH_SECTIONS": true,
|
||||
"APP_COMPILE_TIME_DATE": true,
|
||||
"APP_EXCLUDE_PROJECT_NAME_VAR": false,
|
||||
"APP_EXCLUDE_PROJECT_VER_VAR": false,
|
||||
"APP_NO_BLOBS": false,
|
||||
"APP_PROJECT_VER_FROM_CONFIG": false,
|
||||
"APP_REPRODUCIBLE_BUILD": false,
|
||||
"APP_RETRIEVE_LEN_ELF_SHA": 9,
|
||||
"BOOTLOADER_APP_ROLLBACK_ENABLE": false,
|
||||
"BOOTLOADER_APP_TEST": false,
|
||||
"BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG": false,
|
||||
"BOOTLOADER_COMPILER_OPTIMIZATION_PERF": false,
|
||||
"BOOTLOADER_COMPILER_OPTIMIZATION_SIZE": true,
|
||||
"BOOTLOADER_COMPILE_TIME_DATE": true,
|
||||
"BOOTLOADER_CPU_CLK_FREQ_MHZ": 80,
|
||||
"BOOTLOADER_CUSTOM_RESERVE_RTC": false,
|
||||
"BOOTLOADER_FACTORY_RESET": false,
|
||||
"BOOTLOADER_FLASH_DC_AWARE": false,
|
||||
"BOOTLOADER_FLASH_XMC_SUPPORT": true,
|
||||
"BOOTLOADER_LOG_COLORS": false,
|
||||
"BOOTLOADER_LOG_LEVEL": 3,
|
||||
"BOOTLOADER_LOG_LEVEL_DEBUG": false,
|
||||
"BOOTLOADER_LOG_LEVEL_ERROR": false,
|
||||
"BOOTLOADER_LOG_LEVEL_INFO": true,
|
||||
"BOOTLOADER_LOG_LEVEL_NONE": false,
|
||||
"BOOTLOADER_LOG_LEVEL_VERBOSE": false,
|
||||
"BOOTLOADER_LOG_LEVEL_WARN": false,
|
||||
"BOOTLOADER_LOG_MODE_TEXT": true,
|
||||
"BOOTLOADER_LOG_MODE_TEXT_EN": true,
|
||||
"BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS": true,
|
||||
"BOOTLOADER_LOG_VERSION": 1,
|
||||
"BOOTLOADER_LOG_VERSION_1": true,
|
||||
"BOOTLOADER_OFFSET_IN_FLASH": 0,
|
||||
"BOOTLOADER_PROJECT_VER": 1,
|
||||
"BOOTLOADER_REGION_PROTECTION_ENABLE": true,
|
||||
"BOOTLOADER_RESERVE_RTC_SIZE": 0,
|
||||
"BOOTLOADER_SKIP_VALIDATE_ALWAYS": false,
|
||||
"BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP": false,
|
||||
"BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON": false,
|
||||
"BOOTLOADER_WDT_DISABLE_IN_USER_CODE": false,
|
||||
"BOOTLOADER_WDT_ENABLE": true,
|
||||
"BOOTLOADER_WDT_TIME_MS": 9000,
|
||||
"BOOT_ROM_LOG_ALWAYS_OFF": false,
|
||||
"BOOT_ROM_LOG_ALWAYS_ON": true,
|
||||
"BOOT_ROM_LOG_ON_GPIO_HIGH": false,
|
||||
"BOOT_ROM_LOG_ON_GPIO_LOW": false,
|
||||
"COMPILER_ASSERT_NDEBUG_EVALUATE": false,
|
||||
"COMPILER_CXX_EXCEPTIONS": false,
|
||||
"COMPILER_CXX_GLIBCXX_CONSTEXPR_COLD": false,
|
||||
"COMPILER_CXX_GLIBCXX_CONSTEXPR_COLD_CONSTEXPR": false,
|
||||
"COMPILER_CXX_GLIBCXX_CONSTEXPR_NO_CHANGE": true,
|
||||
"COMPILER_CXX_RTTI": false,
|
||||
"COMPILER_DISABLE_DEFAULT_ERRORS": true,
|
||||
"COMPILER_DISABLE_GCC12_WARNINGS": false,
|
||||
"COMPILER_DISABLE_GCC13_WARNINGS": false,
|
||||
"COMPILER_DISABLE_GCC14_WARNINGS": false,
|
||||
"COMPILER_DISABLE_GCC15_WARNINGS": false,
|
||||
"COMPILER_DUMP_RTL_FILES": false,
|
||||
"COMPILER_FLOAT_LIB_FROM_GCCLIB": true,
|
||||
"COMPILER_HIDE_PATHS_MACROS": true,
|
||||
"COMPILER_NO_MERGE_CONSTANTS": false,
|
||||
"COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE": false,
|
||||
"COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE": true,
|
||||
"COMPILER_OPTIMIZATION_ASSERTIONS_SILENT": false,
|
||||
"COMPILER_OPTIMIZATION_ASSERTION_LEVEL": 2,
|
||||
"COMPILER_OPTIMIZATION_CHECKS_SILENT": false,
|
||||
"COMPILER_OPTIMIZATION_DEBUG": true,
|
||||
"COMPILER_OPTIMIZATION_NONE": false,
|
||||
"COMPILER_OPTIMIZATION_PERF": false,
|
||||
"COMPILER_OPTIMIZATION_SIZE": false,
|
||||
"COMPILER_ORPHAN_SECTIONS_ERROR": true,
|
||||
"COMPILER_ORPHAN_SECTIONS_PLACE": false,
|
||||
"COMPILER_ORPHAN_SECTIONS_WARNING": false,
|
||||
"COMPILER_RT_LIB_GCCLIB": true,
|
||||
"COMPILER_RT_LIB_NAME": "gcc",
|
||||
"COMPILER_SAVE_RESTORE_LIBCALLS": false,
|
||||
"COMPILER_STACK_CHECK_MODE_ALL": false,
|
||||
"COMPILER_STACK_CHECK_MODE_NONE": true,
|
||||
"COMPILER_STACK_CHECK_MODE_NORM": false,
|
||||
"COMPILER_STACK_CHECK_MODE_STRONG": false,
|
||||
"COMPILER_STATIC_ANALYZER": false,
|
||||
"COMPILER_WARN_WRITE_STRINGS": false,
|
||||
"EFUSE_CUSTOM_TABLE": false,
|
||||
"EFUSE_MAX_BLK_LEN": 256,
|
||||
"EFUSE_VIRTUAL": false,
|
||||
"ESP32C3_REV_MAX_FULL": 199,
|
||||
"ESP32C3_REV_MIN_0": false,
|
||||
"ESP32C3_REV_MIN_1": false,
|
||||
"ESP32C3_REV_MIN_101": false,
|
||||
"ESP32C3_REV_MIN_2": false,
|
||||
"ESP32C3_REV_MIN_3": true,
|
||||
"ESP32C3_REV_MIN_4": false,
|
||||
"ESP32C3_REV_MIN_FULL": 3,
|
||||
"ESP32C3_UNIVERSAL_MAC_ADDRESSES": 4,
|
||||
"ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
|
||||
"ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO": false,
|
||||
"ESPTOOLPY_AFTER": "hard_reset",
|
||||
"ESPTOOLPY_AFTER_NORESET": false,
|
||||
"ESPTOOLPY_AFTER_RESET": true,
|
||||
"ESPTOOLPY_BEFORE": "default_reset",
|
||||
"ESPTOOLPY_BEFORE_NORESET": false,
|
||||
"ESPTOOLPY_BEFORE_RESET": true,
|
||||
"ESPTOOLPY_FLASHFREQ": "80m",
|
||||
"ESPTOOLPY_FLASHFREQ_20M": false,
|
||||
"ESPTOOLPY_FLASHFREQ_26M": false,
|
||||
"ESPTOOLPY_FLASHFREQ_40M": false,
|
||||
"ESPTOOLPY_FLASHFREQ_80M": true,
|
||||
"ESPTOOLPY_FLASHMODE": "dio",
|
||||
"ESPTOOLPY_FLASHMODE_DIO": true,
|
||||
"ESPTOOLPY_FLASHMODE_DOUT": false,
|
||||
"ESPTOOLPY_FLASHMODE_QIO": false,
|
||||
"ESPTOOLPY_FLASHMODE_QOUT": false,
|
||||
"ESPTOOLPY_FLASHSIZE": "2MB",
|
||||
"ESPTOOLPY_FLASHSIZE_128MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_16MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_1MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_2MB": true,
|
||||
"ESPTOOLPY_FLASHSIZE_32MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_4MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_64MB": false,
|
||||
"ESPTOOLPY_FLASHSIZE_8MB": false,
|
||||
"ESPTOOLPY_FLASH_SAMPLE_MODE_STR": true,
|
||||
"ESPTOOLPY_HEADER_FLASHSIZE_UPDATE": false,
|
||||
"ESPTOOLPY_MONITOR_BAUD": 115200,
|
||||
"ESPTOOLPY_NO_STUB": false,
|
||||
"ESP_BROWNOUT_DET": true,
|
||||
"ESP_BROWNOUT_DET_LVL": 7,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_2": false,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_3": false,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_4": false,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_5": false,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_6": false,
|
||||
"ESP_BROWNOUT_DET_LVL_SEL_7": true,
|
||||
"ESP_BROWNOUT_USE_INTR": true,
|
||||
"ESP_CONSOLE_NONE": false,
|
||||
"ESP_CONSOLE_ROM_SERIAL_PORT_NUM": 0,
|
||||
"ESP_CONSOLE_SECONDARY_NONE": false,
|
||||
"ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG": true,
|
||||
"ESP_CONSOLE_UART": true,
|
||||
"ESP_CONSOLE_UART_BAUDRATE": 115200,
|
||||
"ESP_CONSOLE_UART_CUSTOM": false,
|
||||
"ESP_CONSOLE_UART_DEFAULT": true,
|
||||
"ESP_CONSOLE_UART_NUM": 0,
|
||||
"ESP_CONSOLE_USB_SERIAL_JTAG": false,
|
||||
"ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED": true,
|
||||
"ESP_DEBUG_OCDAWARE": true,
|
||||
"ESP_DEBUG_STUBS_ENABLE": false,
|
||||
"ESP_DEFAULT_CPU_FREQ_MHZ": 160,
|
||||
"ESP_DEFAULT_CPU_FREQ_MHZ_160": true,
|
||||
"ESP_DEFAULT_CPU_FREQ_MHZ_80": false,
|
||||
"ESP_EFUSE_BLOCK_REV_MAX_FULL": 199,
|
||||
"ESP_EFUSE_BLOCK_REV_MIN_FULL": 0,
|
||||
"ESP_ERR_TO_NAME_LOOKUP": true,
|
||||
"ESP_INTR_IN_IRAM": true,
|
||||
"ESP_INT_WDT": true,
|
||||
"ESP_INT_WDT_TIMEOUT_MS": 300,
|
||||
"ESP_IPC_TASK_STACK_SIZE": 1024,
|
||||
"ESP_MAC_ADDR_UNIVERSE_BT": true,
|
||||
"ESP_MAC_ADDR_UNIVERSE_ETH": true,
|
||||
"ESP_MAC_ADDR_UNIVERSE_WIFI_AP": true,
|
||||
"ESP_MAC_ADDR_UNIVERSE_WIFI_STA": true,
|
||||
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES": 4,
|
||||
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
|
||||
"ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC": false,
|
||||
"ESP_MAIN_TASK_AFFINITY": 0,
|
||||
"ESP_MAIN_TASK_AFFINITY_CPU0": true,
|
||||
"ESP_MAIN_TASK_AFFINITY_NO_AFFINITY": false,
|
||||
"ESP_MAIN_TASK_STACK_SIZE": 3584,
|
||||
"ESP_MINIMAL_SHARED_STACK_SIZE": 2048,
|
||||
"ESP_PANIC_HANDLER_IRAM": false,
|
||||
"ESP_PERIPH_CTRL_FUNC_IN_IRAM": true,
|
||||
"ESP_REGI2C_CTRL_FUNC_IN_IRAM": true,
|
||||
"ESP_REV_MAX_FULL": 199,
|
||||
"ESP_REV_MIN_FULL": 3,
|
||||
"ESP_ROM_CONSOLE_OUTPUT_SECONDARY": true,
|
||||
"ESP_ROM_GET_CLK_FREQ": true,
|
||||
"ESP_ROM_HAS_CRC_BE": true,
|
||||
"ESP_ROM_HAS_CRC_LE": true,
|
||||
"ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV": true,
|
||||
"ESP_ROM_HAS_ERASE_0_REGION_BUG": true,
|
||||
"ESP_ROM_HAS_ETS_PRINTF_BUG": true,
|
||||
"ESP_ROM_HAS_JPEG_DECODE": true,
|
||||
"ESP_ROM_HAS_LAYOUT_TABLE": true,
|
||||
"ESP_ROM_HAS_MZ_CRC32": true,
|
||||
"ESP_ROM_HAS_NEWLIB": true,
|
||||
"ESP_ROM_HAS_NEWLIB_32BIT_TIME": true,
|
||||
"ESP_ROM_HAS_NEWLIB_NANO_FORMAT": true,
|
||||
"ESP_ROM_HAS_RETARGETABLE_LOCKING": true,
|
||||
"ESP_ROM_HAS_SPI_FLASH": true,
|
||||
"ESP_ROM_HAS_SPI_FLASH_MMAP": true,
|
||||
"ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY": true,
|
||||
"ESP_ROM_HAS_SW_FLOAT": true,
|
||||
"ESP_ROM_HAS_VERSION": true,
|
||||
"ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE": true,
|
||||
"ESP_ROM_NEEDS_SWSETUP_WORKAROUND": true,
|
||||
"ESP_ROM_PRINT_IN_IRAM": true,
|
||||
"ESP_ROM_RAM_APP_NEEDS_MMU_INIT": true,
|
||||
"ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB": true,
|
||||
"ESP_ROM_UART_CLK_IS_XTAL": true,
|
||||
"ESP_ROM_USB_OTG_NUM": -1,
|
||||
"ESP_ROM_USB_SERIAL_DEVICE_NUM": 3,
|
||||
"ESP_SLEEP_CACHE_SAFE_ASSERTION": false,
|
||||
"ESP_SLEEP_DEBUG": false,
|
||||
"ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND": true,
|
||||
"ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS": true,
|
||||
"ESP_SLEEP_GPIO_RESET_WORKAROUND": true,
|
||||
"ESP_SLEEP_MSPI_NEED_ALL_IO_PU": false,
|
||||
"ESP_SLEEP_POWER_DOWN_FLASH": false,
|
||||
"ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY": 0,
|
||||
"ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP": true,
|
||||
"ESP_SYSTEM_CHECK_INT_LEVEL_4": true,
|
||||
"ESP_SYSTEM_EVENT_QUEUE_SIZE": 32,
|
||||
"ESP_SYSTEM_EVENT_TASK_STACK_SIZE": 2304,
|
||||
"ESP_SYSTEM_HW_PC_RECORD": true,
|
||||
"ESP_SYSTEM_HW_STACK_GUARD": true,
|
||||
"ESP_SYSTEM_IN_IRAM": true,
|
||||
"ESP_SYSTEM_MEMPROT": true,
|
||||
"ESP_SYSTEM_MEMPROT_PMS": true,
|
||||
"ESP_SYSTEM_MEMPROT_PMS_LOCK": true,
|
||||
"ESP_SYSTEM_NO_BACKTRACE": true,
|
||||
"ESP_SYSTEM_PANIC_PRINT_HALT": false,
|
||||
"ESP_SYSTEM_PANIC_PRINT_REBOOT": true,
|
||||
"ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS": 0,
|
||||
"ESP_SYSTEM_PANIC_SILENT_REBOOT": false,
|
||||
"ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK": true,
|
||||
"ESP_SYSTEM_SINGLE_CORE_MODE": true,
|
||||
"ESP_SYSTEM_USE_EH_FRAME": false,
|
||||
"ESP_SYSTEM_USE_FRAME_POINTER": false,
|
||||
"ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0": true,
|
||||
"ESP_TASK_WDT_EN": true,
|
||||
"ESP_TASK_WDT_INIT": true,
|
||||
"ESP_TASK_WDT_PANIC": false,
|
||||
"ESP_TASK_WDT_TIMEOUT_S": 5,
|
||||
"FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER": true,
|
||||
"FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE": false,
|
||||
"FREERTOS_CHECK_STACKOVERFLOW_CANARY": true,
|
||||
"FREERTOS_CHECK_STACKOVERFLOW_NONE": false,
|
||||
"FREERTOS_CHECK_STACKOVERFLOW_PTRVAL": false,
|
||||
"FREERTOS_CORETIMER_SYSTIMER_LVL1": true,
|
||||
"FREERTOS_CORETIMER_SYSTIMER_LVL3": false,
|
||||
"FREERTOS_DEBUG_OCDAWARE": true,
|
||||
"FREERTOS_ENABLE_BACKWARD_COMPATIBILITY": false,
|
||||
"FREERTOS_GENERATE_RUN_TIME_STATS": false,
|
||||
"FREERTOS_HZ": 100,
|
||||
"FREERTOS_IDLE_TASK_STACKSIZE": 1536,
|
||||
"FREERTOS_INTERRUPT_BACKTRACE": true,
|
||||
"FREERTOS_IN_IRAM": false,
|
||||
"FREERTOS_ISR_STACKSIZE": 1536,
|
||||
"FREERTOS_MAX_TASK_NAME_LEN": 16,
|
||||
"FREERTOS_NO_AFFINITY": 2147483647,
|
||||
"FREERTOS_NUMBER_OF_CORES": 1,
|
||||
"FREERTOS_OPTIMIZED_SCHEDULER": true,
|
||||
"FREERTOS_PORT": true,
|
||||
"FREERTOS_QUEUE_REGISTRY_SIZE": 0,
|
||||
"FREERTOS_SMP": false,
|
||||
"FREERTOS_SUPPORT_STATIC_ALLOCATION": true,
|
||||
"FREERTOS_SYSTICK_USES_SYSTIMER": true,
|
||||
"FREERTOS_TASK_FUNCTION_WRAPPER": true,
|
||||
"FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES": 1,
|
||||
"FREERTOS_TASK_PRE_DELETION_HOOK": false,
|
||||
"FREERTOS_THREAD_LOCAL_STORAGE_POINTERS": 1,
|
||||
"FREERTOS_TICK_SUPPORT_SYSTIMER": true,
|
||||
"FREERTOS_TIMER_QUEUE_LENGTH": 10,
|
||||
"FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY": 2147483647,
|
||||
"FREERTOS_TIMER_SERVICE_TASK_NAME": "Tmr Svc",
|
||||
"FREERTOS_TIMER_TASK_AFFINITY_CPU0": false,
|
||||
"FREERTOS_TIMER_TASK_NO_AFFINITY": true,
|
||||
"FREERTOS_TIMER_TASK_PRIORITY": 1,
|
||||
"FREERTOS_TIMER_TASK_STACK_DEPTH": 2048,
|
||||
"FREERTOS_TLSP_DELETION_CALLBACKS": true,
|
||||
"FREERTOS_UNICORE": true,
|
||||
"FREERTOS_USE_APPLICATION_TASK_TAG": false,
|
||||
"FREERTOS_USE_IDLE_HOOK": false,
|
||||
"FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES": false,
|
||||
"FREERTOS_USE_TICK_HOOK": false,
|
||||
"FREERTOS_USE_TIMERS": true,
|
||||
"FREERTOS_USE_TRACE_FACILITY": false,
|
||||
"FREERTOS_WATCHPOINT_END_OF_STACK": false,
|
||||
"GDMA_CTRL_FUNC_IN_IRAM": true,
|
||||
"GDMA_ENABLE_DEBUG_LOG": false,
|
||||
"GDMA_ISR_HANDLER_IN_IRAM": true,
|
||||
"GDMA_OBJ_DRAM_SAFE": true,
|
||||
"HAL_ASSERTION_DISABLE": false,
|
||||
"HAL_ASSERTION_ENABLE": false,
|
||||
"HAL_ASSERTION_EQUALS_SYSTEM": true,
|
||||
"HAL_ASSERTION_SILENT": false,
|
||||
"HAL_DEFAULT_ASSERTION_LEVEL": 2,
|
||||
"HAL_GPIO_USE_ROM_IMPL": true,
|
||||
"IDF_CMAKE": true,
|
||||
"IDF_EXPERIMENTAL_FEATURES": false,
|
||||
"IDF_FIRMWARE_CHIP_ID": 5,
|
||||
"IDF_INIT_VERSION": "6.0.0",
|
||||
"IDF_TARGET": "esp32c3",
|
||||
"IDF_TARGET_ARCH": "riscv",
|
||||
"IDF_TARGET_ARCH_RISCV": true,
|
||||
"IDF_TARGET_ESP32C3": true,
|
||||
"IDF_TOOLCHAIN": "gcc",
|
||||
"IDF_TOOLCHAIN_GCC": true,
|
||||
"LIBC_ASSERT_BUFFER_SIZE": 200,
|
||||
"LIBC_LOCKS_PLACE_IN_IRAM": true,
|
||||
"LIBC_MISC_IN_IRAM": true,
|
||||
"LIBC_NEWLIB": true,
|
||||
"LIBC_NEWLIB_NANO_FORMAT": false,
|
||||
"LIBC_OPTIMIZED_MISALIGNED_ACCESS": true,
|
||||
"LIBC_TIME_SYSCALL_USE_HRT": false,
|
||||
"LIBC_TIME_SYSCALL_USE_NONE": false,
|
||||
"LIBC_TIME_SYSCALL_USE_RTC": false,
|
||||
"LIBC_TIME_SYSCALL_USE_RTC_HRT": true,
|
||||
"LOG_COLORS": false,
|
||||
"LOG_DEFAULT_LEVEL": 3,
|
||||
"LOG_DEFAULT_LEVEL_DEBUG": false,
|
||||
"LOG_DEFAULT_LEVEL_ERROR": false,
|
||||
"LOG_DEFAULT_LEVEL_INFO": true,
|
||||
"LOG_DEFAULT_LEVEL_NONE": false,
|
||||
"LOG_DEFAULT_LEVEL_VERBOSE": false,
|
||||
"LOG_DEFAULT_LEVEL_WARN": false,
|
||||
"LOG_DYNAMIC_LEVEL_CONTROL": true,
|
||||
"LOG_IN_IRAM": true,
|
||||
"LOG_MASTER_LEVEL": false,
|
||||
"LOG_MAXIMUM_EQUALS_DEFAULT": true,
|
||||
"LOG_MAXIMUM_LEVEL": 3,
|
||||
"LOG_MAXIMUM_LEVEL_DEBUG": false,
|
||||
"LOG_MAXIMUM_LEVEL_VERBOSE": false,
|
||||
"LOG_MODE_TEXT": true,
|
||||
"LOG_MODE_TEXT_EN": true,
|
||||
"LOG_TAG_LEVEL_CACHE_ARRAY": false,
|
||||
"LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP": true,
|
||||
"LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST": true,
|
||||
"LOG_TAG_LEVEL_IMPL_CACHE_SIZE": 31,
|
||||
"LOG_TAG_LEVEL_IMPL_LINKED_LIST": false,
|
||||
"LOG_TAG_LEVEL_IMPL_NONE": false,
|
||||
"LOG_TIMESTAMP_SOURCE_RTOS": true,
|
||||
"LOG_TIMESTAMP_SOURCE_SYSTEM": false,
|
||||
"LOG_VERSION": 1,
|
||||
"LOG_VERSION_1": true,
|
||||
"LOG_VERSION_2": false,
|
||||
"MMU_PAGE_MODE": "64KB",
|
||||
"MMU_PAGE_SIZE": 65536,
|
||||
"MMU_PAGE_SIZE_64KB": true,
|
||||
"PARTITION_TABLE_CUSTOM": false,
|
||||
"PARTITION_TABLE_CUSTOM_FILENAME": "partitions.csv",
|
||||
"PARTITION_TABLE_FILENAME": "partitions_singleapp.csv",
|
||||
"PARTITION_TABLE_MD5": true,
|
||||
"PARTITION_TABLE_OFFSET": 32768,
|
||||
"PARTITION_TABLE_SINGLE_APP": true,
|
||||
"PARTITION_TABLE_SINGLE_APP_LARGE": false,
|
||||
"PARTITION_TABLE_TWO_OTA": false,
|
||||
"PARTITION_TABLE_TWO_OTA_LARGE": false,
|
||||
"RTC_CLK_CAL_CYCLES": 1024,
|
||||
"RTC_CLK_SRC_EXT_CRYS": false,
|
||||
"RTC_CLK_SRC_EXT_OSC": false,
|
||||
"RTC_CLK_SRC_INT_8MD256": false,
|
||||
"RTC_CLK_SRC_INT_RC": true,
|
||||
"SECURE_BOOT": false,
|
||||
"SECURE_BOOT_V2_PREFERRED": true,
|
||||
"SECURE_BOOT_V2_RSA_SUPPORTED": true,
|
||||
"SECURE_FLASH_ENC_ENABLED": false,
|
||||
"SECURE_ROM_DL_MODE_ENABLED": true,
|
||||
"SECURE_SIGNED_APPS_NO_SECURE_BOOT": false,
|
||||
"SOC_ADC_ARBITER_SUPPORTED": true,
|
||||
"SOC_ADC_ATTEN_NUM": 4,
|
||||
"SOC_ADC_CALIBRATION_V1_SUPPORTED": true,
|
||||
"SOC_ADC_DIGI_CONTROLLER_NUM": 1,
|
||||
"SOC_ADC_DIGI_DATA_BYTES_PER_CONV": 4,
|
||||
"SOC_ADC_DIGI_IIR_FILTER_NUM": 2,
|
||||
"SOC_ADC_DIGI_MAX_BITWIDTH": 12,
|
||||
"SOC_ADC_DIGI_MIN_BITWIDTH": 12,
|
||||
"SOC_ADC_DIGI_MONITOR_NUM": 2,
|
||||
"SOC_ADC_DIGI_RESULT_BYTES": 4,
|
||||
"SOC_ADC_DIG_CTRL_SUPPORTED": true,
|
||||
"SOC_ADC_DIG_IIR_FILTER_SUPPORTED": true,
|
||||
"SOC_ADC_DMA_SUPPORTED": true,
|
||||
"SOC_ADC_MAX_CHANNEL_NUM": 5,
|
||||
"SOC_ADC_MONITOR_SUPPORTED": true,
|
||||
"SOC_ADC_PATT_LEN_MAX": 8,
|
||||
"SOC_ADC_PERIPH_NUM": 2,
|
||||
"SOC_ADC_RTC_MAX_BITWIDTH": 12,
|
||||
"SOC_ADC_RTC_MIN_BITWIDTH": 12,
|
||||
"SOC_ADC_SAMPLE_FREQ_THRES_HIGH": 83333,
|
||||
"SOC_ADC_SAMPLE_FREQ_THRES_LOW": 611,
|
||||
"SOC_ADC_SELF_HW_CALI_SUPPORTED": true,
|
||||
"SOC_ADC_SHARED_POWER": true,
|
||||
"SOC_ADC_SUPPORTED": true,
|
||||
"SOC_AES_GDMA": true,
|
||||
"SOC_AES_SUPPORTED": true,
|
||||
"SOC_AES_SUPPORT_AES_128": true,
|
||||
"SOC_AES_SUPPORT_AES_256": true,
|
||||
"SOC_AES_SUPPORT_DMA": true,
|
||||
"SOC_AHB_GDMA_SUPPORTED": true,
|
||||
"SOC_AHB_GDMA_VERSION": 1,
|
||||
"SOC_APB_BACKUP_DMA": true,
|
||||
"SOC_ASSIST_DEBUG_SUPPORTED": true,
|
||||
"SOC_ASYNC_MEMCPY_SUPPORTED": true,
|
||||
"SOC_BLE_50_SUPPORTED": true,
|
||||
"SOC_BLE_DEVICE_PRIVACY_SUPPORTED": true,
|
||||
"SOC_BLE_MESH_SUPPORTED": true,
|
||||
"SOC_BLE_SUPPORTED": true,
|
||||
"SOC_BLUFI_SUPPORTED": true,
|
||||
"SOC_BOD_SUPPORTED": true,
|
||||
"SOC_BROWNOUT_RESET_SUPPORTED": true,
|
||||
"SOC_BT_SUPPORTED": true,
|
||||
"SOC_CACHE_FREEZE_SUPPORTED": true,
|
||||
"SOC_CACHE_MEMORY_IBANK_SIZE": 16384,
|
||||
"SOC_CLK_LP_FAST_SUPPORT_XTAL_D2": true,
|
||||
"SOC_CLK_RC_FAST_D256_SUPPORTED": true,
|
||||
"SOC_CLK_RC_FAST_SUPPORT_CALIBRATION": true,
|
||||
"SOC_CLK_TREE_SUPPORTED": true,
|
||||
"SOC_CLK_XTAL32K_SUPPORTED": true,
|
||||
"SOC_COEX_HW_PTI": true,
|
||||
"SOC_CPU_BREAKPOINTS_NUM": 8,
|
||||
"SOC_CPU_CORES_NUM": 1,
|
||||
"SOC_CPU_HAS_CSR_PC": true,
|
||||
"SOC_CPU_HAS_FLEXIBLE_INTC": true,
|
||||
"SOC_CPU_INTR_NUM": 32,
|
||||
"SOC_CPU_WATCHPOINTS_NUM": 8,
|
||||
"SOC_CPU_WATCHPOINT_MAX_REGION_SIZE": 2147483648,
|
||||
"SOC_DEDICATED_GPIO_SUPPORTED": true,
|
||||
"SOC_DEEP_SLEEP_SUPPORTED": true,
|
||||
"SOC_DIG_SIGN_SUPPORTED": true,
|
||||
"SOC_DS_KEY_CHECK_MAX_WAIT_US": 1100,
|
||||
"SOC_DS_KEY_PARAM_MD_IV_LENGTH": 16,
|
||||
"SOC_DS_SIGNATURE_MAX_BIT_LEN": 3072,
|
||||
"SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK": true,
|
||||
"SOC_EFUSE_DIS_DIRECT_BOOT": true,
|
||||
"SOC_EFUSE_DIS_DOWNLOAD_ICACHE": true,
|
||||
"SOC_EFUSE_DIS_ICACHE": true,
|
||||
"SOC_EFUSE_DIS_PAD_JTAG": true,
|
||||
"SOC_EFUSE_DIS_USB_JTAG": true,
|
||||
"SOC_EFUSE_HAS_EFUSE_RST_BUG": true,
|
||||
"SOC_EFUSE_KEY_PURPOSE_FIELD": true,
|
||||
"SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS": true,
|
||||
"SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS": 3,
|
||||
"SOC_EFUSE_SOFT_DIS_JTAG": true,
|
||||
"SOC_EFUSE_SUPPORTED": true,
|
||||
"SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX": 32,
|
||||
"SOC_FLASH_ENCRYPTION_XTS_AES": true,
|
||||
"SOC_FLASH_ENCRYPTION_XTS_AES_128": true,
|
||||
"SOC_FLASH_ENC_SUPPORTED": true,
|
||||
"SOC_GDMA_NUM_GROUPS_MAX": 1,
|
||||
"SOC_GDMA_PAIRS_PER_GROUP_MAX": 3,
|
||||
"SOC_GDMA_SUPPORTED": true,
|
||||
"SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX": true,
|
||||
"SOC_GPIO_CLOCKOUT_CHANNEL_NUM": 3,
|
||||
"SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT": 6,
|
||||
"SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK": 0,
|
||||
"SOC_GPIO_FILTER_CLK_SUPPORT_APB": true,
|
||||
"SOC_GPIO_IN_RANGE_MAX": 21,
|
||||
"SOC_GPIO_OUT_RANGE_MAX": 21,
|
||||
"SOC_GPIO_PIN_COUNT": 22,
|
||||
"SOC_GPIO_PORT": 1,
|
||||
"SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP": true,
|
||||
"SOC_GPIO_SUPPORT_FORCE_HOLD": true,
|
||||
"SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP": true,
|
||||
"SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER": true,
|
||||
"SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK": 4194240,
|
||||
"SOC_GPSPI_SUPPORTED": true,
|
||||
"SOC_GPTIMER_SUPPORTED": true,
|
||||
"SOC_HMAC_SUPPORTED": true,
|
||||
"SOC_HP_I2C_NUM": 1,
|
||||
"SOC_I2C_CMD_REG_NUM": 8,
|
||||
"SOC_I2C_FIFO_LEN": 32,
|
||||
"SOC_I2C_NUM": 1,
|
||||
"SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE": true,
|
||||
"SOC_I2C_SLAVE_SUPPORT_BROADCAST": true,
|
||||
"SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS": true,
|
||||
"SOC_I2C_SUPPORTED": true,
|
||||
"SOC_I2C_SUPPORT_10BIT_ADDR": true,
|
||||
"SOC_I2C_SUPPORT_HW_CLR_BUS": true,
|
||||
"SOC_I2C_SUPPORT_RTC": true,
|
||||
"SOC_I2C_SUPPORT_SLAVE": true,
|
||||
"SOC_I2C_SUPPORT_XTAL": true,
|
||||
"SOC_I2S_HW_VERSION_2": true,
|
||||
"SOC_I2S_NUM": 1,
|
||||
"SOC_I2S_PDM_MAX_RX_LINES": 1,
|
||||
"SOC_I2S_PDM_MAX_TX_LINES": 2,
|
||||
"SOC_I2S_SUPPORTED": true,
|
||||
"SOC_I2S_SUPPORTS_PCM": true,
|
||||
"SOC_I2S_SUPPORTS_PCM2PDM": true,
|
||||
"SOC_I2S_SUPPORTS_PDM": true,
|
||||
"SOC_I2S_SUPPORTS_PDM_RX": true,
|
||||
"SOC_I2S_SUPPORTS_PDM_TX": true,
|
||||
"SOC_I2S_SUPPORTS_PLL_F160M": true,
|
||||
"SOC_I2S_SUPPORTS_TDM": true,
|
||||
"SOC_I2S_SUPPORTS_XTAL": true,
|
||||
"SOC_LEDC_CHANNEL_NUM": 6,
|
||||
"SOC_LEDC_SUPPORTED": true,
|
||||
"SOC_LEDC_SUPPORT_APB_CLOCK": true,
|
||||
"SOC_LEDC_SUPPORT_FADE_STOP": true,
|
||||
"SOC_LEDC_SUPPORT_XTAL_CLOCK": true,
|
||||
"SOC_LEDC_TIMER_BIT_WIDTH": 14,
|
||||
"SOC_LEDC_TIMER_NUM": 4,
|
||||
"SOC_LIGHT_SLEEP_SUPPORTED": true,
|
||||
"SOC_LP_PERIPH_SHARE_INTERRUPT": true,
|
||||
"SOC_LP_TIMER_BIT_WIDTH_HI": 16,
|
||||
"SOC_LP_TIMER_BIT_WIDTH_LO": 32,
|
||||
"SOC_MAC_BB_PD_MEM_SIZE": 192,
|
||||
"SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE": 16,
|
||||
"SOC_MEMPROT_MEM_ALIGN_SIZE": 512,
|
||||
"SOC_MEMPROT_SUPPORTED": true,
|
||||
"SOC_MEMSPI_IS_INDEPENDENT": true,
|
||||
"SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED": true,
|
||||
"SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED": true,
|
||||
"SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED": true,
|
||||
"SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED": true,
|
||||
"SOC_MMU_LINEAR_ADDRESS_REGION_NUM": 1,
|
||||
"SOC_MMU_PERIPH_NUM": 1,
|
||||
"SOC_MPI_MEM_BLOCKS_NUM": 4,
|
||||
"SOC_MPI_OPERATIONS_NUM": 3,
|
||||
"SOC_MPI_SUPPORTED": true,
|
||||
"SOC_MPU_MIN_REGION_SIZE": 536870912,
|
||||
"SOC_MPU_REGIONS_MAX_NUM": 8,
|
||||
"SOC_MWDT_SUPPORT_XTAL": true,
|
||||
"SOC_PHY_COMBO_MODULE": true,
|
||||
"SOC_PHY_DIG_REGS_MEM_SIZE": 21,
|
||||
"SOC_PHY_SUPPORTED": true,
|
||||
"SOC_PM_CPU_RETENTION_BY_RTCCNTL": true,
|
||||
"SOC_PM_MODEM_PD_BY_SW": true,
|
||||
"SOC_PM_MODEM_RETENTION_BY_BACKUPDMA": true,
|
||||
"SOC_PM_SUPPORTED": true,
|
||||
"SOC_PM_SUPPORT_BT_PD": true,
|
||||
"SOC_PM_SUPPORT_BT_WAKEUP": true,
|
||||
"SOC_PM_SUPPORT_CPU_PD": true,
|
||||
"SOC_PM_SUPPORT_MAC_BB_PD": true,
|
||||
"SOC_PM_SUPPORT_RC_FAST_PD": true,
|
||||
"SOC_PM_SUPPORT_VDDSDIO_PD": true,
|
||||
"SOC_PM_SUPPORT_WIFI_PD": true,
|
||||
"SOC_PM_SUPPORT_WIFI_WAKEUP": true,
|
||||
"SOC_RMT_CHANNELS_PER_GROUP": 4,
|
||||
"SOC_RMT_GROUPS": 1,
|
||||
"SOC_RMT_MEM_WORDS_PER_CHANNEL": 48,
|
||||
"SOC_RMT_RX_CANDIDATES_PER_GROUP": 2,
|
||||
"SOC_RMT_SUPPORTED": true,
|
||||
"SOC_RMT_SUPPORT_APB": true,
|
||||
"SOC_RMT_SUPPORT_ASYNC_STOP": true,
|
||||
"SOC_RMT_SUPPORT_RC_FAST": true,
|
||||
"SOC_RMT_SUPPORT_RX_DEMODULATION": true,
|
||||
"SOC_RMT_SUPPORT_RX_PINGPONG": true,
|
||||
"SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY": true,
|
||||
"SOC_RMT_SUPPORT_TX_LOOP_COUNT": true,
|
||||
"SOC_RMT_SUPPORT_TX_SYNCHRO": true,
|
||||
"SOC_RMT_SUPPORT_XTAL": true,
|
||||
"SOC_RMT_TX_CANDIDATES_PER_GROUP": 2,
|
||||
"SOC_RNG_SUPPORTED": true,
|
||||
"SOC_RSA_MAX_BIT_LEN": 3072,
|
||||
"SOC_RTCIO_PIN_COUNT": 0,
|
||||
"SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH": 128,
|
||||
"SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM": 108,
|
||||
"SOC_RTC_FAST_MEM_SUPPORTED": true,
|
||||
"SOC_RTC_MEM_SUPPORTED": true,
|
||||
"SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256": true,
|
||||
"SOC_SDM_SUPPORTED": true,
|
||||
"SOC_SECURE_BOOT_SUPPORTED": true,
|
||||
"SOC_SECURE_BOOT_V2_RSA": true,
|
||||
"SOC_SHARED_IDCACHE_SUPPORTED": true,
|
||||
"SOC_SHA_DMA_MAX_BUFFER_SIZE": 3968,
|
||||
"SOC_SHA_GDMA": true,
|
||||
"SOC_SHA_SUPPORTED": true,
|
||||
"SOC_SHA_SUPPORT_DMA": true,
|
||||
"SOC_SHA_SUPPORT_RESUME": true,
|
||||
"SOC_SHA_SUPPORT_SHA1": true,
|
||||
"SOC_SHA_SUPPORT_SHA224": true,
|
||||
"SOC_SHA_SUPPORT_SHA256": true,
|
||||
"SOC_SLEEP_SYSTIMER_STALL_WORKAROUND": true,
|
||||
"SOC_SLEEP_TGWDT_STOP_WORKAROUND": true,
|
||||
"SOC_SPI_FLASH_SUPPORTED": true,
|
||||
"SOC_SPI_MAXIMUM_BUFFER_SIZE": 64,
|
||||
"SOC_SPI_MAX_CS_NUM": 6,
|
||||
"SOC_SPI_MAX_PRE_DIVIDER": 16,
|
||||
"SOC_SPI_MEM_SUPPORT_AUTO_RESUME": true,
|
||||
"SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND": true,
|
||||
"SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE": true,
|
||||
"SOC_SPI_MEM_SUPPORT_CHECK_SUS": true,
|
||||
"SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE": true,
|
||||
"SOC_SPI_MEM_SUPPORT_IDLE_INTR": true,
|
||||
"SOC_SPI_MEM_SUPPORT_SW_SUSPEND": true,
|
||||
"SOC_SPI_MEM_SUPPORT_WRAP": true,
|
||||
"SOC_SPI_PERIPH_NUM": 2,
|
||||
"SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT": true,
|
||||
"SOC_SPI_SCT_BUFFER_NUM_MAX": true,
|
||||
"SOC_SPI_SCT_CONF_BITLEN_MAX": 262138,
|
||||
"SOC_SPI_SCT_REG_NUM": 14,
|
||||
"SOC_SPI_SCT_SUPPORTED": true,
|
||||
"SOC_SPI_SLAVE_SUPPORT_SEG_TRANS": true,
|
||||
"SOC_SPI_SUPPORT_CD_SIG": true,
|
||||
"SOC_SPI_SUPPORT_CLK_APB": true,
|
||||
"SOC_SPI_SUPPORT_CLK_XTAL": true,
|
||||
"SOC_SPI_SUPPORT_CONTINUOUS_TRANS": true,
|
||||
"SOC_SPI_SUPPORT_DDRCLK": true,
|
||||
"SOC_SPI_SUPPORT_SLAVE_HD_VER2": true,
|
||||
"SOC_SUPPORTS_SECURE_DL_MODE": true,
|
||||
"SOC_SUPPORT_COEXISTENCE": true,
|
||||
"SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY": true,
|
||||
"SOC_SYSTIMER_ALARM_MISS_COMPENSATE": true,
|
||||
"SOC_SYSTIMER_ALARM_NUM": 3,
|
||||
"SOC_SYSTIMER_BIT_WIDTH_HI": 20,
|
||||
"SOC_SYSTIMER_BIT_WIDTH_LO": 32,
|
||||
"SOC_SYSTIMER_COUNTER_NUM": 2,
|
||||
"SOC_SYSTIMER_FIXED_DIVIDER": true,
|
||||
"SOC_SYSTIMER_INT_LEVEL": true,
|
||||
"SOC_SYSTIMER_SUPPORTED": true,
|
||||
"SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC": true,
|
||||
"SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL": true,
|
||||
"SOC_TEMP_SENSOR_SUPPORTED": true,
|
||||
"SOC_TWAI_BRP_MAX": 16384,
|
||||
"SOC_TWAI_BRP_MIN": 2,
|
||||
"SOC_TWAI_CLK_SUPPORT_APB": true,
|
||||
"SOC_TWAI_CONTROLLER_NUM": 1,
|
||||
"SOC_TWAI_MASK_FILTER_NUM": 1,
|
||||
"SOC_TWAI_SUPPORTED": true,
|
||||
"SOC_TWAI_SUPPORTS_RX_STATUS": true,
|
||||
"SOC_UART_BITRATE_MAX": 5000000,
|
||||
"SOC_UART_FIFO_LEN": 128,
|
||||
"SOC_UART_HP_NUM": 2,
|
||||
"SOC_UART_NUM": 2,
|
||||
"SOC_UART_SUPPORTED": true,
|
||||
"SOC_UART_SUPPORT_APB_CLK": true,
|
||||
"SOC_UART_SUPPORT_FSM_TX_WAIT_SEND": true,
|
||||
"SOC_UART_SUPPORT_RTC_CLK": true,
|
||||
"SOC_UART_SUPPORT_WAKEUP_INT": true,
|
||||
"SOC_UART_SUPPORT_XTAL_CLK": true,
|
||||
"SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE": true,
|
||||
"SOC_UHCI_NUM": 1,
|
||||
"SOC_UHCI_SUPPORTED": true,
|
||||
"SOC_USB_SERIAL_JTAG_SUPPORTED": true,
|
||||
"SOC_WDT_SUPPORTED": true,
|
||||
"SOC_WIFI_CSI_SUPPORT": true,
|
||||
"SOC_WIFI_FTM_SUPPORT": true,
|
||||
"SOC_WIFI_GCMP_SUPPORT": true,
|
||||
"SOC_WIFI_HW_TSF": true,
|
||||
"SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH": 12,
|
||||
"SOC_WIFI_MESH_SUPPORT": true,
|
||||
"SOC_WIFI_PHY_NEEDS_USB_WORKAROUND": true,
|
||||
"SOC_WIFI_SUPPORTED": true,
|
||||
"SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW": true,
|
||||
"SOC_WIFI_WAPI_SUPPORT": true,
|
||||
"SOC_XTAL_SUPPORT_40M": true,
|
||||
"SOC_XT_WDT_SUPPORTED": true,
|
||||
"SPI_FLASH_AUTO_SUSPEND": false,
|
||||
"SPI_FLASH_BROWNOUT_RESET": true,
|
||||
"SPI_FLASH_BROWNOUT_RESET_XMC": true,
|
||||
"SPI_FLASH_BYPASS_BLOCK_ERASE": false,
|
||||
"SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED": false,
|
||||
"SPI_FLASH_DANGEROUS_WRITE_ABORTS": true,
|
||||
"SPI_FLASH_DANGEROUS_WRITE_ALLOWED": false,
|
||||
"SPI_FLASH_DANGEROUS_WRITE_FAILS": false,
|
||||
"SPI_FLASH_ENABLE_COUNTERS": false,
|
||||
"SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE": true,
|
||||
"SPI_FLASH_ERASE_YIELD_DURATION_MS": 20,
|
||||
"SPI_FLASH_ERASE_YIELD_TICKS": 1,
|
||||
"SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND": false,
|
||||
"SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND": false,
|
||||
"SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST": false,
|
||||
"SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM": true,
|
||||
"SPI_FLASH_ROM_DRIVER_PATCH": true,
|
||||
"SPI_FLASH_ROM_IMPL": false,
|
||||
"SPI_FLASH_SIZE_OVERRIDE": false,
|
||||
"SPI_FLASH_SUPPORT_BOYA_CHIP": true,
|
||||
"SPI_FLASH_SUPPORT_GD_CHIP": true,
|
||||
"SPI_FLASH_SUPPORT_ISSI_CHIP": true,
|
||||
"SPI_FLASH_SUPPORT_MXIC_CHIP": true,
|
||||
"SPI_FLASH_SUPPORT_TH_CHIP": true,
|
||||
"SPI_FLASH_SUPPORT_WINBOND_CHIP": true,
|
||||
"SPI_FLASH_SUSPEND_TSUS_VAL_US": 50,
|
||||
"SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED": true,
|
||||
"SPI_FLASH_VERIFY_WRITE": false,
|
||||
"SPI_FLASH_WRITE_CHUNK_SIZE": 8192,
|
||||
"SPI_FLASH_YIELD_DURING_ERASE": true,
|
||||
"XTAL_FREQ": 40,
|
||||
"XTAL_FREQ_40": true
|
||||
}
|
||||
Reference in New Issue
Block a user