169 lines
5.8 KiB
C
169 lines
5.8 KiB
C
/*
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* avrdude - A Downloader/Uploader for AVR device programmers
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* Copyright (C) 2005 Joerg Wunsch <j@uriah.heep.sax.de>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* $Id$ */
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/*
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* JTAG ICE mkI definitions
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*/
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/* ICE command codes */
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/* 0x20 Get Synch [Resp_OK] */
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#define CMD_GET_SYNC ' '
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/* 0x31 Single Step [Sync_CRC/EOP] [Resp_OK] */
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/* 0x32 Read PC [Sync_CRC/EOP] [Resp_OK] [program counter]
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* [Resp_OK] */
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/* 0x33 Write PC [program counter] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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/* 0xA2 Firmware Upgrade [upgrade string] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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/* 0xA0 Set Device Descriptor [device info] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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#define CMD_SET_DEVICE_DESCRIPTOR 0xA0
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/* 0x42 Set Parameter [parameter] [setting] [Sync_CRC/EOP] [Resp_OK]
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* [Resp_OK] */
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#define CMD_SET_PARAM 'B'
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/* 0x46 Forced Stop [Sync_CRC/EOP] [Resp_OK] [checksum][program
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* counter] [Resp_OK] */
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#define CMD_STOP 'F'
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/* 0x47 Go [Sync_CRC/EOP] [Resp_OK] */
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#define CMD_GO 'G'
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/* 0x52 Read Memory [memory type] [word count] [start address]
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* [Sync_CRC/EOP] [Resp_OK] [word 0] ... [word n] [checksum]
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* [Resp_OK] */
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#define CMD_READ_MEM 'R'
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/* 0x53 Get Sign On [Sync_CRC/EOP] [Resp_OK] ["AVRNOCD"] [Resp_OK] */
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#define CMD_GET_SIGNON 'S'
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/* 0XA1 Erase Page spm [address] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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/* 0x57 Write Memory [memory type] [word count] [start address]
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* [Sync_CRC/EOP] [Resp_OK] [Cmd_DATA] [word 0] ... [word n] */
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#define CMD_WRITE_MEM 'W'
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/* Second half of write memory: the data command. Undocumented. */
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#define CMD_DATA 'h'
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/* 0x64 Get Debug Info [Sync_CRC/EOP] [Resp_OK] [0x00] [Resp_OK] */
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/* 0x71 Get Parameter [parameter] [Sync_CRC/EOP] [Resp_OK] [setting]
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* [Resp_OK] */
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#define CMD_GET_PARAM 'q'
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/* 0x78 Reset [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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#define CMD_RESET 'x'
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/* 0xA3 Enter Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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#define CMD_ENTER_PROGMODE 0xa3
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/* 0xA4 Leave Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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#define CMD_LEAVE_PROGMODE 0xa4
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/* 0xA5 Chip Erase [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */
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#define CMD_CHIP_ERASE 0xa5
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/* ICE responses */
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#define RESP_OK 'A'
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#define RESP_BREAK 'B'
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#define RESP_INFO 'G'
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#define RESP_FAILED 'F'
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#define RESP_SYNC_ERROR 'E'
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#define RESP_SLEEP 'H'
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#define RESP_POWER 'I'
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#define PARM_BITRATE 'b'
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#define PARM_SW_VERSION 0x7b
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#define PARM_HW_VERSION 0x7a
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#define PARM_IREG_HIGH 0x81
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#define PARM_IREG_LOW 0x82
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#define PARM_OCD_VTARGET 0x84
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#define PARM_OCD_BREAK_CAUSE 0x85
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#define PARM_CLOCK 0x86
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#define PARM_EXTERNAL_RESET 0x8b
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#define PARM_FLASH_PAGESIZE_LOW 0x88
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#define PARM_FLASH_PAGESIZE_HIGH 0x89
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#define PARM_EEPROM_PAGESIZE 0x8a
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#define PARM_TIMERS_RUNNING 0xa0
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#define PARM_BP_FLOW 0xa1
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#define PARM_BP_X_HIGH 0xa2
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#define PARM_BP_X_LOW 0xa3
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#define PARM_BP_Y_HIGH 0xa4
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#define PARM_BP_Y_LOW 0xa5
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#define PARM_BP_MODE 0xa6
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#define PARM_JTAGID_BYTE0 0xa7
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#define PARM_JTAGID_BYTE1 0xa8
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#define PARM_JTAGID_BYTE2 0xa9
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#define PARM_JTAGID_BYTE3 0xaa
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#define PARM_UNITS_BEFORE 0xab
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#define PARM_UNITS_AFTER 0xac
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#define PARM_BIT_BEFORE 0xad
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#define PARM_BIT_AFTER 0xae
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#define PARM_PSB0_LOW 0xaf
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#define PARM_PSBO_HIGH 0xb0
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#define PARM_PSB1_LOW 0xb1
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#define PARM_PSB1_HIGH 0xb2
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#define PARM_MCU_MODE 0xb3
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#define JTAG_BITRATE_1_MHz 0xff
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#define JTAG_BITRATE_500_kHz 0xfe
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#define JTAG_BITRATE_250_kHz 0xfd
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#define JTAG_BITRATE_125_kHz 0xfb
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/* memory types for CMND_{READ,WRITE}_MEMORY */
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#define MTYPE_IO_SHADOW 0x30 /* cached IO registers? */
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#define MTYPE_SRAM 0x20 /* target's SRAM or [ext.] IO registers */
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#define MTYPE_EEPROM 0x22 /* EEPROM, what way? */
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#define MTYPE_EVENT 0x60 /* ICE event memory */
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#define MTYPE_SPM 0xA0 /* flash through LPM/SPM */
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#define MTYPE_FLASH_PAGE 0xB0 /* flash in programming mode */
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#define MTYPE_EEPROM_PAGE 0xB1 /* EEPROM in programming mode */
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#define MTYPE_FUSE_BITS 0xB2 /* fuse bits in programming mode */
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#define MTYPE_LOCK_BITS 0xB3 /* lock bits in programming mode */
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#define MTYPE_SIGN_JTAG 0xB4 /* signature in programming mode */
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#define MTYPE_OSCCAL_BYTE 0xB5 /* osccal cells in programming mode */
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struct device_descriptor
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{
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unsigned char ucReadIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucReadIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucReadExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucWriteExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucReadIOExtShadow[20]; /*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucWriteIOExtShadow[20];/*LSB = IOloc 96, MSB = IOloc255 */
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unsigned char ucIDRAddress; /*IDR address */
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unsigned char ucSPMCRAddress; /*SPMCR Register address and dW BasePC */
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unsigned char ucRAMPZAddress; /*RAMPZ Register address in SRAM I/O */
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/*space */
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unsigned char uiFlashPageSize[2]; /*Device Flash Page Size, Size = */
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/*2 exp ucFlashPageSize */
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unsigned char ucEepromPageSize; /*Device Eeprom Page Size in bytes */
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unsigned char ulBootAddress[4]; /*Device Boot Loader Start Address */
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unsigned char uiUpperExtIOLoc; /*Topmost (last) extended I/O */
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/*location, 0 if no external I/O */
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};
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