761 lines
26 KiB
C
761 lines
26 KiB
C
/*
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* avrdude - A Downloader/Uploader for AVR device programmers
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* Copyright (C) 2022 Stefan Rueger <stefan.rueger@urclocks.c>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* $Id$ */
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#include "ac_cfg.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <string.h>
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#include <sys/time.h>
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#include <time.h>
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#include "avrdude.h"
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#include "libavrdude.h"
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#include "avrintel.h"
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/*
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* Provides an API for cached bytewise access
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*
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* int avr_read_byte_cached(const PROGRAMMER *pgm, const AVRPART *p, const
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* AVRMEM *mem, unsigned long addr, unsigned char *value);
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*
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* int avr_write_byte_cached(const PROGRAMMER *pgm, const AVRPART *p, const
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* AVRMEM *mem, unsigned long addr, unsigned char data);
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*
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* int avr_flush_cache(const PROGRAMMER *pgm, const AVRPART *p);
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*
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* int avr_chip_erase_cached(const PROGRAMMER *pgm, const AVRPART *p);
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*
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* int avr_page_erase_cached(const PROGRAMMER *pgm, const AVRPART *p, const
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* AVRMEM *mem, unsigned int baseaddr);
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*
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* int avr_reset_cache(const PROGRAMMER *pgm, const AVRPART *p);
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*
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* avr_read_byte_cached() and avr_write_byte_cached() use a cache if paged
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* routines are available and if the device memory is EEPROM or flash,
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* otherwise they fall back to pgm->read_byte() and pgm->write_byte(),
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* respectively. Bytewise cached read always gets its data from the cache,
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* possibly after reading a page from the device memory. Bytewise cached
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* write with an address in memory range only ever modifies the cache. Any
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* modifications are written to the device after calling avr_flush_cache() or
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* when attempting to read or write from a location outside the address range
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* of the device memory.
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*
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* avr_flush_cache() synchronises pending writes to EEPROM and flash with the
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* device. With some programmer and part combinations, flash (and sometimes
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* EEPROM, too) looks like a NOR memory, ie, one can only write 0 bits, not 1
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* bits. When this is detected, either page erase is deployed (eg, with parts
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* that have PDI/UPDI interfaces), or if that is not available, both EEPROM
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* and flash caches are fully read in, a pgm->chip_erase() command is issued
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* and both EEPROM and flash are written back to the device. Hence, it can
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* take minutes to ensure that a single previously cleared bit is set and,
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* therefore, this routine should be called sparingly.
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*
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* avr_chip_erase_cached() erases the chip and discards pending writes() to
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* flash or EEPROM. It presets the flash cache to all 0xff alleviating the
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* need to read from the device flash. However, if the programmer serves
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* bootloaders (pgm->prog_modes & PM_SPM) then the flash cache is reset
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* instead, necessitating flash memory be fetched from the device on first
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* read; the reason for this is that bootloaders emulate chip erase and they
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* won't overwrite themselves (some bootloaders, eg, optiboot ignore chip
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* erase commands) making it truly unknowable what the flash contents on
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* device is after a chip erase.
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*
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* For EEPROM avr_chip_erase_cached() concludes that it has been deleted if a
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* previously cached EEPROM page that contained cleared bits now no longer
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* has these clear bits on the device. Only with this evidence is the EEPROM
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* cache preset to all 0xff otherwise the cache discards all pending writes
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* to EEPROM and is left unchanged otherwise.
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*
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* The avr_page_erase_cached() function erases a page and synchronises it
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* with the cache.
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*
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* Finally, avr_reset_cache() resets the cache without synchronising pending
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* writes() to the device.
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*
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* This file also holds the following utility functions
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*
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* // Does the programmer/memory combo have paged memory access?
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* int avr_has_paged_access(const PROGRAMMER *pgm, const AVRMEM *mem);
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*
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* // Read the page containing addr from the device into buf
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* int avr_read_page_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, unsigned char *buf);
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*
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* // Write the data page to the device into the page containing addr
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* int avr_write_page_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, unsigned char *data);
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*
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* // Could memory region s1 be the result of a NOR-memory copy of s3 onto s2?
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* int avr_is_and(const unsigned char *s1, const unsigned char *s2, const unsigned char *s3, size_t n);
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*
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*/
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/*
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* Paged access?
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* - Programmer must have paged routines
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* - Memory has positive page size, which is a power of two
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* - Memory has positive size, which is a multiple of the page size
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* - Memory is flash type or eeprom type
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*
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* Note that in this definition the page size can be 1
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*/
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int avr_has_paged_access(const PROGRAMMER *pgm, const AVRMEM *mem) {
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return pgm->paged_load && pgm->paged_write &&
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mem->page_size > 0 && (mem->page_size & (mem->page_size-1)) == 0 &&
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mem->size > 0 && mem->size % mem->page_size == 0 &&
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(avr_mem_is_flash_type(mem) || avr_mem_is_eeprom_type(mem));
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}
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#define fallback_read_byte (pgm->read_byte != avr_read_byte_cached? pgm->read_byte: avr_read_byte_default)
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#define fallback_write_byte (pgm->write_byte != avr_write_byte_cached? pgm->write_byte: avr_write_byte_default)
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/*
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* Read the page containing addr from the device into buf
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* - Caller to ensure buf has mem->page_size bytes
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* - Part memory buffer mem is unaffected by this (though temporarily changed)
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* - Uses read_byte() if memory page size is one, otherwise paged_load()
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* - Fall back to bytewise read if paged_load() returned an error
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* - On failure returns a negative value, on success a non-negative value, which is either
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* + The number of bytes read by pgm->paged_load() if that succeeded
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* + LIBAVRDUDE_SUCCESS (0) if the fallback of bytewise read succeeded
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*/
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int avr_read_page_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, unsigned char *buf) {
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if(!avr_has_paged_access(pgm, mem) || addr < 0 || addr >= mem->size)
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return LIBAVRDUDE_GENERAL_FAILURE;
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int rc, pgsize = mem->page_size, base = addr & ~(pgsize-1);
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unsigned char *pagecopy = cfg_malloc("avr_read_page_default()", pgsize);
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if(pgsize == 1)
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return fallback_read_byte(pgm, p, mem, addr, buf);
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memcpy(pagecopy, mem->buf + base, pgsize);
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if((rc = pgm->paged_load(pgm, p, mem, pgsize, base, pgsize)) >= 0)
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memcpy(buf, mem->buf + base, pgsize);
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memcpy(mem->buf + base, pagecopy, pgsize);
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if(rc < 0 && pgm->read_byte != avr_read_byte_cached) {
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rc = LIBAVRDUDE_SUCCESS;
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for(int i=0; i<pgsize; i++) {
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if(pgm->read_byte(pgm, p, mem, base+i, pagecopy+i) < 0) {
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rc = LIBAVRDUDE_GENERAL_FAILURE;
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break;
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}
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}
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if(rc == LIBAVRDUDE_SUCCESS)
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memcpy(buf, pagecopy, pgsize);
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}
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free(pagecopy);
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return rc;
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}
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/*
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* Write the data page to the device into the page containing addr
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* - Caller to provide all mem->page_size bytes incl padding if any
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* - Part memory buffer mem is unaffected by this (though temporarily changed)
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* - Uses write_byte() if memory page size is one, otherwise paged_write()
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*/
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int avr_write_page_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, unsigned char *data) {
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if(!avr_has_paged_access(pgm, mem) || addr < 0 || addr >= mem->size)
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return LIBAVRDUDE_GENERAL_FAILURE;
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int rc, pgsize = mem->page_size, base = addr & ~(pgsize-1);
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unsigned char *pagecopy = cfg_malloc("avr_write_page_default()", pgsize);
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if(pgsize == 1)
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return fallback_write_byte(pgm, p, mem, addr, *data);
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memcpy(pagecopy, mem->buf + base, pgsize);
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memcpy(mem->buf + base, data, pgsize);
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rc = pgm->paged_write(pgm, p, mem, pgsize, base, pgsize);
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memcpy(mem->buf + base, pagecopy, pgsize);
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free(pagecopy);
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return rc;
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}
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// Could memory region s1 be the result of a NOR-memory copy of s3 onto s2?
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int avr_is_and(const unsigned char *s1, const unsigned char *s2, const unsigned char *s3, size_t n) {
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while(n--)
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if(*s1++ != (*s2++ & *s3++))
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return 0;
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return 1;
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}
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static int cacheAddress(int addr, const AVR_Cache *cp, const AVRMEM *mem) {
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int cacheaddr = addr + (int) (mem->offset - cp->offset);
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if(cacheaddr < 0 || cacheaddr >= cp->size) { // Should never happen (unless offsets wrong in avrdude.conf)
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pmsg_error("%s cache address 0x%04x out of range [0, 0x%04x]\n", mem->desc, cacheaddr, cp->size-1);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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if(mem->page_size != cp->page_size) { // Should never happen (unless incompatible page sizes in avrdude.conf)
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pmsg_error("%s page size %d incompatible with cache page size %d\n", mem->desc, mem->page_size, cp->page_size);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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return cacheaddr;
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}
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static int loadCachePage(AVR_Cache *cp, const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, int cacheaddr, int nlOnErr) {
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int pgno = cacheaddr/cp->page_size;
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if(!cp->iscached[pgno]) {
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// Read cached section from device
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int cachebase = cacheaddr & ~(cp->page_size-1);
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if(avr_read_page_default(pgm, p, mem, addr & ~(cp->page_size-1), cp->cont + cachebase) < 0) {
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report_progress(1, -1, NULL);
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if(nlOnErr && quell_progress)
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msg_info("\n");
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pmsg_error("unable to read %s page at addr 0x%04x\n", mem->desc, addr);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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// Copy last read device page, so we can later check for changes
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memcpy(cp->copy + cachebase, cp->cont + cachebase, cp->page_size);
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cp->iscached[pgno] = 1;
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}
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return LIBAVRDUDE_SUCCESS;
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}
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static int initCache(AVR_Cache *cp, const PROGRAMMER *pgm, const AVRPART *p) {
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AVRMEM *basemem = avr_locate_mem(p, cp == pgm->cp_flash? "flash": "eeprom");
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if(!basemem || !avr_has_paged_access(pgm, basemem))
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return LIBAVRDUDE_GENERAL_FAILURE;
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cp->size = basemem->size;
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cp->page_size = basemem->page_size;
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cp->offset = basemem->offset;
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cp->cont = cfg_malloc("initCache()", cp->size);
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cp->copy = cfg_malloc("initCache()", cp->size);
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cp->iscached = cfg_malloc("initCache()", cp->size/cp->page_size);
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if((pgm->prog_modes & PM_SPM) && avr_mem_is_flash_type(basemem)) { // Could be vector bootloader
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// Caching the vector page gives control to the progammer that then can patch the reset vector
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if(loadCachePage(cp, pgm, p, basemem, 0, 0, 0) < 0)
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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return LIBAVRDUDE_SUCCESS;
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}
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static int writeCachePage(AVR_Cache *cp, const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int base, int nlOnErr) {
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// Write modified page cont to device; if unsuccessful try bytewise access
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if(avr_write_page_default(pgm, p, mem, base, cp->cont + base) < 0) {
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if(pgm->read_byte != avr_read_byte_cached && pgm->write_byte != avr_write_byte_cached) {
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for(int i=0; i < cp->page_size; i++)
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if(cp->cont[base+i] != cp->copy[base+i])
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if(pgm->write_byte(pgm, p, mem, base+i, cp->cont[base+i]) < 0 ||
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pgm->read_byte(pgm, p, mem, base+i, cp->copy+base+i) < 0) {
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report_progress(1, -1, NULL);
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if(nlOnErr && quell_progress)
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msg_info("\n");
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pmsg_error("%s access error at addr 0x%04x\n", mem->desc, base+i);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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return LIBAVRDUDE_SUCCESS; // Bytewise writes & reads successful
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}
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report_progress(1, -1, NULL);
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if(nlOnErr && quell_progress)
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msg_info("\n");
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pmsg_error("write %s page error at addr 0x%04x\n", mem->desc, base);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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// Read page back from device and update copy to what is on device
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if(avr_read_page_default(pgm, p, mem, base, cp->copy + base) < 0) {
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report_progress(1, -1, NULL);
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if(nlOnErr && quell_progress)
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msg_info("\n");
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pmsg_error("unable to read %s page at addr 0x%04x\n", mem->desc, base);
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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return LIBAVRDUDE_SUCCESS;
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}
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// Does the memory region only haxe 0xff?
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static int _is_all_0xff(const void *p, size_t n) {
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const unsigned char *q = (const unsigned char *) p;
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return n <= 0 || (*q == 0xff && memcmp(q, q+1, n-1) == 0);
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}
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// A coarse guess where any bootloader might start (prob underestimates the start)
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static int guessBootStart(const PROGRAMMER *pgm, const AVRPART *p) {
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int bootstart = 0;
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const AVR_Cache *cp = pgm->cp_flash;
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if(p->n_boot_sections > 0 && p->boot_section_size > 0)
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bootstart = cp->size - (p->boot_section_size<<(p->n_boot_sections-1));
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if(bootstart <= cp->size/2 || bootstart >= cp->size)
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bootstart = cp->size > 32768? cp->size - 16384: cp->size*3/4;
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return bootstart & ~(cp->page_size-1);
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}
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typedef struct {
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AVRMEM *mem;
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AVR_Cache *cp;
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int isflash, zopaddr, pgerase;
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} CacheDesc_t;
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// Write both EEPROM and flash caches to device and free them
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int avr_flush_cache(const PROGRAMMER *pgm, const AVRPART *p) {
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CacheDesc_t mems[2] = {
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{ avr_locate_mem(p, "flash"), pgm->cp_flash, 1, -1, 0 },
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{ avr_locate_mem(p, "eeprom"), pgm->cp_eeprom, 0, -1, 0 },
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};
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int chpages = 0;
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bool chiperase = 0;
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// Count page changes and find a page that needs a clear bit set
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for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
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AVRMEM *mem = mems[i].mem;
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AVR_Cache *cp = mems[i].cp;
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if(!mem || !cp->cont)
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continue;
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for(int pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size) {
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if(cp->iscached[pgno])
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if(memcmp(cp->copy + n, cp->cont + n, cp->page_size)) {
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chpages++;
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if(mems[i].zopaddr == -1 && !avr_is_and(cp->cont + n, cp->copy + n, cp->cont + n, cp->page_size))
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mems[i].zopaddr = n;
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}
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}
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}
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if(!chpages)
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return LIBAVRDUDE_SUCCESS;
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pmsg_info("synching cache to device ... ");
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fflush(stderr);
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// Check whether page erase needed and working and whether chip erase needed
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for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
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AVRMEM *mem = mems[i].mem;
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AVR_Cache *cp = mems[i].cp;
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if(!mem)
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continue;
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if(!cp->cont) // Ensure cache is initialised from now on
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if(initCache(cp, pgm, p) < 0) {
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if(quell_progress)
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msg_info("\n");
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pmsg_error("unable to initialise the cache\n");
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return LIBAVRDUDE_GENERAL_FAILURE;
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}
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if(chiperase || mems[i].zopaddr < 0)
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continue;
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int n=mems[i].zopaddr;
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if(writeCachePage(cp, pgm, p, mem, n, 1) < 0)
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return LIBAVRDUDE_GENERAL_FAILURE;
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// Same? OK, can set cleared bit to one, "normal" memory
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if(!memcmp(cp->copy + n, cp->cont + n, cp->page_size)) {
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chpages--;
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continue;
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}
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// Probably NOR memory, check out page erase
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if(pgm->page_erase && pgm->page_erase(pgm, p, mem, n) >= 0) {
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if(writeCachePage(cp, pgm, p, mem, n, 1) < 0)
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return LIBAVRDUDE_GENERAL_FAILURE;
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// Worked OK? Can use page erase on this memory
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if(!memcmp(cp->copy + n, cp->cont + n, cp->page_size)) {
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mems[i].pgerase = 1;
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chpages--;
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continue;
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}
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}
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chiperase = 1;
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}
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if(!chpages) {
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msg_info("done\n");
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return LIBAVRDUDE_SUCCESS;
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}
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if(chiperase) {
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if(quell_progress) {
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msg_info("reading/chip erase/writing cycle needed ... ");
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fflush(stderr);
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}
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int nrd = 0;
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// Count read operations needed
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for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
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AVRMEM *mem = mems[i].mem;
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AVR_Cache *cp = mems[i].cp;
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if(!mem)
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continue;
|
|
|
|
for(int pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size)
|
|
if(!cp->iscached[pgno])
|
|
nrd++;
|
|
}
|
|
|
|
report_progress(0, 1, "Reading");
|
|
if(nrd) {
|
|
// Read full flash and EEPROM
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVRMEM *mem = mems[i].mem;
|
|
AVR_Cache *cp = mems[i].cp;
|
|
if(!mem)
|
|
continue;
|
|
|
|
for(int ird = 0, pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size) {
|
|
if(!cp->iscached[pgno]) {
|
|
report_progress(ird++, nrd, NULL);
|
|
if(loadCachePage(cp, pgm, p, mem, n, n, 1) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
report_progress(1, 0, NULL);
|
|
|
|
report_progress(0, 1, "Erasing");
|
|
if(avr_chip_erase(pgm, p) < 0) {
|
|
report_progress(1, -1, NULL);
|
|
if(quell_progress)
|
|
msg_info("\n");
|
|
pmsg_error("chip erase failed\n");
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
|
|
// Update cache copies after chip erase so that writing back is efficient
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVRMEM *mem = mems[i].mem;
|
|
AVR_Cache *cp = mems[i].cp;
|
|
if(!mem)
|
|
continue;
|
|
|
|
if(mems[i].isflash) { // flash
|
|
memset(cp->copy, 0xff, cp->size); // record device memory as erased
|
|
if(pgm->prog_modes & PM_SPM) { // Bootloaders will not overwrite themselves
|
|
// Read back generously estimated bootloader section to avoid verification errors
|
|
int bootstart = guessBootStart(pgm, p);
|
|
int nbo = (cp->size - bootstart)/cp->page_size;
|
|
|
|
for(int ibo = 0, n = bootstart; n < cp->size; n += cp->page_size) {
|
|
report_progress(1+ibo++, nbo+2, NULL);
|
|
if(avr_read_page_default(pgm, p, mem, n, cp->copy + n) < 0) {
|
|
report_progress(1, -1, NULL);
|
|
if(quell_progress)
|
|
msg_info("\n");
|
|
pmsg_error("flash read failed at addr 0x%04x\n", n);
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
}
|
|
}
|
|
} else { // EEPROM
|
|
// Don't know whether chip erase has zapped EEPROM
|
|
for(int n = 0; n < cp->size; n += cp->page_size) {
|
|
if(!_is_all_0xff(cp->copy + n, cp->page_size)) { // First page that had EEPROM data
|
|
if(avr_read_page_default(pgm, p, mem, n, cp->copy + n) < 0) {
|
|
report_progress(1, -1, NULL);
|
|
if(quell_progress)
|
|
msg_info("\n");
|
|
pmsg_error("EEPROM read failed at addr 0x%04x\n", n);
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
// EEPROM zapped by chip erase? Set all copy to 0xff
|
|
if(_is_all_0xff(cp->copy + n, cp->page_size))
|
|
memset(cp->copy, 0xff, cp->size);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
report_progress(1, 0, NULL);
|
|
}
|
|
|
|
int nwr = 0;
|
|
// Count number of writes
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVRMEM *mem = mems[i].mem;
|
|
AVR_Cache *cp = mems[i].cp;
|
|
if(!mem)
|
|
continue;
|
|
|
|
for(int pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size)
|
|
if(cp->iscached[pgno] && memcmp(cp->copy + n, cp->cont + n, cp->page_size))
|
|
nwr++;
|
|
}
|
|
|
|
report_progress(0, 1, "Writing");
|
|
if(nwr) {
|
|
// Write all modified pages to the device
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVRMEM *mem = mems[i].mem;
|
|
AVR_Cache *cp = mems[i].cp;
|
|
if(!mem || !cp->cont)
|
|
continue;
|
|
|
|
for(int iwr = 0, pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size) {
|
|
if(cp->iscached[pgno] && memcmp(cp->copy + n, cp->cont + n, cp->page_size)) {
|
|
if(!chiperase && mems[i].pgerase)
|
|
pgm->page_erase(pgm, p, mem, n);
|
|
if(writeCachePage(cp, pgm, p, mem, n, 1) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
if(memcmp(cp->copy + n, cp->cont + n, cp->page_size)) {
|
|
report_progress(1, -1, NULL);
|
|
if(quell_progress)
|
|
msg_info("\n");
|
|
pmsg_error("verification mismatch at %s page addr 0x%04x\n", mem->desc, n);
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
report_progress(iwr++, nwr, NULL);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
report_progress(1, 0, NULL);
|
|
|
|
msg_info(quell_progress? "done\n": "\n");
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
|
|
/*
|
|
* Read byte via a read/write cache
|
|
* - Used if paged routines available and if memory is EEPROM or flash
|
|
* - Otherwise fall back to pgm->read_byte()
|
|
* - Out of memory addr: synchronise cache and, if successful, pretend reading a zero
|
|
* - Cache is automagically created and initialised if needed
|
|
*/
|
|
int avr_read_byte_cached(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem,
|
|
unsigned long addr, unsigned char *value) {
|
|
|
|
// Use pgm->read_byte() if not EEPROM/flash or no paged access
|
|
if(!avr_has_paged_access(pgm, mem))
|
|
return fallback_read_byte(pgm, p, mem, addr, value);
|
|
|
|
// If address is out of range synchronise cache and, if successful, pretend reading a zero
|
|
if(addr >= (unsigned long) mem->size) {
|
|
if(avr_flush_cache(pgm, p) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
*value = 0;
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
AVR_Cache *cp = avr_mem_is_eeprom_type(mem)? pgm->cp_eeprom: pgm->cp_flash;
|
|
|
|
if(!cp->cont) // Init cache if needed
|
|
if(initCache(cp, pgm, p) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
int cacheaddr = cacheAddress((int) addr, cp, mem);
|
|
if(cacheaddr < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
// Ensure cache page is there
|
|
if(loadCachePage(cp, pgm, p, mem, addr, cacheaddr, 0) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
*value = cp->cont[cacheaddr];
|
|
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
|
|
/*
|
|
* Write byte via a read/write cache
|
|
* - Used if paged routines available and if memory is EEPROM or flash
|
|
* - Otherwise fall back to pgm->write_byte()
|
|
* - Out of memory addr: synchronise cache with device and return whether successful
|
|
* - If programmer indicates a readonly spot, return LIBAVRDUDE_SOFTFAIL
|
|
* - Cache is automagically created and initialised if needed
|
|
*/
|
|
int avr_write_byte_cached(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem,
|
|
unsigned long addr, unsigned char data) {
|
|
|
|
if(pgm->readonly && pgm->readonly(pgm, p, mem, addr))
|
|
return LIBAVRDUDE_SOFTFAIL;
|
|
|
|
// Use pgm->write_byte() if not EEPROM/flash or no paged access
|
|
if(!avr_has_paged_access(pgm, mem))
|
|
return fallback_write_byte(pgm, p, mem, addr, data);
|
|
|
|
// If address is out of range synchronise caches with device and return whether successful
|
|
if(addr >= (unsigned long) mem->size)
|
|
return avr_flush_cache(pgm, p);
|
|
|
|
AVR_Cache *cp = avr_mem_is_eeprom_type(mem)? pgm->cp_eeprom: pgm->cp_flash;
|
|
|
|
if(!cp->cont) // Init cache if needed
|
|
if(initCache(cp, pgm, p) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
int cacheaddr = cacheAddress((int) addr, cp, mem);
|
|
if(cacheaddr < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
// Ensure cache page is there
|
|
if(loadCachePage(cp, pgm, p, mem, addr, cacheaddr, 0) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
cp->cont[cacheaddr] = data;
|
|
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
|
|
// Erase the chip and set the cache accordingly
|
|
int avr_chip_erase_cached(const PROGRAMMER *pgm, const AVRPART *p) {
|
|
CacheDesc_t mems[2] = {
|
|
{ avr_locate_mem(p, "flash"), pgm->cp_flash, 1, -1, 0 },
|
|
{ avr_locate_mem(p, "eeprom"), pgm->cp_eeprom, 0, -1, 0 },
|
|
};
|
|
int rc;
|
|
|
|
if((rc = pgm->chip_erase(pgm, p)) < 0)
|
|
return rc;
|
|
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVRMEM *mem = mems[i].mem;
|
|
AVR_Cache *cp = mems[i].cp;
|
|
|
|
if(!mem || !avr_has_paged_access(pgm, mem))
|
|
continue;
|
|
|
|
if(!cp->cont) // Init cache if needed
|
|
if(initCache(cp, pgm, p) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
if(mems[i].isflash) { // flash
|
|
if(pgm->prog_modes & PM_SPM) { // reset cache to unknown
|
|
memset(cp->iscached, 0, cp->size/cp->page_size);
|
|
} else { // preset all pages as erased
|
|
memset(cp->copy, 0xff, cp->size);
|
|
memset(cp->cont, 0xff, cp->size);
|
|
memset(cp->iscached, 1, cp->size/cp->page_size);
|
|
}
|
|
} else { // EEPROM: test whether cached pages were zapped
|
|
bool erasedee = 0;
|
|
for(int pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size) {
|
|
if(cp->iscached[pgno]) {
|
|
if(!_is_all_0xff(cp->copy + n, cp->page_size)) { // Page has EEPROM data?
|
|
if(avr_read_page_default(pgm, p, mem, n, cp->copy + n) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
erasedee = _is_all_0xff(cp->copy + n, cp->page_size);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if(erasedee) { // EEPROM was erased, set cache correspondingly
|
|
memset(cp->copy, 0xff, cp->size);
|
|
memset(cp->cont, 0xff, cp->size);
|
|
memset(cp->iscached, 1, cp->size/cp->page_size);
|
|
} else { // discard previous writes, but leave cache
|
|
for(int pgno = 0, n = 0; n < cp->size; pgno++, n += cp->page_size)
|
|
if(cp->iscached[pgno])
|
|
memcpy(cp->cont + n, cp->copy + n, cp->page_size);
|
|
}
|
|
}
|
|
}
|
|
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
|
|
// Erase a page and synchronise it with the cache
|
|
int avr_page_erase_cached(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem,
|
|
unsigned int uaddr) {
|
|
|
|
int addr = uaddr;
|
|
|
|
if(!avr_has_paged_access(pgm, mem) || addr < 0 || addr >= mem->size)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
if(mem->page_size == 1) {
|
|
if(fallback_write_byte(pgm, p, mem, uaddr, 0xff) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
} else {
|
|
if(!pgm->page_erase || pgm->page_erase(pgm, p, mem, uaddr) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
}
|
|
|
|
AVR_Cache *cp = avr_mem_is_eeprom_type(mem)? pgm->cp_eeprom: pgm->cp_flash;
|
|
|
|
if(!cp->cont) // Init cache if needed
|
|
if(initCache(cp, pgm, p) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
int cacheaddr = cacheAddress(addr, cp, mem);
|
|
if(cacheaddr < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
// Invalidate this cache page and read back, ie, we don't trust the page_erase() routine
|
|
cp->iscached[cacheaddr/cp->page_size] = 0;
|
|
|
|
// Reload cache page
|
|
if(loadCachePage(cp, pgm, p, mem, (int) addr, cacheaddr, 0) < 0)
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
if(!_is_all_0xff(cp->cont + (cacheaddr & ~(cp->page_size-1)), cp->page_size))
|
|
return LIBAVRDUDE_GENERAL_FAILURE;
|
|
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|
|
|
|
|
|
// Free cache(s) discarding any pending writes
|
|
int avr_reset_cache(const PROGRAMMER *pgm, const AVRPART *p_unused) {
|
|
AVR_Cache *mems[2] = { pgm->cp_flash, pgm->cp_eeprom, };
|
|
|
|
for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) {
|
|
AVR_Cache *cp = mems[i];
|
|
if(cp->cont)
|
|
free(cp->cont);
|
|
if(cp->copy)
|
|
free(cp->copy);
|
|
if(cp->iscached)
|
|
free(cp->iscached);
|
|
memset(cp, 0, sizeof*cp);
|
|
}
|
|
|
|
return LIBAVRDUDE_SUCCESS;
|
|
}
|