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Add support for the JTAG ICE mkII in ISP mode.

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* avrdude.conf.in (jtag2isp): New programmer entry.
* config_gram.y: Add K_JTAG_MKII_ISP.
* jtagmkII.c: Restructure and export some more functions.
* jtagmkII.h: Declare exported functions.
* jtagmkII_private.h: Prepare file to be included in stk500v2.c.
* lexer.l: Add jtagmkii_isp token.
* stk500v2.c: Implement glue to jtagmkII.c.
* stk500v2.h: Declare stk500v2_jtagmkII_initpgm().
* avrdude.1: Document the new programmer support.
* doc/avrdude.texi: (Ditto.)


git-svn-id: svn://svn.savannah.nongnu.org/avrdude/trunk/avrdude@643 81a1dc3b-b13d-400b-aceb-764788c761c2
This commit is contained in:
joerg_wunsch
2006-09-06 20:06:07 +00:00
parent 26952bf8f0
commit f8796c29cc
12 changed files with 391 additions and 68 deletions
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9
avrdude.1
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@@ -19,7 +19,7 @@
.\"
.\" $Id$
.\"
.Dd DATE August 16, 2006
.Dd DATE September 6, 2006
.Os
.Dt AVRDUDE 1
.Sh NAME
@@ -57,7 +57,7 @@ microcontrollers.
.Nm Avrdude
supports Atmel's STK500 programmer,
Atmel's AVRISP and AVRISP mkII devices,
Atmel's JTAG ICE (both mkI and mkII),
Atmel's JTAG ICE (both mkI and mkII, the latter also in ISP mode),
programmers complying to AppNote AVR910 and AVR109 (including the Butterfly),
as well as a simple hard-wired
programmer connected directly to a
@@ -111,6 +111,7 @@ supported on a serial port.
.Pp
Atmel's JTAG ICE (both mkI and mkII) is supported as well to up- or download memory
areas from/to an AVR target (no support for on-chip debugging).
For the JTAG ICE mkII, both JTAG and ISP mode are supported.
.Pp
Input files can be provided, and output files can be written in
different file formats, such as raw binary files containing the data
@@ -219,7 +220,7 @@ and bit-bang programmers.
Override the RS-232 connection baud rate specified in the respective
programmer's entry of the configuration file.
.It Fl B Ar bitclock
Specify the bit clock period for the JTAG interface (JTAG ICE only).
Specify the bit clock period for the JTAG interface or the ISP clock (JTAG ICE only).
The value is a floating-point number in microseconds.
The default value of the JTAG ICE results in about 1 microsecond bit
clock period, suitable for target MCUs running at 4 MHz clock and
@@ -629,6 +630,8 @@ microseconds.
Note that unlike STK500 settings, this setting will be reverted to
its default value (approximately 1 microsecond) when the programming
software signs off from the JTAG ICE.
This parameter can also be used on the JTAG ICE mkII to specify the
ISP clock period when operating the ICE in ISP mode.
.It Ar parms
.Em STK500 programmer only:
Display the current voltage and master oscillator parameters.