diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index dbe23e64..851942ed 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -215,6 +215,7 @@ jobs: -D CMAKE_C_FLAGS_RELWITHDEBINFO="/MT /GL /Zi /O2 /Ob1 /DNDEBUG" -D CMAKE_CXX_FLAGS_RELWITHDEBINFO="/MT /GL /Zi /O2 /Ob1 /DNDEBUG" -D CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO="/DEBUG /INCREMENTAL:NO /LTCG /OPT:REF /OPT:ICF" + -D HAVE_LIBREADLINE=HAVE_LIBREADLINE-NOTFOUND -D CMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -D USE_EXTERNAL=1 -B build diff --git a/src/avr.c b/src/avr.c index 010e65c3..370f09fb 100644 --- a/src/avr.c +++ b/src/avr.c @@ -340,6 +340,10 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con if (v != NULL) vmem = avr_locate_mem(v, mem->desc); + + if(mem->size < 0) // Sanity check + return -1; + /* * start with all 0xff */ @@ -355,7 +359,7 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con avr_tpi_setup_rw(pgm, mem, 0, TPI_NVMCMD_NO_OPERATION); /* load bytes */ - for (lastaddr = i = 0; i < mem->size; i++) { + for (lastaddr = i = 0; i < (unsigned long) mem->size; i++) { if (vmem == NULL || (vmem->tags[i] & TAG_ALLOCATED) != 0) { @@ -389,7 +393,7 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con /* quickly scan number of pages to be written to first */ for (pageaddr = 0, npages = 0; - pageaddr < mem->size; + pageaddr < (unsigned int) mem->size; pageaddr += mem->page_size) { /* check whether this page must be read */ for (i = pageaddr; @@ -406,7 +410,7 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con } for (pageaddr = 0, failure = 0, nread = 0; - !failure && pageaddr < mem->size; + !failure && pageaddr < (unsigned int) mem->size; pageaddr += mem->page_size) { /* check whether this page must be read */ for (i = pageaddr, need_read = 0; @@ -443,7 +447,7 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con } } - for (i=0; i < mem->size; i++) { + for (i=0; i < (unsigned long) mem->size; i++) { if (vmem == NULL || (vmem->tags[i] & TAG_ALLOCATED) != 0) { rc = pgm->read_byte(pgm, p, mem, i, mem->buf + i); if (rc != LIBAVRDUDE_SUCCESS) { @@ -467,9 +471,9 @@ int avr_read_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, con /* * write a page data at the specified address */ -int avr_write_page(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, - unsigned long addr) -{ +int avr_write_page(const PROGRAMMER *pgm, const AVRPART *p_unused, const AVRMEM *mem, + unsigned long addr) { + unsigned char cmd[4]; unsigned char res[4]; OPCODE * wp, * lext; @@ -714,8 +718,8 @@ int avr_write_byte_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM } gettimeofday (&tv, NULL); prog_time = (tv.tv_sec * 1000000) + tv.tv_usec; - } while ((r != data) && - ((prog_time-start_time) < mem->max_write_delay)); + } while (r != data && mem->max_write_delay >= 0 && + prog_time - start_time < (unsigned long) mem->max_write_delay); } /* @@ -824,12 +828,13 @@ int avr_write_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, int wsize = m->size; if (size < wsize) { wsize = size; - } - else if (size > wsize) { + } else if (size > wsize) { pmsg_warning("%d bytes requested, but memory region is only %d bytes\n", size, wsize); imsg_warning("Only %d bytes will actually be written\n", wsize); } + if(wsize <= 0) + return wsize; if ((p->prog_modes & PM_TPI) && m->page_size > 1 && pgm->cmd_tpi) { unsigned int chunk; /* number of words for each write command */ @@ -860,7 +865,7 @@ int avr_write_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, int wsize = (wsize+chunk-1) / chunk * chunk; /* write words in chunks, low byte first */ - for (lastaddr = i = 0; i < wsize; i += chunk) { + for (lastaddr = i = 0; i < (unsigned int) wsize; i += chunk) { /* check that at least one byte in this chunk is allocated */ for (writeable_chunk = j = 0; !writeable_chunk && j < chunk; j++) { writeable_chunk = m->tags[i+j] & TAG_ALLOCATED; @@ -897,50 +902,114 @@ int avr_write_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, int /* * the programmer supports a paged mode write */ - int need_write, failure; + int need_write, failure, nset; unsigned int pageaddr; unsigned int npages, nwritten; - /* quickly scan number of pages to be written to first */ - for (pageaddr = 0, npages = 0; - pageaddr < wsize; - pageaddr += m->page_size) { - /* check whether this page must be written to */ - for (i = pageaddr; - i < pageaddr + m->page_size; - i++) - if ((m->tags[i] & TAG_ALLOCATED) != 0) { + /* + * Not all paged memory looks like NOR memory to AVRDUDE, particularly + * - EEPROM + * - when talking to a bootloader + * - handling write via a part-programmer combo that can do page erase + * + * Hence, read in from the chip all pages with holes to fill them in. The + * small cost of doing so is outweighed by the benefit of not potentially + * overwriting bytes with 0xff outside the input file. + * + * Also consider that the effective page size for *SPM* erasing of parts + * can be 4 times the page size for SPM writing (eg, ATtiny1634). Thus + * ensure the holes cover the effective page size for SPM programming. + * Benefits -c arduino with input files with holes on 4-page-erase parts. + */ + + AVRMEM *cm = avr_dup_mem(m); + + // Establish and sanity check effective page size + int pgsize = (pgm->prog_modes & PM_SPM) && p->n_page_erase > 0? + p->n_page_erase*cm->page_size: cm->page_size; + if((pgsize & (pgsize-1)) || pgsize < 1) { + pmsg_error("effective page size %d implausible\n", pgsize); + avr_free_mem(cm); + return -1; + } + + uint8_t *spc = cfg_malloc(__func__, cm->page_size); + + // Set cwsize as rounded-up wsize + int cwsize = (wsize + pgsize-1)/pgsize*pgsize; + + for(pageaddr = 0; pageaddr < (unsigned int) cwsize; pageaddr += pgsize) { + for(i = pageaddr, nset = 0; i < pageaddr + pgsize; i++) + if(cm->tags[i] & TAG_ALLOCATED) + nset++; + + if(nset && nset != pgsize) { // Effective page has holes + for(int np=0; np < pgsize/cm->page_size; np++) { // page by page + unsigned int beg = pageaddr + np*cm->page_size; + unsigned int end = beg + cm->page_size; + + for(i = beg; i < end; i++) + if(!(cm->tags[i] & TAG_ALLOCATED)) + break; + + if(i >= end) // Memory page has no holes + continue; + + // Read flash contents to separate memory spc and fill in holes + if(avr_read_page_default(pgm, p, cm, beg, spc) >= 0) { + pmsg_notice2("padding %s [0x%04x, 0x%04x]\n", cm->desc, beg, end-1); + for(i = beg; i < end; i++) + if(!(cm->tags[i] & TAG_ALLOCATED)) { + cm->tags[i] |= TAG_ALLOCATED; + cm->buf[i] = spc[i-beg]; + } + } else { + pmsg_notice2("cannot read %s [0x%04x, 0x%04x] to pad page\n", + cm->desc, beg, end-1); + } + } + } + } + + // Quickly scan number of pages to be written to + for(pageaddr = 0, npages = 0; pageaddr < (unsigned int) cwsize; pageaddr += cm->page_size) { + for(i = pageaddr; i < pageaddr + cm->page_size; i++) + if(cm->tags[i] & TAG_ALLOCATED) { npages++; break; } } for (pageaddr = 0, failure = 0, nwritten = 0; - !failure && pageaddr < wsize; - pageaddr += m->page_size) { - /* check whether this page must be written to */ - for (i = pageaddr, need_write = 0; - i < pageaddr + m->page_size; - i++) - if ((m->tags[i] & TAG_ALLOCATED) != 0) { + !failure && pageaddr < (unsigned int) cwsize; + pageaddr += cm->page_size) { + + // Check whether this page must be written to + for (i = pageaddr, need_write = 0; i < pageaddr + cm->page_size; i++) + if ((cm->tags[i] & TAG_ALLOCATED) != 0) { need_write = 1; break; } + if (need_write) { rc = 0; if (auto_erase) - rc = pgm->page_erase(pgm, p, m, pageaddr); + rc = pgm->page_erase(pgm, p, cm, pageaddr); if (rc >= 0) - rc = pgm->paged_write(pgm, p, m, m->page_size, pageaddr, m->page_size); + rc = pgm->paged_write(pgm, p, cm, cm->page_size, pageaddr, cm->page_size); if (rc < 0) /* paged write failed, fall back to byte-at-a-time write below */ failure = 1; } else { - pmsg_debug("avr_write_mem(): skipping page %u: no interesting data\n", pageaddr / m->page_size); + pmsg_debug("avr_write_mem(): skipping page %u: no interesting data\n", pageaddr / cm->page_size); } nwritten++; report_progress(nwritten, npages, NULL); } + + avr_free_mem(cm); + free(spc); + if (!failure) return wsize; /* else: fall back to byte-at-a-time write, for historical reasons */ @@ -954,7 +1023,7 @@ int avr_write_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, int page_tainted = 0; flush_page = 0; - for (i=0; ibuf[i]; report_progress(i, wsize, NULL); @@ -978,8 +1047,8 @@ int avr_write_mem(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, int } else { page_tainted |= do_write; } - if (i % m->page_size == m->page_size - 1 || - i == wsize - 1) { + if (i % m->page_size == (unsigned int) m->page_size - 1 || + i == (unsigned int) wsize - 1) { /* last byte this page */ flush_page = page_tainted; newpage = 1; diff --git a/src/avrcache.c b/src/avrcache.c index cca15483..638ac46f 100644 --- a/src/avrcache.c +++ b/src/avrcache.c @@ -135,6 +135,9 @@ int avr_has_paged_access(const PROGRAMMER *pgm, const AVRMEM *mem) { * - Part memory buffer mem is unaffected by this (though temporarily changed) * - Uses read_byte() if memory page size is one, otherwise paged_load() * - Fall back to bytewise read if paged_load() returned an error + * - On failure returns a negative value, on success a non-negative value, which is either + * + The number of bytes read by pgm->paged_load() if that succeeded + * + LIBAVRDUDE_SUCCESS (0) if the fallback of bytewise read succeeded */ int avr_read_page_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, int addr, unsigned char *buf) { if(!avr_has_paged_access(pgm, mem) || addr < 0 || addr >= mem->size) @@ -643,8 +646,8 @@ int avr_write_byte_cached(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM // Erase the chip and set the cache accordingly int avr_chip_erase_cached(const PROGRAMMER *pgm, const AVRPART *p) { CacheDesc_t mems[2] = { - { avr_locate_mem(p, "flash"), pgm->cp_flash, 1 }, - { avr_locate_mem(p, "eeprom"), pgm->cp_eeprom, 0 }, + { avr_locate_mem(p, "flash"), pgm->cp_flash, 1, -1, 0 }, + { avr_locate_mem(p, "eeprom"), pgm->cp_eeprom, 0, -1, 0 }, }; int rc; @@ -740,7 +743,7 @@ int avr_page_erase_cached(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM // Free cache(s) discarding any pending writes -int avr_reset_cache(const PROGRAMMER *pgm, const AVRPART *p) { +int avr_reset_cache(const PROGRAMMER *pgm, const AVRPART *p_unused) { AVR_Cache *mems[2] = { pgm->cp_flash, pgm->cp_eeprom, }; for(size_t i = 0; i < sizeof mems/sizeof*mems; i++) { diff --git a/src/avrdude.1 b/src/avrdude.1 index c0ab2bba..efdaff5d 100644 --- a/src/avrdude.1 +++ b/src/avrdude.1 @@ -75,10 +75,12 @@ so, for the based programmer, the MCU signals .Ql /RESET , .Ql SCK , -.Ql MISO +.Ql SDI and -.Ql MOSI -need to be connected to the parallel port. Optionally, some otherwise +.Ql SDO +of the AVR's SPI interface need to be connected to the +parallel port; older boards might use the labels MOSI for SDO or MISO for SDI. +Optionally, some otherwise unused output pins of the parallel port can be used to supply power for the MCU part, so it is also possible to construct a passive stand-alone programming device. Some status LEDs indicating the @@ -98,7 +100,7 @@ work at all, or to work abysmally slow. .Pp If you happen to have a Linux system with at least 4 hardware GPIOs available (like almost all embedded Linux boards) you can do without -any additional hardware - just connect them to the MOSI, MISO, RESET +any additional hardware - just connect them to the SDO, SDI, RESET and SCK pins on the AVR and use the linuxgpio programmer type. It bitbangs the lines using the Linux sysfs GPIO interface. Of course, care should be taken about voltage level compatibility. Also, although not strictly @@ -114,7 +116,7 @@ programmer type can be used to directly connect to and program a chip using the built in interfaces on the computer. The requirements to use this type are that an SPI interface is exposed along with one GPIO pin. The GPIO serves as the reset output since the Linux SPI drivers -do not hold slave select down when a transfer is not occurring and thus +do not hold chip select down when a transfer is not occurring and thus it cannot be used as the reset pin. A readily available level translator should be used between the SPI bus/reset GPIO and the chip to avoid potentially damaging the computer's SPI controller in the @@ -217,7 +219,7 @@ has been compiled in .Nm avrdude , the avrftdi device adds support for many programmers using FTDI's 2232C/D/H and 4232H parts running in MPSSE mode, which hard-codes (in the chip) -SCK to bit 1, MOSI to bit 2, and MISO to bit 3. Reset is usually bit 4. +SCK to bit 1, SDO to bit 2, and SDI to bit 3. Reset is usually bit 4. .Pp The Atmel DFU bootloader is supported in both, FLIP protocol version 1 (AT90USB* and ATmega*U* devices), as well as version 2 (Xmega devices). @@ -301,7 +303,7 @@ file. Finally, a ``terminal'' mode is available that allows one to interactively communicate with the MCU, and to display or program individual memory cells. On the STK500 and STK600 programmer, several operational parameters (target supply -voltage, target Aref voltage, master clock) can be examined and changed +voltage, target Aref voltage, programming clock) can be examined and changed from within terminal mode as well. .Ss Options In order to control all the different operation modi, a number of options @@ -959,7 +961,7 @@ can be omitted. .It Ar spi Enter direct SPI mode. The .Em pgmled -pin acts as slave select. +pin acts as chip select. .Em Supported on parallel bitbang programmers, and partially by USBtiny. .It Ar pgm Return to programming mode (from direct SPI mode). @@ -981,7 +983,7 @@ can be selected by the optional argument (either 0 or 1). .Em Supported on the STK500 and STK600 programmer. .It Ar fosc freq Ns Op M Ns \&| Ns k -Set the master oscillator to +Set the programming oscillator to .Ar freq Hz. An optional trailing letter @@ -991,7 +993,7 @@ multiplies by 1E6, a trailing letter by 1E3. .Em Supported on the STK500 and STK600 programmer. .It Ar fosc off -Turn the master oscillator off. +Turn the programming oscillator off. .Em Supported on the STK500 and STK600 programmer. .It Ar sck period .Em STK500 and STK600 programmer: @@ -1009,7 +1011,7 @@ This parameter can also be used on the JTAG ICE mkII, JTAGICE3, and Atmel-ICE to ISP clock period when operating the ICE in ISP mode. .It Ar parms .Em STK500 and STK600 programmer: -Display the current voltage and master oscillator parameters. +Display the current voltage and programming oscillator parameters. .Em JTAG ICE: Display the current target supply voltage and JTAG bit clock rate/period. .Em Other programmers: @@ -1025,8 +1027,8 @@ ll. 2-5 Vcc (optional power supply to MCU) 7 /RESET (to MCU) 8 SCK (to MCU) -9 MOSI (to MCU) -10 MISO (from MCU) +9 SDO (to MCU) +10 SDI (from MCU) 18-25 GND .TE .Ss debugWire limitations @@ -1258,7 +1260,7 @@ Show this help menu and exit .It Ar reset={cs,aux,aux2} The default setup assumes the BusPirate's CS output pin connected to the RESET pin on AVR side. It is however possible to have multiple AVRs -connected to the same BP with MISO, MOSI and SCK lines common for all of them. +connected to the same BP with SDI, SDO and SCK lines common for all of them. In such a case one AVR should have its RESET connected to BusPirate's .Pa CS pin, second AVR's RESET connected to BusPirate's @@ -1371,9 +1373,9 @@ Connection to the PICkit2 programmer: RST - VPP/MCLR (1) VDD - VDD Target (2) -- possibly optional if AVR self powered GND - GND (3) -MISO - PGD (4) +SDI - PGD (4) SCLK - PDC (5) -MOSI - AUX (6) +SDO - AUX (6) .Ed Extended commandline parameters: @@ -1529,7 +1531,7 @@ The USBasp and USBtinyISP drivers do not offer any option to distinguish multipl devices connected simultaneously, so effectively only a single device is supported. .Pp -Slave Select must be externally held low for direct SPI when +Chip Select must be externally held low for direct SPI when using USBtinyISP, and send must be a multiple of four bytes. .Pp The avrftdi driver allows one to select specific devices using any combination of vid,pid diff --git a/src/avrdude.conf.in b/src/avrdude.conf.in index 5d277349..2e04f8e3 100644 --- a/src/avrdude.conf.in +++ b/src/avrdude.conf.in @@ -29,8 +29,8 @@ # buff = [, ... ] ; # pin number(s) # reset = ; # pin number # sck = ; # pin number -# mosi = ; # pin number -# miso = ; # pin number +# sdo = ; # pin number +# sdi = ; # pin number # errled = ; # pin number # rdyled = ; # pin number # pgmled = ; # pin number @@ -72,6 +72,8 @@ # mcuid = ; # unique id in 0..2039 for 8-bit AVRs # n_interrupts = ; # number of interrupts, used for vector bootloaders # n_page_erase = ; # if set, number of pages erased during SPM erase +# n_boot_sections = ; # Number of boot sections +# boot_section_size = ; # Size of (smallest) boot section, if any # hvupdi_variant = ; # numeric -1 (n/a) or 0..2 # devicecode = ; # deprecated, use stk500_devcode # stk500_devcode = ; # numeric @@ -411,8 +413,8 @@ programmer vcc = 2, 3, 4, 5; reset = 7; sck = 8; - mosi = 9; - miso = 10; + sdo = 9; + sdi = 10; ; #------------------------------------------------------------ @@ -427,8 +429,8 @@ programmer buff = 4, 5; reset = 9; sck = 6; - mosi = 7; - miso = 10; + sdo = 7; + sdi = 10; ; #------------------------------------------------------------ @@ -457,8 +459,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = 4; sck = 5; - mosi = 2; - miso = 11; + sdo = 2; + sdi = 11; ; #------------------------------------------------------------ @@ -483,8 +485,8 @@ programmer buff = 6; reset = 7; sck = 8; - mosi = 9; - miso = 10; + sdo = 9; + sdi = 10; errled = 1; rdyled = 14; pgmled = 16; @@ -503,8 +505,8 @@ programmer vcc = 4, 5, 6, 7, 8; reset = 3; sck = 2; - mosi = 9; - miso = 11; + sdo = 9; + sdi = 11; ; #------------------------------------------------------------ @@ -518,8 +520,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = 2; sck = 3; - mosi = 4; - miso = 13; + sdo = 4; + sdi = 13; ; #------------------------------------------------------------ @@ -533,8 +535,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = 4; sck = 3; - mosi = 2; - miso = 10; + sdo = 2; + sdi = 10; ; #------------------------------------------------------------ @@ -548,8 +550,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = 3; sck = 2; - mosi = 1; - miso = 10; + sdo = 1; + sdi = 10; ; #------------------------------------------------------------ @@ -561,7 +563,7 @@ programmer # the programming circuit) but is necessary to switch one of the # buffer lines (trying to add it to the "buff" lines doesn't work in # avrdude versions before 5.5j). -# With this, TMS connects to RESET, TDI to MOSI, TDO to MISO and TCK +# With this, TMS connects to RESET, TDI to SDO, TDO to SDI and TCK # to SCK (plus vcc/gnd of course) programmer @@ -573,8 +575,8 @@ programmer buff = 5; reset = 4; sck = 3; - mosi = 2; - miso = 13; + sdo = 2; + sdi = 13; ; #------------------------------------------------------------ @@ -589,8 +591,8 @@ programmer vcc = 3; reset = 16; sck = 1; - mosi = 2; - miso = 11; + sdo = 2; + sdi = 11; ; #------------------------------------------------------------ @@ -604,8 +606,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = ~6; sck = ~8; - mosi = ~7; - miso = ~10; + sdo = ~7; + sdi = ~10; ; #------------------------------------------------------------ @@ -619,8 +621,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = ~4; sck = 3; - mosi = 2; - miso = 10; + sdo = 2; + sdi = 10; ; #------------------------------------------------------------ @@ -635,8 +637,8 @@ programmer buff = 14; reset = 3; sck = 2; - mosi = 8; - miso = 11; + sdo = 8; + sdi = 11; ; #------------------------------------------------------------ @@ -667,8 +669,8 @@ programmer prog_modes = PM_TPI | PM_ISP; reset = 17; sck = 1; - mosi = 2; - miso = 10; + sdo = 2; + sdi = 10; ; @HAVE_PARPORT_END@ @@ -699,8 +701,8 @@ programmer # prog_modes = PM_ISP; # reset = ?; # sck = ?; -# mosi = ?; -# miso = ?; +# sdo = ?; +# sdi = ?; # ; @HAVE_LINUXGPIO_END@ @@ -801,7 +803,7 @@ programmer # And fill that in here. # # Note that the pin numbers for the main ISP signals (reset, sck, -# mosi, miso) are fixed and cannot be changed, since they must match +# sdo, sdi) are fixed and cannot be changed, since they must match # the way the Multi-Protocol Synchronous Serial Engine (MPSSE) of # these FTDI ICs has been designed. @@ -817,8 +819,8 @@ programmer # ISP-signals - lower ADBUS-Nibble (default) reset = 3; sck = 0; - mosi = 1; - miso = 2; + sdo = 1; + sdi = 2; # LED SIGNALs - higher ADBUS-Nibble # errled = 4; # rdyled = 5; @@ -851,8 +853,8 @@ programmer #ISP-signals reset = 3; sck = 0; - mosi = 1; - miso = 2; + sdo = 1; + sdi = 2; #LED SIGNALs errled = ~11; rdyled = ~14; @@ -891,8 +893,8 @@ programmer # ISP-signals => 20 - Pin connector on JTAGKey reset = 3; # TMS 7 violet sck = 0; # TCK 9 white - mosi = 1; # TDI 5 green - miso = 2; # TDO 13 orange + sdo = 1; # TDI 5 green + sdi = 2; # TDO 13 orange # VTG VREF 1 brown with red tip # GND GND 20 black # The colors are on the 20 pin breakout cable from Amontec @@ -914,8 +916,8 @@ programmer #ISP-signals reset = 3; # AD3 (TMS) sck = 0; # AD0 (TCK) - mosi = 1; # AD1 (TDI) - miso = 2; # AD2 (TDO) + sdo = 1; # AD1 (TDI) + sdi = 2; # AD2 (TDO) ; #------------------------------------------------------------ @@ -923,8 +925,8 @@ programmer #------------------------------------------------------------ # Pin J2-7 (AD0) is SCK -# Pin J2-8 (AD1) is MOSI -# Pin J2-9 (AD2) is MISO +# Pin J2-8 (AD1) is SDO +# Pin J2-9 (AD2) is SDI # Pin J2-10 (AD3) is RESET # Pin J2-6 is GND # Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get @@ -941,8 +943,8 @@ programmer parent "ft232h" #------------------------------------------------------------ # Orange (Pin 2) is SCK -# Yellow (Pin 3) is MOSI -# Green (Pin 4) is MISO +# Yellow (Pin 3) is SDO +# Green (Pin 4) is SDI # Brown (Pin 5) is RESET # Black (Pin 10) is GND # Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get @@ -997,8 +999,8 @@ programmer usbdev = "A"; reset = 3; # TMS 7 sck = 0; # TCK 9 - mosi = 1; # TDI 5 - miso = 2; # TDO 13 + sdo = 1; # TDI 5 + sdi = 2; # TDO 13 ; #------------------------------------------------------------ @@ -1024,8 +1026,8 @@ programmer #ISP-signals - lower ACBUS-Nibble (default) reset = 3; sck = 0; - mosi = 1; - miso = 2; + sdo = 1; + sdi = 2; ; #------------------------------------------------------------ @@ -1046,8 +1048,8 @@ programmer usbvendor = "TIAO"; reset = 3; # TMS 7 sck = 0; # TCK 9 - mosi = 1; # TDI 5 - miso = 2; # TDO 13 + sdo = 1; # TDI 5 + sdi = 2; # TDO 13 ; #------------------------------------------------------------ @@ -1063,7 +1065,7 @@ programmer # KT-LINK JTAG CONN: # 1=Vsense(->EXT13), 19=5V(EXT1->EXT3), 20=GND, 3=TPIRST, 9=TPICLK, 7=TPIDATA. # INTERNALS CONFIGURATION ("~" MEANS ACTIVE LOW): -# ~TRST_EN=10(ACBUS2), ~CLK_EN=14(ACBUS6), ~MOSI_EN=13(ACBUS5), +# ~TRST_EN=10(ACBUS2), ~CLK_EN=14(ACBUS6), ~SDO_EN=13(ACBUS5), # TMS_SEL=5(ADBUS5), ~TMS_EN=12(ACBUS4), LED=~15(ACBUS7). # CONNECTION NOTES: # * Connect EXT connector pin 1 with 3 to get 5V on JTAG connector pin 19. @@ -1083,8 +1085,8 @@ programmer buff = 5, ~10, ~13, ~14; reset = 8; sck = 0; - mosi = 1; - miso = 2; + sdo = 1; + sdi = 2; rdyled = ~15; ; @@ -1106,8 +1108,8 @@ programmer buff = 5, 6, 7; reset = 3; sck = 0; - mosi = 1; - miso = 2; + sdo = 1; + sdi = 2; ; #------------------------------------------------------------ @@ -1190,11 +1192,11 @@ programmer prog_modes = PM_TPI | PM_ISP; connection_type = serial; # pins are bits in bitbang byte (numbers are 87654321) - # 1|POWER|PULLUP|AUX|MOSI|CLK|MISO|CS + # 1|POWER|PULLUP|AUX|SDO|CLK|SDI|CS reset = 1; sck = 3; - mosi = 4; - miso = 2; + sdo = 4; + sdi = 2; # vcc = 7; # Internally set independent of this setting ; @@ -1335,8 +1337,8 @@ programmer connection_type = usb; reset = 4; # D4 sck = 0; # D0 - mosi = 2; # D2 - miso = 1; # D1 + sdo = 2; # D2 + sdi = 1; # D1 ; #------------------------------------------------------------ @@ -1351,8 +1353,8 @@ programmer connection_type = usb; reset = 4; # DTR sck = 0; # TxD - mosi = 2; # RTS - miso = 1; # RxD + sdo = 2; # RTS + sdi = 1; # RxD ; #------------------------------------------------------------ @@ -1369,8 +1371,8 @@ programmer connection_type = usb; reset = 7; # RI sck = 6; # DCD - mosi = 3; # CTS - miso = 5; # DSR + sdo = 3; # CTS + sdi = 5; # DSR ; #------------------------------------------------------------ @@ -1388,8 +1390,8 @@ programmer connection_type = usb; reset = 7; # RI X3(4) sck = 5; # DSR X3(2) - mosi = 6; # DCD X3(3) - miso = 3; # CTS X3(1) + sdo = 6; # DCD X3(3) + sdi = 3; # CTS X3(1) ; #------------------------------------------------------------ @@ -1405,8 +1407,8 @@ programmer # FOR TPI devices: reset = 3; # CTS = D3 (wire to ~RESET) sck = 2; # RTS = D2 (wire to SCK) - mosi = 0; # TxD = D0 (wire to TPIDATA via 1k resistor) - miso = 1; # RxD = D1 (wire to TPIDATA directly) + sdo = 0; # TxD = D0 (wire to TPIDATA via 1k resistor) + sdi = 1; # RxD = D1 (wire to TPIDATA directly) ; #------------------------------------------------------------ @@ -1439,8 +1441,8 @@ programmer connection_type = usb; reset = 7; # ri sck = 5; # dsr - mosi = 6; # dcd - miso = 3; # cts + sdo = 6; # dcd + sdi = 3; # cts ; #------------------------------------------------------------ @@ -1453,11 +1455,11 @@ programmer # For ICSP pinout see for example http://www.atmel.com/images/doc2562.pdf # (Figure 1. ISP6PIN header pinout and Table 1. Connections required for ISP ...) # TTL-232R GND 1 Black -> ICPS GND (pin 6) -# TTL-232R CTS 2 Brown -> ICPS MOSI (pin 4) +# TTL-232R CTS 2 Brown -> ICPS SDO (pin 4) # TTL-232R VCC 3 Red -> ICPS VCC (pin 2) # TTL-232R TXD 4 Orange -> ICPS RESET (pin 5) # TTL-232R RXD 5 Yellow -> ICPS SCK (pin 3) -# TTL-232R RTS 6 Green -> ICPS MISO (pin 1) +# TTL-232R RTS 6 Green -> ICPS SDI (pin 1) # Except for VCC and GND, you can connect arbitual pairs as long as # the following table is adjusted. @@ -1469,8 +1471,8 @@ programmer connection_type = usb; reset = 0; # txd sck = 1; # rxd - mosi = 3; # cts - miso = 2; # rts + sdo = 3; # cts + sdi = 2; # rts ; #------------------------------------------------------------ @@ -1537,8 +1539,8 @@ programmer #------------------------------------------------------------ # USBtiny can also be used for TPI programming. -# In that case, a resistor of 1 kOhm is needed between MISO and MOSI -# pins of the connector, and MISO (pin 1 of the 6-pin connector) +# In that case, a resistor of 1 kOhm is needed between SDI and SDO +# pins of the connector, and SDI (pin 1 of the 6-pin connector) # connects to TPIDATA. programmer @@ -2421,18 +2423,18 @@ programmer # Using RI is not supported under Win32 but is supported under Posix. # serial ponyprog design (dasa2 in uisp) -# reset=!txd sck=rts mosi=dtr miso=cts +# reset=!txd sck=rts sdo=dtr sdi=cts programmer id = "ponyser"; - desc = "design ponyprog serial, reset=!txd sck=rts mosi=dtr miso=cts"; + desc = "design ponyprog serial, reset=!txd sck=rts sdo=dtr sdi=cts"; type = "serbb"; prog_modes = PM_TPI | PM_ISP; connection_type = serial; reset = ~3; sck = 7; - mosi = 4; - miso = 8; + sdo = 4; + sdi = 8; ; #------------------------------------------------------------ @@ -2440,7 +2442,7 @@ programmer #------------------------------------------------------------ # Same as above, different name -# reset=!txd sck=rts mosi=dtr miso=cts +# reset=!txd sck=rts sdo=dtr sdi=cts programmer parent "ponyser" id = "siprog"; @@ -2452,18 +2454,18 @@ programmer parent "ponyser" #------------------------------------------------------------ # unknown (dasa in uisp) -# reset=rts sck=dtr mosi=txd miso=cts +# reset=rts sck=dtr sdo=txd sdi=cts programmer id = "dasa"; - desc = "serial port banging, reset=rts sck=dtr mosi=txd miso=cts"; + desc = "serial port banging, reset=rts sck=dtr sdo=txd sdi=cts"; type = "serbb"; prog_modes = PM_TPI | PM_ISP; connection_type = serial; reset = 7; sck = 4; - mosi = 3; - miso = 8; + sdo = 3; + sdi = 8; ; #------------------------------------------------------------ @@ -2471,18 +2473,18 @@ programmer #------------------------------------------------------------ # unknown (dasa3 in uisp) -# reset=!dtr sck=rts mosi=txd miso=cts +# reset=!dtr sck=rts sdo=txd sdi=cts programmer id = "dasa3"; - desc = "serial port banging, reset=!dtr sck=rts mosi=txd miso=cts"; + desc = "serial port banging, reset=!dtr sck=rts sdo=txd sdi=cts"; type = "serbb"; prog_modes = PM_TPI | PM_ISP; connection_type = serial; reset = ~4; sck = 7; - mosi = 3; - miso = 8; + sdo = 3; + sdi = 8; ; #------------------------------------------------------------ @@ -2490,18 +2492,18 @@ programmer #------------------------------------------------------------ # C2N232i (jumper configuration "auto") -# reset=dtr sck=!rts mosi=!txd miso=!cts +# reset=dtr sck=!rts sdo=!txd sdi=!cts programmer id = "c2n232i"; - desc = "serial port banging, reset=dtr sck=!rts mosi=!txd miso=!cts"; + desc = "serial port banging, reset=dtr sck=!rts sdo=!txd sdi=!cts"; type = "serbb"; prog_modes = PM_TPI | PM_ISP; connection_type = serial; reset = 4; sck = ~7; - mosi = ~3; - miso = ~8; + sdo = ~3; + sdi = ~8; ; #------------------------------------------------------------ @@ -2729,6 +2731,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 0; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -3740,6 +3744,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 72; n_interrupts = 35; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xa0; avr910_devcode = 0x45; chip_erase_delay = 9000; @@ -3869,6 +3875,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 85; n_interrupts = 35; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xb2; avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -3999,6 +4007,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 176; n_interrupts = 37; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -4122,6 +4132,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 172; n_interrupts = 37; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -4245,6 +4257,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 171; n_interrupts = 37; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -4368,6 +4382,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 49; n_interrupts = 21; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x82; avr910_devcode = 0x74; chip_erase_delay = 9000; @@ -4493,6 +4509,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 111; n_interrupts = 31; + n_boot_sections = 4; + boot_section_size = 512; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4614,6 +4632,7 @@ part parent "m324p" desc = "ATmega164P"; id = "m164p"; mcuid = 93; + boot_section_size = 256; signature = 0x1e 0x94 0x0a; memory "eeprom" @@ -4690,6 +4709,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 127; n_interrupts = 28; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4845,6 +4866,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 140; n_interrupts = 35; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4980,6 +5003,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 90; n_interrupts = 28; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x83; avr910_devcode = 0x63; chip_erase_delay = 9000; @@ -5101,6 +5126,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP; mcuid = 91; n_interrupts = 18; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x81; avr910_devcode = 0x64; chip_erase_delay = 32000; @@ -5205,6 +5232,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 104; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x85; avr910_devcode = 0x78; chip_erase_delay = 9000; @@ -5362,6 +5391,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 121; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 512; # stk500_devcode = 0x85; # no STK500 support, only STK500v2 # avr910_devcode = 0x?; # try the ATmega169 one: avr910_devcode = 0x75; @@ -5565,6 +5596,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 135; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0x85; # no STK500 support, only STK500v2 # avr910_devcode = 0x?; # try the ATmega169 one: avr910_devcode = 0x75; @@ -5745,6 +5778,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG | PM_JTAGmkI; mcuid = 58; n_interrupts = 21; + n_boot_sections = 4; + boot_section_size = 512; stk500_devcode = 0x91; avr910_devcode = 0x72; chip_erase_delay = 9000; @@ -5858,6 +5893,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP; mcuid = 89; n_interrupts = 21; + n_boot_sections = 1; + boot_section_size = 1024; stk500_devcode = 0x80; avr910_devcode = 0x60; chip_erase_delay = 28000; @@ -5959,6 +5996,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP; mcuid = 45; n_interrupts = 19; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x70; avr910_devcode = 0x76; chip_erase_delay = 10000; @@ -6080,6 +6119,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP; mcuid = 160; n_interrupts = 17; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x63; avr910_devcode = 0x3a; chip_erase_delay = 9000; @@ -6183,6 +6224,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP; mcuid = 161; n_interrupts = 21; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x64; avr910_devcode = 0x69; chip_erase_delay = 9000; @@ -6429,6 +6472,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -6565,6 +6610,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -6701,6 +6748,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -6892,6 +6941,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7028,6 +7079,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 79; n_interrupts = 26; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x73; chip_erase_delay = 9000; pagel = 0xd7; @@ -7064,6 +7117,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7201,6 +7256,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 99; n_interrupts = 26; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x86; chip_erase_delay = 9000; pagel = 0xd7; @@ -7237,6 +7294,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7374,6 +7433,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 35; n_interrupts = 26; + n_boot_sections = 4; + boot_section_size = 256; stk500_devcode = 0x86; chip_erase_delay = 15000; pagel = 0xd7; @@ -7410,6 +7471,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7546,6 +7609,7 @@ part programfusepolltimeout = 5; programlockpolltimeout = 5; spmcr = 0x57; + eecr = 0x3f; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7673,6 +7737,7 @@ part programfusepolltimeout = 5; programlockpolltimeout = 5; spmcr = 0x57; + eecr = 0x3f; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7800,6 +7865,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -7928,6 +7995,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8020,6 +8089,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 118; n_interrupts = 26; + n_boot_sections = 4; + boot_section_size = 512; stk500_devcode = 0x86; chip_erase_delay = 9000; pagel = 0xd7; @@ -8056,6 +8127,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8194,6 +8267,7 @@ part parent "m328" id = "m64m1"; mcuid = 76; n_interrupts = 31; + boot_section_size = 1024; bs2 = 0xe2; # stk500_devcode = 0x??; # avr910_devcode = 0x??; @@ -8269,6 +8343,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 0; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8413,6 +8489,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 0; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8505,6 +8583,7 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 167; n_interrupts = 32; + n_boot_sections = 4; stk500_devcode = 0x65; chip_erase_delay = 9000; pagel = 0xd8; @@ -8540,6 +8619,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8631,6 +8712,7 @@ part parent "pwm2" desc = "AT90PWM3"; id = "pwm3"; mcuid = 169; + boot_section_size = 256; ; #------------------------------------------------------------ @@ -8642,6 +8724,7 @@ part parent "pwm2" desc = "AT90PWM2B"; id = "pwm2b"; mcuid = 168; + boot_section_size = 256; signature = 0x1e 0x93 0x83; ocdrev = 1; ; @@ -8668,6 +8751,7 @@ part parent "pwm3b" desc = "AT90PWM316"; id = "pwm316"; mcuid = 180; + boot_section_size = 512; signature = 0x1e 0x94 0x83; memory "flash" @@ -8742,6 +8826,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -8871,6 +8957,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -9001,6 +9089,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -9094,6 +9184,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 126; n_interrupts = 57; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -9217,6 +9309,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 138; n_interrupts = 57; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -9353,6 +9447,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 143; n_interrupts = 57; + n_boot_sections = 4; + boot_section_size = 1024; stk500_devcode = 0xb2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -9649,6 +9745,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -9789,6 +9887,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -9929,6 +10029,8 @@ part programfusepolltimeout = 25; programlockpolltimeout = 25; synchcycles = 6; + spmcr = 0x57; + eecr = 0x3c; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -10119,6 +10221,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -10212,6 +10316,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 57; n_interrupts = 43; + n_boot_sections = 4; + boot_section_size = 512; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10336,6 +10442,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 65; n_interrupts = 43; + n_boot_sections = 4; + boot_section_size = 512; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10460,6 +10568,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 181; n_interrupts = 38; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10595,6 +10705,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 184; n_interrupts = 38; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10730,6 +10842,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 178; n_interrupts = 29; + n_boot_sections = 4; + boot_section_size = 512; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; @@ -10759,6 +10873,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -10850,6 +10966,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 174; n_interrupts = 58; + n_boot_sections = 4; + boot_section_size = 512; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; @@ -10879,6 +10997,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -10970,6 +11090,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 64; n_interrupts = 29; + n_boot_sections = 4; + boot_section_size = 512; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; @@ -10999,6 +11121,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -11090,6 +11214,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 56; n_interrupts = 29; + n_boot_sections = 4; + boot_section_size = 512; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; @@ -11119,6 +11245,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -11210,6 +11338,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; mcuid = 48; n_interrupts = 58; + n_boot_sections = 4; + boot_section_size = 512; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; @@ -11239,6 +11369,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3f; ocdrev = 1; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -11330,6 +11462,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 95; n_interrupts = 22; + n_boot_sections = 4; + boot_section_size = 256; # stk500_devcode = 0x??; # avr910_devcode = 0x??; chip_erase_delay = 9000; @@ -11484,6 +11618,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 114; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 512; # stk500_devcode = 0x??; # No STK500v1 support? # avr910_devcode = 0x??; # Try the ATmega16 one avr910_devcode = 0x74; @@ -11642,6 +11778,8 @@ part prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; mcuid = 132; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 1024; # stk500_devcode = 0x??; # No STK500v1 support? # avr910_devcode = 0x??; # Try the ATmega16 one avr910_devcode = 0x74; @@ -11870,6 +12008,7 @@ part desc = "AVR XMEGA family common values"; id = ".xmega"; prog_modes = PM_SPM | PM_PDI; + n_boot_sections = 1; mcu_base = 0x0090; nvm_base = 0x01c0; @@ -11925,6 +12064,7 @@ part parent ".xmega" id = "x16a4u"; mcuid = 232; n_interrupts = 127; + boot_section_size = 4096; signature = 0x1e 0x94 0x41; usbpid = 0x2fe3; @@ -12019,6 +12159,7 @@ part parent ".xmega" id = "x32a4u"; mcuid = 239; n_interrupts = 127; + boot_section_size = 4096; signature = 0x1e 0x95 0x41; usbpid = 0x2fe4; @@ -12113,6 +12254,7 @@ part parent ".xmega" id = "x64a4u"; mcuid = 252; n_interrupts = 127; + boot_section_size = 4096; signature = 0x1e 0x96 0x46; usbpid = 0x2fe5; @@ -12295,6 +12437,7 @@ part parent ".xmega" id = "x128c3"; mcuid = 261; n_interrupts = 127; + boot_section_size = 8192; signature = 0x1e 0x97 0x52; usbpid = 0x2fd7; @@ -12503,6 +12646,7 @@ part parent ".xmega" id = "x128a4u"; mcuid = 264; n_interrupts = 127; + boot_section_size = 8192; signature = 0x1e 0x97 0x46; usbpid = 0x2fde; @@ -12559,6 +12703,7 @@ part parent ".xmega" prog_modes = PM_SPM | PM_PDI | PM_XMEGAJTAG; mcuid = 257; n_interrupts = 81; + boot_section_size = 8192; signature = 0x1e 0x97 0x4d; usbpid = 0x2fea; @@ -12632,6 +12777,7 @@ part parent ".xmega" id = "x192c3"; mcuid = 269; n_interrupts = 127; + boot_section_size = 8192; signature = 0x1e 0x97 0x51; # usbpid = 0x2f??; @@ -12740,6 +12886,7 @@ part parent ".xmega" id = "x256c3"; mcuid = 276; n_interrupts = 127; + boot_section_size = 8192; signature = 0x1e 0x98 0x46; usbpid = 0x2fda; @@ -12871,6 +13018,7 @@ part parent ".xmega" id = "x384c3"; mcuid = 278; n_interrupts = 127; + boot_section_size = 8192; signature = 0x1e 0x98 0x45; usbpid = 0x2fdb; @@ -12938,6 +13086,7 @@ part parent ".xmega" id = "x8e5"; mcuid = 230; n_interrupts = 43; + boot_section_size = 2048; signature = 0x1e 0x93 0x41; memory "eeprom" @@ -12992,6 +13141,7 @@ part parent ".xmega" id = "x16e5"; mcuid = 235; n_interrupts = 43; + boot_section_size = 4096; signature = 0x1e 0x94 0x45; memory "eeprom" @@ -13046,6 +13196,7 @@ part parent ".xmega" id = "x32e5"; mcuid = 242; n_interrupts = 43; + boot_section_size = 4096; signature = 0x1e 0x95 0x4c; memory "eeprom" @@ -13166,6 +13317,8 @@ part chiperasepolltimeout = 10; programfusepolltimeout = 5; programlockpolltimeout = 5; + spmcr = 0x57; + eecr = 0x3c; chip_erase = "1010.1100--100x.xxxx--xxxx.xxxx--xxxx.xxxx"; pgm_enable = "1010.1100--0101.0011--xxxx.xxxx--xxxx.xxxx"; @@ -13446,6 +13599,8 @@ part prog_modes = PM_SPM | PM_HVPP | PM_JTAG; mcuid = 125; n_interrupts = 23; + n_boot_sections = 4; + boot_section_size = 512; # STK500 parameters (parallel programming IO lines) pagel = 0xa7; bs2 = 0xa0; @@ -13508,6 +13663,7 @@ part desc = "AVR8X family common values"; id = ".avr8x"; prog_modes = PM_SPM | PM_UPDI; + n_boot_sections = 1; nvm_base = 0x1000; ocd_base = 0x0f80; @@ -14880,6 +15036,7 @@ part id = ".avrdx"; family_id = "AVR "; prog_modes = PM_SPM | PM_UPDI; + n_boot_sections = 1; # Dedicated UPDI pin, no HV hvupdi_variant = 1; nvm_base = 0x1000; diff --git a/src/avrftdi.c b/src/avrftdi.c index 00d04f09..1427743d 100644 --- a/src/avrftdi.c +++ b/src/avrftdi.c @@ -62,7 +62,7 @@ void avrftdi_initpgm(PROGRAMMER *pgm) { #else -enum { FTDI_SCK = 0, FTDI_MOSI, FTDI_MISO, FTDI_RESET }; +enum { FTDI_SCK = 0, FTDI_SDO, FTDI_SDI, FTDI_RESET }; static int write_flush(avrftdi_t *); @@ -216,7 +216,7 @@ static int set_frequency(avrftdi_t* ftdi, uint32_t freq) } /* - * This function sets or clears any pin, except SCK, MISO and MOSI. Depending + * This function sets or clears any pin, except SCK, SDI and SDO. Depending * on the pin configuration, a non-zero value sets the pin in the 'active' * state (high active, low active) and a zero value sets the pin in the * inactive state. @@ -288,7 +288,7 @@ static inline int set_data(const PROGRAMMER *pgm, unsigned char *buf, unsigned c avrftdi_t* pdata = to_pdata(pgm); for (j=0; j<8; j++) { - pdata->pin_value = SET_BITS_0(pdata->pin_value,pgm,PIN_AVR_MOSI,data & bit); + pdata->pin_value = SET_BITS_0(pdata->pin_value,pgm,PIN_AVR_SDO,data & bit); pdata->pin_value = SET_BITS_0(pdata->pin_value,pgm,PIN_AVR_SCK,0); buf[buf_pos++] = SET_BITS_LOW; buf[buf_pos++] = (pdata->pin_value) & 0xff; @@ -323,7 +323,7 @@ static inline unsigned char extract_data(const PROGRAMMER *pgm, unsigned char *b buf += offset * 16; // 2 bytes per bit, 8 bits for (j=0; j<8; j++) { uint16_t in = buf[0] | (buf[1] << 8); - if (GET_BITS_0(in,pgm,PIN_AVR_MISO)) { + if (GET_BITS_0(in,pgm,PIN_AVR_SDI)) { r |= bit; } buf += 2; // 2 bytes per input @@ -545,16 +545,16 @@ static int avrftdi_check_pins_mpsse(const PROGRAMMER *pgm, bool output) { avrftdi_t* pdata = to_pdata(pgm); - /* SCK/MOSI/MISO are fixed and not invertible?*/ - /* TODO: inverted SCK/MISO/MOSI */ - static const struct pindef_t valid_pins_SCK = {{0x01},{0x00}} ; - static const struct pindef_t valid_pins_MOSI = {{0x02},{0x00}} ; - static const struct pindef_t valid_pins_MISO = {{0x04},{0x00}} ; + /* SCK/SDO/SDI are fixed and not invertible? */ + /* TODO: inverted SCK/SDI/SDO */ + static const struct pindef_t valid_pins_SCK = {{0x01},{0x00}}; + static const struct pindef_t valid_pins_SDO = {{0x02},{0x00}}; + static const struct pindef_t valid_pins_SDI = {{0x04},{0x00}}; /* value for 8/12/16 bit wide interface for other pins */ int valid_mask = ((1 << pdata->pin_limit) - 1); - /* mask out SCK/MISO/MOSI */ - valid_mask &= ~((1 << FTDI_SCK) | (1 << FTDI_MOSI) | (1 << FTDI_MISO)); + /* mask out SCK/SDI/SDO */ + valid_mask &= ~((1 << FTDI_SCK) | (1 << FTDI_SDO) | (1 << FTDI_SDI)); log_debug("Using valid mask mpsse: 0x%08x\n", valid_mask); static struct pindef_t valid_pins_others; @@ -571,10 +571,10 @@ static int avrftdi_check_pins_mpsse(const PROGRAMMER *pgm, bool output) { /* now set mpsse specific pins */ pin_checklist[PIN_AVR_SCK].mandatory = 1; pin_checklist[PIN_AVR_SCK].valid_pins = &valid_pins_SCK; - pin_checklist[PIN_AVR_MOSI].mandatory = 1; - pin_checklist[PIN_AVR_MOSI].valid_pins = &valid_pins_MOSI; - pin_checklist[PIN_AVR_MISO].mandatory = 1; - pin_checklist[PIN_AVR_MISO].valid_pins = &valid_pins_MISO; + pin_checklist[PIN_AVR_SDO].mandatory = 1; + pin_checklist[PIN_AVR_SDO].valid_pins = &valid_pins_SDO; + pin_checklist[PIN_AVR_SDI].mandatory = 1; + pin_checklist[PIN_AVR_SDI].valid_pins = &valid_pins_SDI; pin_checklist[PIN_AVR_RESET].mandatory = 1; /* assumes all checklists above have same number of entries */ @@ -599,10 +599,10 @@ static int avrftdi_pin_setup(const PROGRAMMER *pgm) { avrftdi_check_pins_bb(pgm, true); log_err("Pin configuration for FTDI MPSSE must be:\n"); log_err("%s: 0, %s: 1, %s: 2 (is: %s, %s, %s)\n", avr_pin_name(PIN_AVR_SCK), - avr_pin_name(PIN_AVR_MOSI), avr_pin_name(PIN_AVR_MISO), - pins_to_str(&pgm->pin[PIN_AVR_SCK]), - pins_to_str(&pgm->pin[PIN_AVR_MOSI]), - pins_to_str(&pgm->pin[PIN_AVR_MISO])); + avr_pin_name(PIN_AVR_SDO), avr_pin_name(PIN_AVR_SDI), + pins_to_str(&pgm->pin[PIN_AVR_SCK]), + pins_to_str(&pgm->pin[PIN_AVR_SDO]), + pins_to_str(&pgm->pin[PIN_AVR_SDI])); log_err("If other pin configuration is used, fallback to slower bitbanging mode is used.\n"); return -1; @@ -614,16 +614,16 @@ static int avrftdi_pin_setup(const PROGRAMMER *pgm) { /* * TODO: No need to fail for a wrongly configured led or something. - * Maybe we should only fail for SCK; MISO, MOSI, RST (and probably + * Maybe we should only fail for SCK; SDI, SDO, RST (and probably * VCC and BUFF). */ - /* everything is an output, except MISO */ + /* everything is an output, except SDI */ for(pin = 0; pin < N_PINS; ++pin) { pdata->pin_direction |= pgm->pin[pin].mask[0]; pdata->pin_value = SET_BITS_0(pdata->pin_value, pgm, pin, OFF); } - pdata->pin_direction &= ~pgm->pin[PIN_AVR_MISO].mask[0]; + pdata->pin_direction &= ~pgm->pin[PIN_AVR_SDI].mask[0]; for(pin = PIN_LED_ERR; pin < N_PINS; ++pin) { pdata->led_mask |= pgm->pin[pin].mask[0]; diff --git a/src/avrftdi_tpi.c b/src/avrftdi_tpi.c index dcb3d48d..f4cd18f9 100644 --- a/src/avrftdi_tpi.c +++ b/src/avrftdi_tpi.c @@ -72,7 +72,7 @@ avrftdi_tpi_initialize(const PROGRAMMER *pgm, const AVRPART *p) { log_info("Setting /Reset pin low\n"); pgm->setpin(pgm, PIN_AVR_RESET, OFF); pgm->setpin(pgm, PIN_AVR_SCK, OFF); - pgm->setpin(pgm, PIN_AVR_MOSI, ON); + pgm->setpin(pgm, PIN_AVR_SDO, ON); usleep(20 * 1000); pgm->setpin(pgm, PIN_AVR_RESET, ON); diff --git a/src/avrintel.c b/src/avrintel.c index a74d964e..f0033cce 100644 --- a/src/avrintel.c +++ b/src/avrintel.c @@ -9,7 +9,7 @@ * meta-author Stefan Rueger * * v 1.1 - * 20.11.2022 + * 24.11.2022 * */ @@ -447,7 +447,7 @@ const char * const vtab_attiny20[vts_attiny20] = { // ATtiny20 "TIM0_OVF", // 11: Timer 0 Overflow "ANA_COMP", // 12: Analog Comparator "ADC_ADC", // 13: Conversion Complete - "TWI_SLAVE", // 14: 2-Wire Interface Periphery + "TWI_PERIPHERAL", // 14: 2-Wire Interface Peripheral "SPI", // 15: SPI Serial Peripheral Interface "QTRIP", // 16: Touch Sensing }; @@ -468,7 +468,7 @@ const char * const vtab_attiny40[vts_attiny40] = { // ATtiny40 "TIM0_OVF", // 12: Timer 0 Overflow "ANA_COMP", // 13: Analog Comparator "ADC", // 14: ADC Conversion Complete - "TWI_SLAVE", // 15: 2-Wire Interface Periphery + "TWI_PERIPHERAL", // 15: 2-Wire Interface Peripheral "SPI", // 16: SPI Serial Peripheral Interface "QTRIP", // 17: Touch Sensing }; @@ -691,7 +691,7 @@ const char * const vtab_attiny828[vts_attiny828] = { // ATtiny828 "ADC", // 20: ADC Conversion Complete "EE_READY", // 21: EEPROM Ready "ANALOG_COMP", // 22: Analog Comparator - "TWI_SLAVE", // 23: 2-Wire Interface Periphery + "TWI_PERIPHERAL", // 23: 2-Wire Interface Peripheral "SPM_Ready", // 24: Store Program Memory Ready "QTRIP", // 25: Touch Sensing }; @@ -726,7 +726,7 @@ const char * const vtab_attiny841[vts_attiny841] = { // ATtiny841, ATtiny441 "USART1_RX", // 26: USART 1 Receive Complete "USART1_UDRE", // 27: USART 1 Data Register Empty "USART1_TX", // 28: USART 1 Transmit Complete - "TWI_SLAVE", // 29: 2-Wire Interface Periphery + "TWI_PERIPHERAL", // 29: 2-Wire Interface Peripheral }; const char * const vtab_attiny861a[vts_attiny861a] = { // ATtiny861A, ATtiny861, ATtiny461A, ATtiny461, ATtiny261A, ATtiny261 @@ -777,7 +777,7 @@ const char * const vtab_attiny1634[vts_attiny1634] = { // ATtiny1634 "USART1_TXC", // 22: USART 1 Transmit Complete "USI_START", // 23: USI Start Condition "USI_OVERFLOW", // 24: USI Overflow - "TWI/TWI_SLAVE", // 25: 2-Wire Interface/2-Wire Interface Periphery + "TWI/TWI_PERIPHERAL", // 25: 2-Wire Interface/2-Wire Interface Peripheral "EE_RDY", // 26: EEPROM Ready "QTRIP", // 27: Touch Sensing }; @@ -2597,7 +2597,7 @@ const char * const vtab_atxmega32a4[vts_atxmega32a4] = { // ATxmega32A4, ATxmega "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF", // 14: TC C0 Overflow "TCC0_ERR", // 15: TC C0 Error @@ -2630,7 +2630,7 @@ const char * const vtab_atxmega32a4[vts_atxmega32a4] = { // ATxmega32A4, ATxmega "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -2694,7 +2694,7 @@ const char * const vtab_atxmega32c4[vts_atxmega32c4] = { // ATxmega32C4, ATxmega "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -2727,7 +2727,7 @@ const char * const vtab_atxmega32c4[vts_atxmega32c4] = { // ATxmega32C4, ATxmega "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -2824,7 +2824,7 @@ const char * const vtab_atxmega32d4[vts_atxmega32d4] = { // ATxmega32D4, ATxmega "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -2857,7 +2857,7 @@ const char * const vtab_atxmega32d4[vts_atxmega32d4] = { // ATxmega32D4, ATxmega "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -2916,7 +2916,7 @@ const char * const vtab_atxmega32e5[vts_atxmega32e5] = { // ATxmega32E5, ATxmega "RTC_OVF", // 7: RTC Overflow "RTC_COMP", // 8: RTC Compare "PORTC_INT", // 9: External Interrupt PORT C - "TWIC_TWIS", // 10: 2-Wire Interface C Periphery + "TWIC_TWIP", // 10: 2-Wire Interface C Peripheral "TWIC_TWIM", // 11: 2-Wire Interface C Controller "TCC4_OVF", // 12: TC C4 Overflow "TCC4_ERR", // 13: TC C4 Error @@ -2964,7 +2964,7 @@ const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxm "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF", // 14: TC C0 Overflow "TCC0_ERR", // 15: TC C0 Error @@ -2997,7 +2997,7 @@ const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxm "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -3027,7 +3027,7 @@ const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxm "ADCA_CH1", // 72: ADCA Interrupt 1 "ADCA_CH2", // 73: ADCA Interrupt 2 "ADCA_CH3", // 74: ADCA Interrupt 3 - "TWID_TWIS", // 75: 2-Wire Interface D Periphery + "TWID_TWIP", // 75: 2-Wire Interface D Peripheral "TWID_TWIM", // 76: 2-Wire Interface D Controller "TCD0_OVF", // 77: TC D0 Overflow "TCD0_ERR", // 78: TC D0 Error @@ -3058,7 +3058,7 @@ const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxm "UNUSED", // 103: not implemented on this device "PORTF_INT0", // 104: External Interrupt 0 PORT F "PORTF_INT1", // 105: External Interrupt 1 PORT F - "TWIF_TWIS", // 106: 2-Wire Interface F Periphery + "TWIF_TWIP", // 106: 2-Wire Interface F Peripheral "TWIF_TWIM", // 107: 2-Wire Interface F Controller "TCF0_OVF", // 108: TC F0 Overflow "TCF0_ERR", // 109: TC F0 Error @@ -3092,7 +3092,7 @@ const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, A "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3125,7 +3125,7 @@ const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, A "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -3155,7 +3155,7 @@ const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, A "ADCA_CH1", // 72: ADCA Interrupt 1 "ADCA_CH2", // 73: ADCA Interrupt 2 "ADCA_CH3", // 74: ADCA Interrupt 3 - "TWID_TWIS", // 75: 2-Wire Interface D Periphery + "TWID_TWIP", // 75: 2-Wire Interface D Peripheral "TWID_TWIM", // 76: 2-Wire Interface D Controller "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow @@ -3186,7 +3186,7 @@ const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, A "UNUSED", // 103: not implemented on this device "PORTF_INT0", // 104: External Interrupt 0 PORT F "PORTF_INT1", // 105: External Interrupt 1 PORT F - "TWIF_TWIS", // 106: 2-Wire Interface F Periphery + "TWIF_TWIP", // 106: 2-Wire Interface F Peripheral "TWIF_TWIM", // 107: 2-Wire Interface F Controller "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow @@ -3222,7 +3222,7 @@ const char * const vtab_atxmega128b1[vts_atxmega128b1] = { // ATxmega128B1, ATxm "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3306,7 +3306,7 @@ const char * const vtab_atxmega128b3[vts_atxmega128b3] = { // ATxmega128B3, ATxm "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3363,7 +3363,7 @@ const char * const vtab_atxmega128a4u[vts_atxmega128a4u] = { // ATxmega128A4U, A "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3396,7 +3396,7 @@ const char * const vtab_atxmega128a4u[vts_atxmega128a4u] = { // ATxmega128A4U, A "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -3493,7 +3493,7 @@ const char * const vtab_atxmega128d4[vts_atxmega128d4] = { // ATxmega128D4, ATxm "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3526,7 +3526,7 @@ const char * const vtab_atxmega128d4[vts_atxmega128d4] = { // ATxmega128D4, ATxm "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -3587,7 +3587,7 @@ const char * const vtab_atxmega256a3[vts_atxmega256a3] = { // ATxmega256A3, ATxm "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF", // 14: TC C0 Overflow "TCC0_ERR", // 15: TC C0 Error @@ -3620,7 +3620,7 @@ const char * const vtab_atxmega256a3[vts_atxmega256a3] = { // ATxmega256A3, ATxm "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -3712,7 +3712,7 @@ const char * const vtab_atxmega256a3b[vts_atxmega256a3b] = { // ATxmega256A3B "DMA_CH3", // 9: DMA Channel 3 "RTC32_OVF", // 10: RTC32 Overflow "RTC32_COMP", // 11: RTC32 Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF", // 14: TC C0 Overflow "TCC0_ERR", // 15: TC C0 Error @@ -3745,7 +3745,7 @@ const char * const vtab_atxmega256a3b[vts_atxmega256a3b] = { // ATxmega256A3B "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF", // 47: TC E0 Overflow "TCE0_ERR", // 48: TC E0 Error @@ -3837,7 +3837,7 @@ const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { // ATxmega256A3BU "DMA_CH3", // 9: DMA Channel 3 "RTC32_OVF", // 10: RTC32 Overflow "RTC32_COMP", // 11: RTC32 Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -3870,7 +3870,7 @@ const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { // ATxmega256A3BU "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -3967,7 +3967,7 @@ const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { // ATxmega256A3U, A "DMA_CH3", // 9: DMA Channel 3 "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -4000,7 +4000,7 @@ const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { // ATxmega256A3U, A "ADCB_CH3", // 42: ADCB Interrupt 3 "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -4097,7 +4097,7 @@ const char * const vtab_atxmega256c3[vts_atxmega256c3] = { // ATxmega256C3, ATxm "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -4130,7 +4130,7 @@ const char * const vtab_atxmega256c3[vts_atxmega256c3] = { // ATxmega256C3, ATxm "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -4227,7 +4227,7 @@ const char * const vtab_atxmega384c3[vts_atxmega384c3] = { // ATxmega384C3 "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -4260,7 +4260,7 @@ const char * const vtab_atxmega384c3[vts_atxmega384c3] = { // ATxmega384C3 "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -4357,7 +4357,7 @@ const char * const vtab_atxmega384d3[vts_atxmega384d3] = { // ATxmega384D3, ATxm "UNUSED", // 9: not implemented on this device "RTC_OVF", // 10: RTC Overflow "RTC_COMP", // 11: RTC Compare - "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral "TWIC_TWIM", // 13: 2-Wire Interface C Controller "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow @@ -4390,7 +4390,7 @@ const char * const vtab_atxmega384d3[vts_atxmega384d3] = { // ATxmega384D3, ATxm "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow @@ -4481,7 +4481,7 @@ const char * const vtab_attiny402[vts_attiny402] = { // ATtiny402, ATtiny202 "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4510,7 +4510,7 @@ const char * const vtab_attiny404[vts_attiny404] = { // ATtiny404, ATtiny204 "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4539,7 +4539,7 @@ const char * const vtab_attiny406[vts_attiny406] = { // ATtiny406 "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4568,7 +4568,7 @@ const char * const vtab_attiny412[vts_attiny412] = { // ATtiny412, ATtiny212 "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4597,7 +4597,7 @@ const char * const vtab_attiny814[vts_attiny814] = { // ATtiny814, ATtiny414, AT "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4626,7 +4626,7 @@ const char * const vtab_attiny817[vts_attiny817] = { // ATtiny817, ATtiny816, AT "AC0_AC", // 16: AC0 AC Interrupt "ADC0_RESRDY", // 17: ADC 0 Result Ready "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller "SPI0_INT", // 21: SPI 0 Interrupt "USART0_RXC", // 22: USART 0 Receive Complete @@ -4660,7 +4660,7 @@ const char * const vtab_attiny1607[vts_attiny1607] = { // ATtiny1607, ATtiny1606 "ADC0_WCOMP", // 21: ADC 0 Window Comparator "UNUSED", // 22: not implemented on this device "UNUSED", // 23: not implemented on this device - "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller "SPI0_INT", // 26: SPI 0 Interrupt "USART0_RXC", // 27: USART 0 Receive Complete @@ -4694,7 +4694,7 @@ const char * const vtab_attiny1614[vts_attiny1614] = { // ATtiny1614 "ADC0_WCOMP", // 21: ADC 0 Window Comparator "ADC1_RESRDY", // 22: ADC 1 Result Ready "ADC1_WCOMP", // 23: ADC 1 Window Comparator - "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller "SPI0_INT", // 26: SPI 0 Interrupt "USART0_RXC", // 27: USART 0 Receive Complete @@ -4728,7 +4728,7 @@ const char * const vtab_attiny3214[vts_attiny3214] = { // ATtiny3214 "ADC0_WCOMP", // 21: ADC 0 Window Comparator "ADC1_RESRDY", // 22: ADC 1 Result Ready "ADC1_WCOMP", // 23: ADC 1 Window Comparator - "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller "SPI0_INT", // 26: SPI 0 Interrupt "USART0_RXC", // 27: USART 0 Receive Complete @@ -4762,7 +4762,7 @@ const char * const vtab_attiny3217[vts_attiny3217] = { // ATtiny3217, ATtiny3216 "ADC0_WCOMP", // 21: ADC 0 Window Comparator "ADC1_RESRDY", // 22: ADC 1 Result Ready "ADC1_WCOMP", // 23: ADC 1 Window Comparator - "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller "SPI0_INT", // 26: SPI 0 Interrupt "USART0_RXC", // 27: USART 0 Receive Complete @@ -4786,7 +4786,7 @@ const char * const vtab_attiny3227[vts_attiny3227] = { // ATtiny3227, ATtiny3226 "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 "TCB0_INT", // 13: TC B0 Interrupt - "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 14: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller "SPI0_INT", // 16: SPI 0 Interrupt "USART0_RXC", // 17: USART 0 Receive Complete @@ -4819,7 +4819,7 @@ const char * const vtab_atmega4808[vts_atmega4808] = { // ATmega4808, ATmega3208 "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 "TCB0_INT", // 12: TC B0 Interrupt "TCB1_INT", // 13: TC B1 Interrupt - "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 14: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller "SPI0_INT", // 16: SPI 0 Interrupt "USART0_RXC", // 17: USART 0 Receive Complete @@ -4858,7 +4858,7 @@ const char * const vtab_atmega4809[vts_atmega4809] = { // ATmega4809, ATmega3209 "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 "TCB0_INT", // 12: TC B0 Interrupt "TCB1_INT", // 13: TC B1 Interrupt - "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 14: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller "SPI0_INT", // 16: SPI 0 Interrupt "USART0_RXC", // 17: USART 0 Receive Complete @@ -4905,7 +4905,7 @@ const char * const vtab_avr64dd32[vts_avr64dd32] = { // AVR64DD32, AVR64DD28, AV "TCB1_INT", // 15: TC B1 Interrupt "TCD0_OVF", // 16: TC D0 Overflow "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller "SPI0_INT", // 20: SPI 0 Interrupt "USART0_RXC", // 21: USART 0 Receive Complete @@ -4941,7 +4941,7 @@ const char * const vtab_avr64ea32[vts_avr64ea32] = { // AVR64EA32, AVR64EA28 "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 "TCB0_INT", // 13: TC B0 Interrupt "TCB1_INT", // 14: TC B1 Interrupt - "TWI0_TWIS", // 15: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller "SPI0_INT", // 17: SPI 0 Interrupt "USART0_RXC", // 18: USART 0 Receive Complete @@ -4981,7 +4981,7 @@ const char * const vtab_avr64ea48[vts_avr64ea48] = { // AVR64EA48 "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 "TCB0_INT", // 13: TC B0 Interrupt "TCB1_INT", // 14: TC B1 Interrupt - "TWI0_TWIS", // 15: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller "SPI0_INT", // 17: SPI 0 Interrupt "USART0_RXC", // 18: USART 0 Receive Complete @@ -5030,7 +5030,7 @@ const char * const vtab_avr128da28[vts_avr128da28] = { // AVR128DA28, AVR64DA28, "TCB1_INT", // 13: TC B1 Interrupt "TCD0_OVF", // 14: TC D0 Overflow "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller "SPI0_INT", // 18: SPI 0 Interrupt "USART0_RXC", // 19: USART 0 Receive Complete @@ -5076,7 +5076,7 @@ const char * const vtab_avr128db28[vts_avr128db28] = { // AVR128DB28, AVR64DB28, "TCB1_INT", // 15: TC B1 Interrupt "TCD0_OVF", // 16: TC D0 Overflow "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller "SPI0_INT", // 20: SPI 0 Interrupt "USART0_RXC", // 21: USART 0 Receive Complete @@ -5119,7 +5119,7 @@ const char * const vtab_avr128da32[vts_avr128da32] = { // AVR128DA32, AVR64DA32, "TCB1_INT", // 13: TC B1 Interrupt "TCD0_OVF", // 14: TC D0 Overflow "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller "SPI0_INT", // 18: SPI 0 Interrupt "USART0_RXC", // 19: USART 0 Receive Complete @@ -5145,7 +5145,7 @@ const char * const vtab_avr128da32[vts_avr128da32] = { // AVR128DA32, AVR64DA32, "USART2_TXC", // 39: USART 2 Transmit Complete "AC2_AC", // 40: AC2 AC Interrupt "UNUSED", // 41: not implemented on this device - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller }; @@ -5168,7 +5168,7 @@ const char * const vtab_avr128db32[vts_avr128db32] = { // AVR128DB32, AVR64DB32, "TCB1_INT", // 15: TC B1 Interrupt "TCD0_OVF", // 16: TC D0 Overflow "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller "SPI0_INT", // 20: SPI 0 Interrupt "USART0_RXC", // 21: USART 0 Receive Complete @@ -5192,7 +5192,7 @@ const char * const vtab_avr128db32[vts_avr128db32] = { // AVR128DB32, AVR64DB32, "USART2_DRE", // 39: USART 2 Data Register Empty "USART2_TXC", // 40: USART 2 Transmit Complete "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller }; @@ -5213,7 +5213,7 @@ const char * const vtab_avr128da48[vts_avr128da48] = { // AVR128DA48, AVR64DA48, "TCB1_INT", // 13: TC B1 Interrupt "TCD0_OVF", // 14: TC D0 Overflow "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller "SPI0_INT", // 18: SPI 0 Interrupt "USART0_RXC", // 19: USART 0 Receive Complete @@ -5239,7 +5239,7 @@ const char * const vtab_avr128da48[vts_avr128da48] = { // AVR128DA48, AVR64DA48, "USART2_TXC", // 39: USART 2 Transmit Complete "AC2_AC", // 40: AC2 AC Interrupt "TCB3_INT", // 41: TC B3 Interrupt - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller "PORTB_PORT", // 44: Interrupt PORT B "PORTE_PORT", // 45: Interrupt PORT E @@ -5276,7 +5276,7 @@ const char * const vtab_avr128db48[vts_avr128db48] = { // AVR128DB48, AVR64DB48, "TCB1_INT", // 15: TC B1 Interrupt "TCD0_OVF", // 16: TC D0 Overflow "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller "SPI0_INT", // 20: SPI 0 Interrupt "USART0_RXC", // 21: USART 0 Receive Complete @@ -5300,7 +5300,7 @@ const char * const vtab_avr128db48[vts_avr128db48] = { // AVR128DB48, AVR64DB48, "USART2_DRE", // 39: USART 2 Data Register Empty "USART2_TXC", // 40: USART 2 Transmit Complete "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller "TCB3_INT", // 44: TC B3 Interrupt "PORTB_PORT", // 45: Interrupt PORT B @@ -5338,7 +5338,7 @@ const char * const vtab_avr128da64[vts_avr128da64] = { // AVR128DA64, AVR64DA64 "TCB1_INT", // 13: TC B1 Interrupt "TCD0_OVF", // 14: TC D0 Overflow "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller "SPI0_INT", // 18: SPI 0 Interrupt "USART0_RXC", // 19: USART 0 Receive Complete @@ -5364,7 +5364,7 @@ const char * const vtab_avr128da64[vts_avr128da64] = { // AVR128DA64, AVR64DA64 "USART2_TXC", // 39: USART 2 Transmit Complete "AC2_AC", // 40: AC2 AC Interrupt "TCB3_INT", // 41: TC B3 Interrupt - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller "PORTB_PORT", // 44: Interrupt PORT B "PORTE_PORT", // 45: Interrupt PORT E @@ -5407,7 +5407,7 @@ const char * const vtab_avr128db64[vts_avr128db64] = { // AVR128DB64, AVR64DB64 "TCB1_INT", // 15: TC B1 Interrupt "TCD0_OVF", // 16: TC D0 Overflow "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller "SPI0_INT", // 20: SPI 0 Interrupt "USART0_RXC", // 21: USART 0 Receive Complete @@ -5431,7 +5431,7 @@ const char * const vtab_avr128db64[vts_avr128db64] = { // AVR128DB64, AVR64DB64 "USART2_DRE", // 39: USART 2 Data Register Empty "USART2_TXC", // 40: USART 2 Transmit Complete "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller "TCB3_INT", // 44: TC B3 Interrupt "PORTB_PORT", // 45: Interrupt PORT B diff --git a/src/avrintel.h b/src/avrintel.h index 0ab72822..9da54fba 100644 --- a/src/avrintel.h +++ b/src/avrintel.h @@ -9,7 +9,7 @@ * meta-author Stefan Rueger * * v 1.1 - * 20.11.2022 + * 24.11.2022 * */ diff --git a/src/bitbang.c b/src/bitbang.c index 74548d5a..4d0be96e 100644 --- a/src/bitbang.c +++ b/src/bitbang.c @@ -172,9 +172,9 @@ static unsigned char bitbang_txrx(const PROGRAMMER *pgm, unsigned char byte) { * one pgm->setpin()-call resp. par clrpin()-call, then * - SCK is high for 2T * - SCK is low for 2T - * - MOSI setuptime is 1T - * - MOSI holdtime is 3T - * - SCK low to MISO read is 2T to 3T + * - SDO setuptime is 1T + * - SDO holdtime is 3T + * - SCK low to SDI read is 2T to 3T * So we are within programming specs (expect for AT90S1200), * if and only if T>t_CLCL (t_CLCL=clock period of target system). * @@ -186,7 +186,7 @@ static unsigned char bitbang_txrx(const PROGRAMMER *pgm, unsigned char byte) { b = (byte >> i) & 0x01; /* set the data input line as desired */ - pgm->setpin(pgm, PIN_AVR_MOSI, b); + pgm->setpin(pgm, PIN_AVR_SDO, b); pgm->setpin(pgm, PIN_AVR_SCK, 1); @@ -194,7 +194,7 @@ static unsigned char bitbang_txrx(const PROGRAMMER *pgm, unsigned char byte) { * read the result bit (it is either valid from a previous falling * edge or it is ignored in the current context) */ - r = pgm->getpin(pgm, PIN_AVR_MISO); + r = pgm->getpin(pgm, PIN_AVR_SDI); pgm->setpin(pgm, PIN_AVR_SCK, 0); @@ -208,7 +208,7 @@ static int bitbang_tpi_clk(const PROGRAMMER *pgm) { unsigned char r = 0; pgm->setpin(pgm, PIN_AVR_SCK, 1); - r = pgm->getpin(pgm, PIN_AVR_MISO); + r = pgm->getpin(pgm, PIN_AVR_SDI); pgm->setpin(pgm, PIN_AVR_SCK, 0); @@ -220,7 +220,7 @@ void bitbang_tpi_tx(const PROGRAMMER *pgm, unsigned char byte) { unsigned char b, parity; /* start bit */ - pgm->setpin(pgm, PIN_AVR_MOSI, 0); + pgm->setpin(pgm, PIN_AVR_SDO, 0); bitbang_tpi_clk(pgm); parity = 0; @@ -229,16 +229,16 @@ void bitbang_tpi_tx(const PROGRAMMER *pgm, unsigned char byte) { parity ^= b; /* set the data input line as desired */ - pgm->setpin(pgm, PIN_AVR_MOSI, b); + pgm->setpin(pgm, PIN_AVR_SDO, b); bitbang_tpi_clk(pgm); } /* parity bit */ - pgm->setpin(pgm, PIN_AVR_MOSI, parity); + pgm->setpin(pgm, PIN_AVR_SDO, parity); bitbang_tpi_clk(pgm); /* 2 stop bits */ - pgm->setpin(pgm, PIN_AVR_MOSI, 1); + pgm->setpin(pgm, PIN_AVR_SDO, 1); bitbang_tpi_clk(pgm); bitbang_tpi_clk(pgm); } @@ -248,7 +248,7 @@ int bitbang_tpi_rx(const PROGRAMMER *pgm) { unsigned char b, rbyte, parity; /* make sure pin is on for "pullup" */ - pgm->setpin(pgm, PIN_AVR_MOSI, 1); + pgm->setpin(pgm, PIN_AVR_SDO, 1); /* wait for start bit (up to 10 bits) */ b = 1; @@ -517,7 +517,7 @@ int bitbang_initialize(const PROGRAMMER *pgm, const AVRPART *p) { pgm->powerup(pgm); usleep(20000); - /* TPIDATA is a single line, so MISO & MOSI should be connected */ + /* TPIDATA is a single line, so SDI & SDO should be connected */ if (p->prog_modes & PM_TPI) { /* make sure cmd_tpi() is defined */ if (pgm->cmd_tpi == NULL) { @@ -532,20 +532,20 @@ int bitbang_initialize(const PROGRAMMER *pgm, const AVRPART *p) { /* RESET must be LOW in case the existing code is driving the TPI pins: */ pgm->setpin(pgm, PIN_AVR_RESET, 0); - msg_notice2("doing MOSI-MISO link check\n"); + msg_notice2("doing SDO-SDI link check\n"); - pgm->setpin(pgm, PIN_AVR_MOSI, 0); - if (pgm->getpin(pgm, PIN_AVR_MISO) != 0) { - pmsg_error("MOSI->MISO 0 failed\n"); + pgm->setpin(pgm, PIN_AVR_SDO, 0); + if (pgm->getpin(pgm, PIN_AVR_SDI) != 0) { + pmsg_error("SDO->SDI 0 failed\n"); return -1; } - pgm->setpin(pgm, PIN_AVR_MOSI, 1); - if (pgm->getpin(pgm, PIN_AVR_MISO) != 1) { - pmsg_error("MOSI->MISO 1 failed\n"); + pgm->setpin(pgm, PIN_AVR_SDO, 1); + if (pgm->getpin(pgm, PIN_AVR_SDI) != 1) { + pmsg_error("SDO->SDI 1 failed\n"); return -1; } - msg_notice2("MOSI-MISO link present\n"); + msg_notice2("SDO-SDI link present\n"); } pgm->setpin(pgm, PIN_AVR_SCK, 0); @@ -554,7 +554,7 @@ int bitbang_initialize(const PROGRAMMER *pgm, const AVRPART *p) { if (p->prog_modes & PM_TPI) { /* keep TPIDATA high for 16 clock cycles */ - pgm->setpin(pgm, PIN_AVR_MOSI, 1); + pgm->setpin(pgm, PIN_AVR_SDO, 1); for (i = 0; i < 16; i++) pgm->highpulsepin(pgm, PIN_AVR_SCK); @@ -626,9 +626,9 @@ int bitbang_check_prerequisites(const PROGRAMMER *pgm) { return -1; if (verify_pin_assigned(pgm, PIN_AVR_SCK, "AVR SCK") < 0) return -1; - if (verify_pin_assigned(pgm, PIN_AVR_MISO, "AVR MISO") < 0) + if (verify_pin_assigned(pgm, PIN_AVR_SDI, "AVR SDI") < 0) return -1; - if (verify_pin_assigned(pgm, PIN_AVR_MOSI, "AVR MOSI") < 0) + if (verify_pin_assigned(pgm, PIN_AVR_SDO, "AVR SDO") < 0) return -1; if (pgm->cmd == NULL) { diff --git a/src/buspirate.c b/src/buspirate.c index 69328950..3df31642 100644 --- a/src/buspirate.c +++ b/src/buspirate.c @@ -25,8 +25,8 @@ * GND <-> GND * +5V <-> Vcc * CS <-> RESET - * MOSI <-> MOSI - * MISO <-> MISO + * SDO <-> SDO + * SDI <-> SDI * SCL/CLK <-> SCK * ( AUX <-> XTAL1 ) * @@ -1168,12 +1168,12 @@ static void buspirate_bb_enable(PROGRAMMER *pgm, const AVRPART *p) { PDATA(pgm)->flag |= BP_FLAG_IN_BINMODE; /* Set pin directions and an initial pin status (all high) */ - PDATA(pgm)->pin_dir = 0x12; /* AUX, MISO input; everything else output */ + PDATA(pgm)->pin_dir = 0x12; /* AUX, SDI input; everything else output */ buf[0] = PDATA(pgm)->pin_dir | 0x40; buspirate_send_bin(pgm, buf, 1); buspirate_recv_bin(pgm, buf, 1); - PDATA(pgm)->pin_val = 0x3f; /* PULLUP, AUX, MOSI, CLK, MISO, CS high */ + PDATA(pgm)->pin_val = 0x3f; /* PULLUP, AUX, SDO, CLK, SDI, CS high */ buf[0] = PDATA(pgm)->pin_val | 0x80; buspirate_send_bin(pgm, buf, 1); buspirate_recv_bin(pgm, buf, 1); @@ -1186,15 +1186,15 @@ static void buspirate_bb_enable(PROGRAMMER *pgm, const AVRPART *p) { Direction: 010xxxxx Input (1) or output (0): - AUX|MOSI|CLK|MISO|CS + AUX|SDO|CLK|SDI|CS Output value: 1xxxxxxx High (1) or low(0): - 1|POWER|PULLUP|AUX|MOSI|CLK|MISO|CS + 1|POWER|PULLUP|AUX|SDO|CLK|SDI|CS Both respond with a byte with current status: - 0|POWER|PULLUP|AUX|MOSI|CLK|MISO|CS + 0|POWER|PULLUP|AUX|SDO|CLK|SDI|CS */ static int buspirate_bb_getpin(const PROGRAMMER *pgm, int pinfunc) { unsigned char buf[10]; diff --git a/src/config.c b/src/config.c index a0cf35cf..ba31ceee 100644 --- a/src/config.c +++ b/src/config.c @@ -70,6 +70,8 @@ Component_t avr_comp[] = { part_comp_desc(mcuid, COMP_INT), part_comp_desc(n_interrupts, COMP_INT), part_comp_desc(n_page_erase, COMP_INT), + part_comp_desc(n_boot_sections, COMP_INT), + part_comp_desc(boot_section_size, COMP_INT), // AVRMEM mem_comp_desc(n_word_writes, COMP_INT), diff --git a/src/config_gram.y b/src/config_gram.y index 23018490..a90d2373 100644 --- a/src/config_gram.y +++ b/src/config_gram.y @@ -100,8 +100,8 @@ static int pin_name; %token K_MAX_WRITE_DELAY %token K_MCU_BASE %token K_MIN_WRITE_DELAY -%token K_MISO -%token K_MOSI +%token K_SDI +%token K_SDO %token K_NUM_PAGES %token K_NVM_BASE %token K_OCD_BASE @@ -662,8 +662,8 @@ prog_parm_pins: K_BUFF TKN_EQUAL {pin_name = PPI_AVR_BUFF; } pin_list | K_RESET TKN_EQUAL {pin_name = PIN_AVR_RESET;} pin_number { free_token($1); } | K_SCK TKN_EQUAL {pin_name = PIN_AVR_SCK; } pin_number { free_token($1); } | - K_MOSI TKN_EQUAL {pin_name = PIN_AVR_MOSI; } pin_number | - K_MISO TKN_EQUAL {pin_name = PIN_AVR_MISO; } pin_number | + K_SDO TKN_EQUAL {pin_name = PIN_AVR_SDO; } pin_number | + K_SDI TKN_EQUAL {pin_name = PIN_AVR_SDI; } pin_number | K_ERRLED TKN_EQUAL {pin_name = PIN_LED_ERR; } pin_number | K_RDYLED TKN_EQUAL {pin_name = PIN_LED_RDY; } pin_number | K_PGMLED TKN_EQUAL {pin_name = PIN_LED_PGM; } pin_number | diff --git a/src/developer_opts.c b/src/developer_opts.c index b6fd722e..5f25b654 100644 --- a/src/developer_opts.c +++ b/src/developer_opts.c @@ -615,7 +615,7 @@ static void dev_part_strct(const AVRPART *p, bool tsv, const AVRPART *base, bool dev_print_comment(cp->comms); if(p->parent_id && *p->parent_id) - dev_info("part parent %s\n", p->parent_id); + dev_info("part parent \"%s\"\n", p->parent_id); else dev_info("part\n"); } @@ -627,6 +627,8 @@ static void dev_part_strct(const AVRPART *p, bool tsv, const AVRPART *base, bool _if_partout(intcmp, "%d", mcuid); _if_partout(intcmp, "%d", n_interrupts); _if_partout(intcmp, "%d", n_page_erase); + _if_partout(intcmp, "%d", n_boot_sections); + _if_partout(intcmp, "%d", boot_section_size); _if_partout(intcmp, "%d", hvupdi_variant); _if_partout(intcmp, "0x%02x", stk500_devcode); _if_partout(intcmp, "0x%02x", avr910_devcode); diff --git a/src/doc/avrdude.texi b/src/doc/avrdude.texi index 672c7a98..539e9b4c 100644 --- a/src/doc/avrdude.texi +++ b/src/doc/avrdude.texi @@ -163,9 +163,10 @@ emulated on top of USB is likely to not work at all, or to work abysmally slow. If you happen to have a Linux system with at least 4 hardware GPIOs -available (like almost all embedded Linux boards) you can do without -any additional hardware - just connect them to the MOSI, MISO, RESET -and SCK pins on the AVR and use the linuxgpio programmer type. It bitbangs +available (like almost all embedded Linux boards) you can do without any +additional hardware - just connect them to the SDO, SDI, RESET and SCK +pins of the AVR's SPI interface and use the linuxgpio programmer +type. Older boards might use the labels MOSI for SDO and MISO for SDI. It bitbangs the lines using the Linux sysfs GPIO interface. Of course, care should be taken about voltage level compatibility. Also, although not strictly required, it is strongly advisable to protect the GPIO pins from @@ -180,7 +181,7 @@ programmer type can be used to directly connect to and program a chip using the built in interfaces on the computer. The requirements to use this type are that an SPI interface is exposed along with one GPIO pin. The GPIO serves as the reset output since the Linux SPI drivers -do not hold slave select down when a transfer is not occuring and thus +do not hold chip select down when a transfer is not occuring and thus it cannot be used as the reset pin. A readily available level translator should be used between the SPI bus/reset GPIO and the chip to avoid potentially damaging the computer's SPI controller in the @@ -195,7 +196,7 @@ the level translator to protect the hardware from damage. On a Raspberry Pi, header J8 provides access to the SPI and GPIO lines. -Typically, pins 19, 21, and 23 are SPI MOSI, MISO, and SCK, while +Typically, pins 19, 21, and 23 are SPI SDO, SDI, and SCK, while pins 24 and 26 would serve as CE outputs. So, close to these pins is pin 22 as GPIO25 which can be used as /RESET, and pin 25 can be used as GND. @@ -204,10 +205,10 @@ A typical programming cable would then look like: @multitable @columnfractions .15 .15 .3 @item @code{J8 pin} @tab @code{ISP pin} @tab @code{Name} -@item @code{21} @tab @code{1} @tab @code{MISO} +@item @code{21} @tab @code{1} @tab @code{SDI} @item @code{-} @tab @code{2} @tab @code{Vcc - leave open} @item @code{23} @tab @code{3} @tab @code{SCK} -@item @code{19} @tab @code{4} @tab @code{MOSI} +@item @code{19} @tab @code{4} @tab @code{SDO} @item @code{22} @tab @code{5} @tab @code{/RESET} @item @code{25} @tab @code{6} @tab @code{GND} @end multitable @@ -223,7 +224,7 @@ programmers communicate through the USB, using @code{libusb} as a platform abstraction layer. The avrftdi adds support for the FT2232C/D, FT2232H, and FT4232H devices. These all use the MPSSE mode, which has a specific pin mapping. Bit 1 (the lsb of the byte in the config -file) is SCK. Bit 2 is MOSI, and Bit 3 is MISO. Bit 4 usually reset. The 2232C/D parts +file) is SCK. Bit 2 is SDO, and Bit 3 is SDI. Bit 4 usually reset. The 2232C/D parts are only supported on interface A, but the H parts can be either A or B (specified by the usbdev config parameter). The STK500, STK600, JTAG ICE, and avr910 contain on-board logic to control the programming of the target @@ -947,7 +948,7 @@ The BusPirate programmer type accepts the following extended parameters: @item @samp{reset=cs,aux,aux2} The default setup assumes the BusPirate's CS output pin connected to the RESET pin on AVR side. It is however possible to have multiple AVRs -connected to the same BP with MISO, MOSI and SCK lines common for all of them. +connected to the same BP with SDI, SDO and SCK lines common for all of them. In such a case one AVR should have its RESET connected to BusPirate's @emph{CS} pin, second AVR's RESET connected to BusPirate's @@ -1075,7 +1076,7 @@ Connection to the PICkit2 programmer: @item @code{RST} @tab @code{VPP/MCLR (1) } @item @code{VDD} @tab @code{VDD Target (2) -- possibly optional if AVR self powered } @item @code{GND} @tab @code{GND (3) } -@item @code{MISO} @tab @code{PGD (4) } +@item @code{SDI} @tab @code{PGD (4) } @item @code{SCLK} @tab @code{PDC (5) } @item @code{OSI} @tab @code{AUX (6) } @end multitable @@ -1518,9 +1519,9 @@ command. When using direct SPI mode, up to 3 bytes can be omitted. @item spi -Enter direct SPI mode. The @emph{pgmled} pin acts as slave select. +Enter direct SPI mode. The @emph{pgmled} pin acts as chip select. @emph{Only supported on parallel bitbang programmers, and partially by USBtiny.} -Slave Select must be externally held low for direct SPI when +Chip Select must be externally held low for direct SPI when using USBtinyISP, and send must be a multiple of four bytes. @item pgm @@ -1538,12 +1539,12 @@ selected by the optional parameter @var{channel} (either 0 or 1). @item fosc @var{freq}[@code{M}|@code{k}] -Set the master oscillator to @var{freq} Hz. +Set the programming oscillator to @var{freq} Hz. An optional trailing letter @code{M} multiplies by 1E6, a trailing letter @code{k} by 1E3. @item fosc off -Turn the master oscillator off. +Turn the programming oscillator off. @item sck @var{period} @emph{STK500 and STK600 only:} @@ -1558,7 +1559,7 @@ ISP clock period when operating the ICE in ISP mode. @item parms @emph{STK500 and STK600 only:} -Display the current voltage and master oscillator parameters. +Display the current voltage and programming oscillator parameters. @emph{JTAG ICE only:} Display the current target supply voltage and JTAG bit clock rate/period. @@ -1799,8 +1800,8 @@ programmer buff = [, ... ] ; # pin number(s) reset = ; # pin number sck = ; # pin number - mosi = ; # pin number - miso = ; # pin number + sdo = ; # pin number + sdi = ; # pin number errled = ; # pin number rdyled = ; # pin number pgmled = ; # pin number @@ -1866,6 +1867,8 @@ part mcuid = ; # unique id in 0..2039 for 8-bit AVRs n_interrupts = ; # number of interrupts, used for vector bootloaders n_page_erase = ; # if set, number of pages erased during SPM erase + n_boot_sections = ; # Number of boot sections + boot_section_size = ; # Size of (smallest) boot section, if any hvupdi_variant = ; # numeric -1 (n/a) or 0..2 devicecode = ; # deprecated, use stk500_devcode stk500_devcode = ; # numeric @@ -2957,10 +2960,10 @@ Solution: Use the 6 pin ISP header on the Dragon and the following pin mapping: @multitable @columnfractions .2 .2 @item @strong{Dragon} @tab @strong{Target} @item @strong{ISP Header} @tab @strong{pins} -@item 1 (MISO) @tab PDI_DATA +@item 1 (SDI) @tab PDI_DATA @item 2 (VCC) @tab VCC @item 3 (SCK) @tab -@item 4 (MOSI) @tab +@item 4 (SDO) @tab @item 5 (RESET) @tab PDI_CLK / RST @item 6 (GND) @tab GND @end multitable @@ -2974,10 +2977,10 @@ Solution: Use the following pin mapping: @multitable @columnfractions .2 .2 .2 @item @strong{AVRISP} @tab @strong{Target} @tab @strong{ATtiny} @item @strong{connector} @tab @strong{pins} @tab @strong{pin #} -@item 1 (MISO) @tab TPIDATA @tab 1 +@item 1 (SDI) @tab TPIDATA @tab 1 @item 2 (VTref) @tab Vcc @tab 5 @item 3 (SCK) @tab TPICLK @tab 3 -@item 4 (MOSI) @tab @tab +@item 4 (SDO) @tab @tab @item 5 (RESET) @tab /RESET @tab 6 @item 6 (GND) @tab GND @tab 2 @end multitable @@ -2987,10 +2990,10 @@ Problem: I want to program an ATtiny4/5/9/10 device using a serial/parallel bitbang programmer. How to connect the pins? Solution: Since TPI has only 1 pin for bi-directional data transfer, both -@var{MISO} and @var{MOSI} pins should be connected to the @var{TPIDATA} pin +@var{SDI} and @var{SDO} pins should be connected to the @var{TPIDATA} pin on the ATtiny device. -However, a 1K resistor should be placed between the @var{MOSI} and @var{TPIDATA}. -The @var{MISO} pin connects to @var{TPIDATA} directly. +However, a 1K resistor should be placed between the @var{SDO} and @var{TPIDATA}. +The @var{SDI} pin connects to @var{TPIDATA} directly. The @var{SCK} pin is connected to @var{TPICLK}. In addition, the @var{Vcc}, @var{/RESET} and @var{GND} pins should @@ -3008,12 +3011,12 @@ front of pins 7, 4, 3 and 8): @example programmer id = "dasa_ftdi"; - desc = "serial port banging, reset=rts sck=dtr mosi=txd miso=cts"; + desc = "serial port banging, reset=rts sck=dtr sdo=txd sdi=cts"; type = serbb; reset = ~7; sck = ~4; - mosi = ~3; - miso = ~8; + sdo = ~3; + sdi = ~8; ; @end example diff --git a/src/ft245r.c b/src/ft245r.c index 900bef5a..8eab7d6f 100644 --- a/src/ft245r.c +++ b/src/ft245r.c @@ -25,9 +25,9 @@ /* ft245r -- FT245R/FT232R Synchronous BitBangMode Programmer default pin assign FT232R / FT245R - miso = 1; # RxD / D1 + sdi = 1; # RxD / D1 sck = 0; # RTS / D0 - mosi = 2; # TxD / D2 + sdo = 2; # TxD / D2 reset = 4; # DTR / D4 */ @@ -548,7 +548,7 @@ static int ft245r_initialize(const PROGRAMMER *pgm, const AVRPART *p) { set_reset(pgm, OFF); /* Wait for at least 20 ms and enable serial programming by sending the Programming - * Enable serial instruction to pin MOSI. + * Enable serial instruction to pin SDO. */ ft245r_usleep(pgm, 20000); // 20ms @@ -557,35 +557,35 @@ static int ft245r_initialize(const PROGRAMMER *pgm, const AVRPART *p) { uint8_t byte; int i; - /* Since there is a single TPIDATA line, MOSI and MISO must be + /* Since there is a single TPIDATA line, SDO and SDI must be linked together through a 1kOhm resistor. Verify that - everything we send on MOSI gets mirrored back on MISO. */ - set_pin(pgm, PIN_AVR_MOSI, 0); - if (get_pin(pgm, PIN_AVR_MISO) != 0) { + everything we send on SDO gets mirrored back on SDI. */ + set_pin(pgm, PIN_AVR_SDO, 0); + if (get_pin(pgm, PIN_AVR_SDI) != 0) { io_link_ok = false; if(ovsigck) { - pmsg_warning("MOSI->MISO 0 failed\n"); + pmsg_warning("SDO->SDI 0 failed\n"); } else { - pmsg_error("MOSI->MISO 0 failed\n"); + pmsg_error("SDO->SDI 0 failed\n"); return -1; } } - set_pin(pgm, PIN_AVR_MOSI, 1); - if (get_pin(pgm, PIN_AVR_MISO) != 1) { + set_pin(pgm, PIN_AVR_SDO, 1); + if (get_pin(pgm, PIN_AVR_SDI) != 1) { io_link_ok = false; if(ovsigck) { - pmsg_warning("MOSI->MISO 1 failed\n"); + pmsg_warning("SDO->SDI 1 failed\n"); } else { - pmsg_error("MOSI->MISO 1 failed\n"); + pmsg_error("SDO->SDI 1 failed\n"); return -1; } } if (io_link_ok) - msg_notice2("MOSI-MISO link present\n"); + msg_notice2("SDO-SDI link present\n"); /* keep TPIDATA high for 16 clock cycles */ - set_pin(pgm, PIN_AVR_MOSI, 1); + set_pin(pgm, PIN_AVR_SDO, 1); for (i = 0; i < 16; i++) { set_sck(pgm, 1); set_sck(pgm, 0); @@ -608,7 +608,7 @@ static int ft245r_initialize(const PROGRAMMER *pgm, const AVRPART *p) { static inline void add_bit(const PROGRAMMER *pgm, unsigned char *buf, int *buf_pos, uint8_t bit) { - ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_MOSI, bit); + ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_SDO, bit); ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_SCK,0); buf[*buf_pos] = ft245r_out; (*buf_pos)++; @@ -632,14 +632,14 @@ static inline int set_data(const PROGRAMMER *pgm, unsigned char *buf, unsigned c static inline unsigned char extract_data(const PROGRAMMER *pgm, unsigned char *buf, int offset) { int j; - int buf_pos = FT245R_CYCLES; /* MISO data is valid AFTER rising SCK edge, + int buf_pos = FT245R_CYCLES; /* SDI data is valid AFTER rising SCK edge, i.e. in next clock cycle */ unsigned char bit = 0x80; unsigned char r = 0; buf += offset * (8 * FT245R_CYCLES); for (j=0; j<8; j++) { - if (GET_BITS_0(buf[buf_pos],pgm,PIN_AVR_MISO)) { + if (GET_BITS_0(buf[buf_pos],pgm,PIN_AVR_SDI)) { r |= bit; } buf_pos += FT245R_CYCLES; @@ -658,7 +658,7 @@ static inline unsigned char extract_data_out(const PROGRAMMER *pgm, unsigned cha buf += offset * (8 * FT245R_CYCLES); for (j=0; j<8; j++) { - if (GET_BITS_0(buf[buf_pos],pgm,PIN_AVR_MOSI)) { + if (GET_BITS_0(buf[buf_pos],pgm,PIN_AVR_SDO)) { r |= bit; } buf_pos += FT245R_CYCLES; @@ -702,7 +702,7 @@ static inline uint8_t extract_tpi_data(const PROGRAMMER *pgm, unsigned char *buf for (j = 0; j < 8; j++) { (*buf_pos)++; // skip over falling clock edge - if (GET_BITS_0(buf[(*buf_pos)++], pgm, PIN_AVR_MISO)) + if (GET_BITS_0(buf[(*buf_pos)++], pgm, PIN_AVR_SDI)) byte |= bit; bit <<= 1; } @@ -747,7 +747,7 @@ static int ft245r_tpi_rx(const PROGRAMMER *pgm, uint8_t *bytep) { uint32_t res, m, byte; /* Allow for up to 4 bits before we must see start bit; during - that time, we must keep the MOSI line high. */ + that time, we must keep the SDO line high. */ for (i = 0; i < 2; ++i) len += set_data(pgm, &buf[len], 0xff); @@ -815,8 +815,8 @@ static const struct pindef_t valid_pins = {{0xff},{0xff}} ; static const struct pin_checklist_t pin_checklist[] = { { PIN_AVR_SCK, 1, &valid_pins}, - { PIN_AVR_MOSI, 1, &valid_pins}, - { PIN_AVR_MISO, 1, &valid_pins}, + { PIN_AVR_SDO, 1, &valid_pins}, + { PIN_AVR_SDI, 1, &valid_pins}, { PIN_AVR_RESET,1, &valid_pins}, { PPI_AVR_BUFF, 0, &valid_pins}, }; @@ -889,7 +889,7 @@ static int ft245r_open(PROGRAMMER *pgm, const char *port) { ft245r_ddr = pgm->pin[PIN_AVR_SCK].mask[0] - | pgm->pin[PIN_AVR_MOSI].mask[0] + | pgm->pin[PIN_AVR_SDO].mask[0] | pgm->pin[PIN_AVR_RESET].mask[0] | pgm->pin[PPI_AVR_BUFF].mask[0] | pgm->pin[PPI_AVR_VCC].mask[0] @@ -902,7 +902,7 @@ static int ft245r_open(PROGRAMMER *pgm, const char *port) { ft245r_out = 0; ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_RESET,1); ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_SCK,0); - ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_MOSI,0); + ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_AVR_SDO,0); ft245r_out = SET_BITS_0(ft245r_out,pgm,PPI_AVR_BUFF,0); ft245r_out = SET_BITS_0(ft245r_out,pgm,PPI_AVR_VCC,0); ft245r_out = SET_BITS_0(ft245r_out,pgm,PIN_LED_ERR,0); diff --git a/src/jtagmkII.c b/src/jtagmkII.c index 2f6425cf..6cc5e01f 100644 --- a/src/jtagmkII.c +++ b/src/jtagmkII.c @@ -247,10 +247,9 @@ u16_to_b2(unsigned char *b, unsigned short l) static const char * jtagmkII_get_rc(unsigned int rc) { - int i; static char msg[64]; - for (i = 0; i < sizeof jtagresults / sizeof jtagresults[0]; i++) + for (size_t i = 0; i < sizeof jtagresults/sizeof*jtagresults; i++) if (jtagresults[i].code == rc) return jtagresults[i].descr; @@ -261,7 +260,7 @@ jtagmkII_get_rc(unsigned int rc) static void jtagmkII_print_memory(unsigned char *b, size_t s) { - int i; + size_t i; if (s < 2) return; @@ -277,8 +276,8 @@ static void jtagmkII_print_memory(unsigned char *b, size_t s) msg_info("\n"); } -static void jtagmkII_prmsg(const PROGRAMMER *pgm, unsigned char *data, size_t len) { - int i; +static void jtagmkII_prmsg(const PROGRAMMER *pgm_unused, unsigned char *data, size_t len) { + size_t i; if (verbose >= 4) { msg_trace("Raw message:\n"); @@ -885,7 +884,7 @@ static int jtagmkII_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { /* * There is no chip erase functionality in debugWire mode. */ -static int jtagmkII_chip_erase_dw(const PROGRAMMER *pgm, const AVRPART *p) { +static int jtagmkII_chip_erase_dw(const PROGRAMMER *pgm_unused, const AVRPART *p_unused) { pmsg_info("chip erase not supported in debugWire mode\n"); @@ -896,7 +895,7 @@ static void jtagmkII_set_devdescr(const PROGRAMMER *pgm, const AVRPART *p) { int status; unsigned char *resp, c; LNODEID ln; - AVRMEM * m; + AVRMEM *flm; struct { unsigned char cmd; struct device_descriptor dd; @@ -907,13 +906,18 @@ static void jtagmkII_set_devdescr(const PROGRAMMER *pgm, const AVRPART *p) { sendbuf.dd.ucSPMCRAddress = p->spmcr; sendbuf.dd.ucRAMPZAddress = p->rampz; sendbuf.dd.ucIDRAddress = p->idr; + if((flm = avr_locate_mem(p, "flash")) && p->boot_section_size > 0) { + unsigned int sbls = (flm->size - p->boot_section_size)/2; // Words + sendbuf.dd.uiStartSmallestBootLoaderSection[0] = sbls; + sendbuf.dd.uiStartSmallestBootLoaderSection[1] = sbls>>8; + } u16_to_b2(sendbuf.dd.EECRAddress, p->eecr? p->eecr: 0x3f); // Unset eecr means 0x3f sendbuf.dd.ucAllowFullPageBitstream = (p->flags & AVRPART_ALLOWFULLPAGEBITSTREAM) != 0; sendbuf.dd.EnablePageProgramming = (p->flags & AVRPART_ENABLEPAGEPROGRAMMING) != 0; for (ln = lfirst(p->mem); ln; ln = lnext(ln)) { - m = ldata(ln); + AVRMEM *m = ldata(ln); if (strcmp(m->desc, "flash") == 0) { if (m->page_size > 256) PDATA(pgm)->flash_pagesize = 256; @@ -1071,7 +1075,7 @@ static int jtagmkII_reset(const PROGRAMMER *pgm, unsigned char flags) { return 0; } -static int jtagmkII_program_enable_INFO(const PROGRAMMER *pgm, const AVRPART *p) { +static int jtagmkII_program_enable_INFO(const PROGRAMMER *pgm_unused, const AVRPART *p_unused) { return 0; } @@ -1197,9 +1201,8 @@ static unsigned char jtagmkII_get_baud(long baud) { 2000000L, PAR_BAUD_2000000 }, { 3000000L, PAR_BAUD_3000000 }, }; - int i; - for (i = 0; i < sizeof baudtab / sizeof baudtab[0]; i++) + for (size_t i = 0; i < sizeof baudtab/sizeof*baudtab; i++) if (baud == baudtab[i].baud) return baudtab[i].val; @@ -1364,7 +1367,7 @@ static void jtagmkII_disable(const PROGRAMMER *pgm) { (void)jtagmkII_program_disable(pgm); } -static void jtagmkII_enable(PROGRAMMER * pgm, const AVRPART *p) { +static void jtagmkII_enable(PROGRAMMER *pgm_unused, const AVRPART *p_unused) { return; } @@ -2983,7 +2986,7 @@ static int jtagmkII_initialize32(const PROGRAMMER *pgm, const AVRPART *p) { return 0; } -static int jtagmkII_chip_erase32(const PROGRAMMER *pgm, const AVRPART *p) { +static int jtagmkII_chip_erase32(const PROGRAMMER *pgm, const AVRPART *p_unused) { int status=0, loops; unsigned char *resp, buf[3], x, ret[4], *retP; unsigned long val=0; @@ -3248,10 +3251,9 @@ static void jtagmkII_close32(PROGRAMMER * pgm) goto ret; } -static int jtagmkII_paged_load32(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, - unsigned int page_size, - unsigned int addr, unsigned int n_bytes) -{ +static int jtagmkII_paged_load32(const PROGRAMMER *pgm, const AVRPART *p_unused, const AVRMEM *m, + unsigned int page_size, unsigned int addr, unsigned int n_bytes) { + unsigned int block_size; unsigned int maxaddr = addr + n_bytes; unsigned char cmd[7]; @@ -3284,7 +3286,8 @@ static int jtagmkII_paged_load32(const PROGRAMMER *pgm, const AVRPART *p, const cmd[2] = 0x05; for (; addr < maxaddr; addr += block_size) { - block_size = ((maxaddr-addr) < pgm->page_size) ? (maxaddr - addr) : pgm->page_size; + block_size = maxaddr - addr < (unsigned int) pgm->page_size? + maxaddr - addr: (unsigned int) pgm->page_size; pmsg_debug("jtagmkII_paged_load32(): " "block_size at addr %d is %d\n", addr, block_size); @@ -3323,10 +3326,9 @@ static int jtagmkII_paged_load32(const PROGRAMMER *pgm, const AVRPART *p, const return -1; } -static int jtagmkII_paged_write32(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, - unsigned int page_size, - unsigned int addr, unsigned int n_bytes) -{ +static int jtagmkII_paged_write32(const PROGRAMMER *pgm, const AVRPART *p_unused , const AVRMEM *m, + unsigned int page_size, unsigned int addr, unsigned int n_bytes) { + unsigned int block_size; unsigned char *cmd=NULL; unsigned char *resp; @@ -3383,7 +3385,8 @@ static int jtagmkII_paged_write32(const PROGRAMMER *pgm, const AVRPART *p, const if(status != 0) {lineno = __LINE__; goto eRR;} for(blocks=0; blocks<2; ++blocks) { - block_size = ((maxaddr-addr) < pgm->page_size) ? (maxaddr - addr) : pgm->page_size; + block_size = maxaddr - addr < (unsigned int) pgm->page_size? + maxaddr - addr: (unsigned int) pgm->page_size; pmsg_debug("jtagmkII_paged_write32(): " "block_size at addr %d is %d\n", addr, block_size); diff --git a/src/lexer.l b/src/lexer.l index b637c4b7..1d80594d 100644 --- a/src/lexer.l +++ b/src/lexer.l @@ -121,7 +121,9 @@ SIGN [+-] } -prog_modes|mcuid|n_interrupts|n_page_erase|n_word_writes { /* Components for assignment */ +(?x: prog_modes | mcuid | n_interrupts | n_page_erase | n_word_writes | n_boot_sections | + boot_section_size ) { /* Components for assignment */ + Component_t *cp = cfg_comp_search(yytext, current_strct); if(!cp) { yyerror("Unknown component %s in %s", yytext, cfg_strct_name(current_strct)); @@ -196,9 +198,9 @@ max_write_delay { yylval=NULL; ccap(); return K_MAX_WRITE_DELAY; } mcu_base { yylval=NULL; ccap(); return K_MCU_BASE; } memory { yylval=NULL; ccap(); return K_MEMORY; } min_write_delay { yylval=NULL; ccap(); return K_MIN_WRITE_DELAY; } -miso { yylval=NULL; ccap(); return K_MISO; } +miso { yylval=NULL; ccap(); return K_SDI; } // Deprecated mode { yylval=NULL; ccap(); return K_MODE; } -mosi { yylval=NULL; ccap(); return K_MOSI; } +mosi { yylval=NULL; ccap(); return K_SDO; } // Deprecated no { yylval=new_token(K_NO); return K_NO; } NULL { yylval=NULL; return K_NULL; } num_banks { yylval=NULL; return K_NUM_PAGES; } @@ -245,6 +247,8 @@ resetdelayms { yylval=NULL; ccap(); return K_RESETDELAYMS; } resetdelayus { yylval=NULL; ccap(); return K_RESETDELAYUS; } retry_pulse { yylval=NULL; ccap(); return K_RETRY_PULSE; } sck { yylval=new_token(K_SCK); ccap(); return K_SCK; } +sdi { yylval=NULL; ccap(); return K_SDI; } +sdo { yylval=NULL; ccap(); return K_SDO; } serial { yylval=NULL; ccap(); return K_SERIAL; } signature { yylval=NULL; ccap(); return K_SIGNATURE; } size { yylval=NULL; ccap(); return K_SIZE; } diff --git a/src/libavrdude.h b/src/libavrdude.h index ddda1865..d9e84be1 100644 --- a/src/libavrdude.h +++ b/src/libavrdude.h @@ -237,6 +237,8 @@ typedef struct avrpart { int mcuid; /* Unique id in 0..2039 for urclock programmer */ int n_interrupts; /* Number of interrupts, used for vector bootloaders */ int n_page_erase; /* If set, number of pages erased during NVM erase */ + int n_boot_sections; /* Number of boot sections */ + int boot_section_size; /* Size of (smallest) boot section, if any */ int hvupdi_variant; /* HV pulse on UPDI pin, no pin or RESET pin */ int stk500_devcode; /* stk500 device code */ int avr910_devcode; /* avr910 device code */ @@ -401,8 +403,8 @@ enum { PPI_AVR_BUFF, PIN_AVR_RESET, PIN_AVR_SCK, - PIN_AVR_MOSI, - PIN_AVR_MISO, + PIN_AVR_SDO, + PIN_AVR_SDI, PIN_LED_ERR, PIN_LED_RDY, PIN_LED_PGM, @@ -830,10 +832,10 @@ void pgm_free(PROGRAMMER *p); void programmer_display(PROGRAMMER * pgm, const char * p); -/* show is a mask like this (1<pinno[i] & PIN_MASK) != 0 || i == PIN_AVR_RESET || i == PIN_AVR_SCK || - i == PIN_AVR_MOSI || - i == PIN_AVR_MISO ) { + i == PIN_AVR_SDO || + i == PIN_AVR_SDI ) { pin = pgm->pinno[i] & PIN_MASK; if ((r=linuxgpio_export(pin)) < 0) { pmsg_ext_error("cannot export GPIO %d, already exported/busy?: %s", @@ -290,7 +290,7 @@ static int linuxgpio_open(PROGRAMMER *pgm, const char *port) { * udev permission rule application after export */ for (retry_count = 0; retry_count < GPIO_SYSFS_OPEN_RETRIES; retry_count++) { usleep(GPIO_SYSFS_OPEN_DELAY); - if (i == PIN_AVR_MISO) + if (i == PIN_AVR_SDI) r=linuxgpio_dir_in(pin); else r=linuxgpio_dir_out(pin); @@ -307,7 +307,7 @@ static int linuxgpio_open(PROGRAMMER *pgm, const char *port) { if (retry_count) pmsg_notice2("needed %d retr%s for linuxgpio_dir_%s(%s)\n", retry_count, retry_count > 1? "ies": "y", - i == PIN_AVR_MISO? "in": "out", avr_pin_name(pin)); + i == PIN_AVR_SDI? "in": "out", avr_pin_name(pin)); if (r < 0) { linuxgpio_unexport(pin); diff --git a/src/linuxspi.c b/src/linuxspi.c index cebee554..e45ca687 100644 --- a/src/linuxspi.c +++ b/src/linuxspi.c @@ -335,7 +335,7 @@ static int linuxspi_program_enable(const PROGRAMMER *pgm, const AVRPART *p) { * plus two CPU clock cycles. See Table 25-5 on page 240 for definition of * minimum pulse width on RESET pin, t RST * 2. Wait for at least 20 ms and then enable serial programming by sending - * the Programming Enable serial instruction to the MOSI pin + * the Programming Enable serial instruction to the SDO pin * 3. The serial programming instructions will not work if the communication * is out of synchronization. When in sync, the second byte (0x53) will echo * back when issuing the third byte of the Programming Enable instruction diff --git a/src/pgm.c b/src/pgm.c index dca0ea87..34006d53 100644 --- a/src/pgm.c +++ b/src/pgm.c @@ -270,10 +270,10 @@ void pgm_display_generic_mask(const PROGRAMMER *pgm, const char *p, unsigned int msg_info("%s RESET = %s\n", p, pins_to_str(&pgm->pin[PIN_AVR_RESET])); if(show & (1<pin[PIN_AVR_SCK])); - if(show & (1<pin[PIN_AVR_MOSI])); - if(show & (1<pin[PIN_AVR_MISO])); + if(show & (1<pin[PIN_AVR_SDO])); + if(show & (1<pin[PIN_AVR_SDI])); if(show & (1<pin[PIN_LED_ERR])); if(show & (1<pin[PIN_AVR_SCK]), &(pgm->pinno[PIN_AVR_SCK])) < 0) return -1; - if (pin_fill_old_pinno(&(pgm->pin[PIN_AVR_MOSI]), &(pgm->pinno[PIN_AVR_MOSI])) < 0) + if (pin_fill_old_pinno(&(pgm->pin[PIN_AVR_SDO]), &(pgm->pinno[PIN_AVR_SDO])) < 0) return -1; - if (pin_fill_old_pinno(&(pgm->pin[PIN_AVR_MISO]), &(pgm->pinno[PIN_AVR_MISO])) < 0) + if (pin_fill_old_pinno(&(pgm->pin[PIN_AVR_SDI]), &(pgm->pinno[PIN_AVR_SDI])) < 0) return -1; if (pin_fill_old_pinno(&(pgm->pin[PIN_LED_ERR]), &(pgm->pinno[PIN_LED_ERR])) < 0) return -1; @@ -378,8 +378,8 @@ const char * avr_pin_name(int pinname) { case PPI_AVR_BUFF : return "BUFF"; case PIN_AVR_RESET : return "RESET"; case PIN_AVR_SCK : return "SCK"; - case PIN_AVR_MOSI : return "MOSI"; - case PIN_AVR_MISO : return "MISO"; + case PIN_AVR_SDO : return "SDO"; + case PIN_AVR_SDI : return "SDI"; case PIN_LED_ERR : return "ERRLED"; case PIN_LED_RDY : return "RDYLED"; case PIN_LED_PGM : return "PGMLED"; @@ -401,8 +401,8 @@ const char * avr_pin_lcname(int pinname) { case PPI_AVR_BUFF : return "buff"; case PIN_AVR_RESET : return "reset"; case PIN_AVR_SCK : return "sck"; - case PIN_AVR_MOSI : return "mosi"; - case PIN_AVR_MISO : return "miso"; + case PIN_AVR_SDO : return "sdo"; + case PIN_AVR_SDI : return "sdi"; case PIN_LED_ERR : return "errled"; case PIN_LED_RDY : return "rdyled"; case PIN_LED_PGM : return "pgmled"; diff --git a/src/stk500.c b/src/stk500.c index 7f26691a..b7788a59 100644 --- a/src/stk500.c +++ b/src/stk500.c @@ -1033,7 +1033,7 @@ static int stk500_set_fosc(const PROGRAMMER *pgm, double v) { /* This code assumes that each count of the SCK duration parameter - represents 8/f, where f is the clock frequency of the STK500 master + represents 8/f, where f is the clock frequency of the STK500 controller processors (not the target). This number comes from Atmel application note AVR061. It appears that the STK500 bit bangs SCK. For small duration values, the actual SCK width is larger than diff --git a/src/stk500v2.c b/src/stk500v2.c index a4cf943a..6a6085a1 100644 --- a/src/stk500v2.c +++ b/src/stk500v2.c @@ -1005,7 +1005,7 @@ static struct const char *description; } connection_status[] = { - { STATUS_CONN_FAIL_MOSI, "MOSI fail" }, + { STATUS_CONN_FAIL_SDO, "SDO fail" }, { STATUS_CONN_FAIL_RST, "RST fail" }, { STATUS_CONN_FAIL_SCK, "SCK fail" }, { STATUS_TGT_NOT_DETECTED, "Target not detected" }, @@ -3038,14 +3038,14 @@ static void stk500v2_display(const PROGRAMMER *pgm, const char *p) { stk500v2_getparm(pgm, PARAM_SW_MAJOR, &maj); stk500v2_getparm(pgm, PARAM_SW_MINOR, &min); msg_info("%sHardware Version: %d\n", p, hdw); - msg_info("%sFirmware Version Master : %d.%02d\n", p, maj, min); + msg_info("%sFirmware Version Controller : %d.%02d\n", p, maj, min); if (PDATA(pgm)->pgmtype == PGMTYPE_STK600) { - stk500v2_getparm(pgm, PARAM_SW_MAJOR_SLAVE1, &maj_s1); - stk500v2_getparm(pgm, PARAM_SW_MINOR_SLAVE1, &min_s1); - stk500v2_getparm(pgm, PARAM_SW_MAJOR_SLAVE2, &maj_s2); - stk500v2_getparm(pgm, PARAM_SW_MINOR_SLAVE2, &min_s2); - msg_info("%sFirmware Version Slave 1: %d.%02d\n", p, maj_s1, min_s1); - msg_info("%sFirmware Version Slave 2: %d.%02d\n", p, maj_s2, min_s2); + stk500v2_getparm(pgm, PARAM_SW_MAJOR_PERIPHERY1, &maj_s1); + stk500v2_getparm(pgm, PARAM_SW_MINOR_PERIPHERY1, &min_s1); + stk500v2_getparm(pgm, PARAM_SW_MAJOR_PERIPHERY2, &maj_s2); + stk500v2_getparm(pgm, PARAM_SW_MINOR_PERIPHERY2, &min_s2); + msg_info("%sFirmware Version Periphery 1: %d.%02d\n", p, maj_s1, min_s1); + msg_info("%sFirmware Version Periphery 2: %d.%02d\n", p, maj_s2, min_s2); } } diff --git a/src/stk500v2_private.h b/src/stk500v2_private.h index 5531a269..560f143e 100644 --- a/src/stk500v2_private.h +++ b/src/stk500v2_private.h @@ -141,7 +141,7 @@ // Status #define STATUS_ISP_READY 0x00 -#define STATUS_CONN_FAIL_MOSI 0x01 +#define STATUS_CONN_FAIL_SDO 0x01 #define STATUS_CONN_FAIL_RST 0x02 #define STATUS_CONN_FAIL_SCK 0x04 #define STATUS_TGT_NOT_DETECTED 0x10 @@ -149,8 +149,8 @@ // hw_status // Bits in status variable -// Bit 0-3: Slave MCU -// Bit 4-7: Master MCU +// Bit 0-3: Periphery MCU +// Bit 4-7: Controller MCU #define STATUS_AREF_ERROR 0 // Set to '1' if AREF is short circuited @@ -191,10 +191,10 @@ #define PARAM_SOCKETCARD_ID 0xA5 #define PARAM_ROUTINGCARD_ID 0xA6 #define PARAM_EXPCARD_ID 0xA7 -#define PARAM_SW_MAJOR_SLAVE1 0xA8 -#define PARAM_SW_MINOR_SLAVE1 0xA9 -#define PARAM_SW_MAJOR_SLAVE2 0xAA -#define PARAM_SW_MINOR_SLAVE2 0xAB +#define PARAM_SW_MAJOR_PERIPHERY1 0xA8 +#define PARAM_SW_MINOR_PERIPHERY1 0xA9 +#define PARAM_SW_MAJOR_PERIPHERY2 0xAA +#define PARAM_SW_MINOR_PERIPHERY2 0xAB #define PARAM_BOARD_ID_STATUS 0xAD #define PARAM_RESET 0xB4 diff --git a/src/update.c b/src/update.c index 0a7166cd..0afcd9ea 100644 --- a/src/update.c +++ b/src/update.c @@ -560,8 +560,7 @@ int do_op(const PROGRAMMER *pgm, const AVRPART *p, UPDATE *upd, enum updateflags pmsg_info("%d byte%s of %s%s written\n", fs.nbytes, update_plural(fs.nbytes), mem->desc, alias_mem_desc); - // Fall through for (default) auto verify, ie, unless -V was specified - if (!(flags & UF_VERIFY)) + if (!(flags & UF_VERIFY)) // Fall through for auto verify unless -V was specified break; case DEVICE_VERIFY: diff --git a/src/urclock.c b/src/urclock.c index 7bfb2d7f..3e03f193 100644 --- a/src/urclock.c +++ b/src/urclock.c @@ -1142,9 +1142,6 @@ static void guessblstart(const PROGRAMMER *pgm, const AVRPART *p) { { 2048, 0, 0x12ab8da0, 0xca46a3ca }, // ATmegaBOOT_168_diecimila.hex { 2048, 0, 0x3242ddd3, 0xf3e94dba }, // ATmegaBOOT_168_ng.hex { 2048, 0, 0x2eed30b3, 0x47d14ffa }, // ATmegaBOOT_168_pro_8MHz.hex - { 4096, 0, 0xc52edd05, 0xa3371f94 }, // Caterina-LilyPadUSB.hex - { 4096, 0, 0x663b8f7e, 0x7efdda2b }, // Caterina-Robot-Control.hex - { 4096, 0, 0x3c6387e7, 0x7e96eea2 }, // Caterina-Robot-Motor.hex { 2048, 0, 0x1cef0d75, 0x6cfbac49 }, // LilyPadBOOT_168.hex { 1024, 1, 0x6ca0f37b, 0x31bae545 }, // bigboot_328.hex { 512, 0, 0x035cbc07, 0x24ba435e }, // optiboot_atmega168.hex @@ -1159,6 +1156,7 @@ static void guessblstart(const PROGRAMMER *pgm, const AVRPART *p) { { 256, 0, 0xaa62bafc, 0xaa62bafc }, // picobootArduino8v3rc1.hex { 256, 0, 0x56263965, 0x56263965 }, // picobootSTK500-168p.hex { 512, 0, 0x3242ddd3, 0x5ba5f5f6 }, // picobootSTK500-328p.hex + { 3072, 0, 0x3242ddd3, 0xd3347c5d }, // optiboot_lgt8f328p.hex }; uint8_t buf[4096], b128[128]; @@ -2260,14 +2258,14 @@ static int urclock_paged_load(const PROGRAMMER *pgm, const AVRPART *p, const AVR int urclock_write_byte(const PROGRAMMER *pgm_uu, const AVRPART *p_uu, const AVRMEM *mem, unsigned long addr_uu, unsigned char data_uu) { - pmsg_error("bootloader does not implement byte-wise write to %s \n", mem->desc); + pmsg_error("bootloader does not implement bytewise write to %s \n", mem->desc); return -1; } int urclock_read_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *mem, unsigned long addr, unsigned char *value) { - // Byte-wise read only valid for flash and eeprom + // Bytewise read only valid for flash and eeprom int mchr = avr_mem_is_flash_type(mem)? 'F': 'E'; if(mchr == 'E' && !avr_mem_is_eeprom_type(mem)) { if(!strcmp(mem->desc, "signature") && pgm->read_sig_bytes) { @@ -2496,8 +2494,9 @@ void urclock_initpgm(PROGRAMMER *pgm) { disable_trailing_ff_removal(); #if defined(HAVE_LIBREADLINE) - pmsg_notice2("libreadline is used; avrdude -t -c urclock should work"); + pmsg_notice2("libreadline is used; avrdude -t -c urclock should work interactively\n"); #else - pmsg_warning("compiled without readline library, cannot use avrdude -t -c urclock"); + pmsg_warning("compiled without readline library, cannot use avrdude -t -c urclock interactively\n"); + imsg_warning("but it is still possible to pipe: echo \"d fl 0 32; quit\" | tr \\; \\\\n | avrdude -t -curclock\n"); #endif } diff --git a/src/usbtiny.c b/src/usbtiny.c index 2063f89b..a69de8f3 100644 --- a/src/usbtiny.c +++ b/src/usbtiny.c @@ -445,10 +445,10 @@ static int usbtiny_initialize (const PROGRAMMER *pgm, const AVRPART *p ) { usleep(50000); if (p->prog_modes & PM_TPI) { - /* Since there is a single TPIDATA line, MOSI and MISO must be + /* Since there is a single TPIDATA line, SDO and SDI must be linked together through a 1kOhm resistor. Verify that - everything we send on MOSI gets mirrored back on MISO. */ - msg_notice2("doing MOSI-MISO link check\n"); + everything we send on SDO gets mirrored back on SDI. */ + msg_notice2("doing SDO-SDI link check\n"); memset(res, 0xaa, sizeof(res)); if (usb_in(pgm, USBTINY_SPI, LITTLE_TO_BIG_16(0x1234), LITTLE_TO_BIG_16(0x5678), @@ -457,9 +457,9 @@ static int usbtiny_initialize (const PROGRAMMER *pgm, const AVRPART *p ) { return -1; } if (res[0] != 0x12 || res[1] != 0x34 || res[2] != 0x56 || res[3] != 0x78) { - pmsg_error("MOSI->MISO check failed (got 0x%02x 0x%02x 0x%02x 0x%02x)\n" - "\tplease verify that MISO is connected directly to TPIDATA and\n" - "\tMOSI is connected to TPIDATA through a 1kOhm resistor\n", + pmsg_error("SDO->SDI check failed (got 0x%02x 0x%02x 0x%02x 0x%02x)\n" + "\tplease verify that SDI is connected directly to TPIDATA and\n" + "\tSDO is connected to TPIDATA through a 1kOhm resistor\n", res[0], res[1], res[2], res[3]); return -1; } diff --git a/tools/bootloader-hash b/tools/bootloader-hash new file mode 100755 index 00000000..7752708a --- /dev/null +++ b/tools/bootloader-hash @@ -0,0 +1,123 @@ +#!/bin/bash + +# published under GNU General Public License, version 3 (GPL-3.0) +# author Stefan Rueger, 2022 +# +# Recursivly find in the current directory intel .hex files, which are +# presumed to be bootloaders; create their hash table entry for urclock.c +# +# Background. This bash script computes the hash-sum of stk500v1 bootloaders +# to ease the guesswork of AVRDUDE's -c urclock programmer. Urclock is +# compatible with -c arduino, but needs to know the size of the bootloader to +# protect it *externally* from being overwritten. In contrast to urboot, +# optiboot et al binaries do not advertise their size and properties. Hence, +# urclock.c maintains a table with hash-sums of popular bootloaders that are +# out there in the wild, so the user doesn't have to know, let alone specify, +# the size of the bootloader on their devices. This utility computes the +# table entry from a .hex files in the directory. +# +# Example: +# $ git clone git@github.com:MCUdude/optiboot_flash.git +# $ ./bootloader-hash + +progname=$(basename $0) + +hash srec_cat 2>/dev/null || { echo $progname: package srecord is needed, try apt install srecord; exit; } +hash cc 2>/dev/null || { echo $progname: need a C compiler; exit; } + +tmp=$(mktemp "$progname.XXXXXX") +trap "rm -f $tmp $tmp.[ch]" EXIT + +cat >$tmp.c < +#include +#include +#include + +#include "$tmp.h" + +// https://en.wikipedia.org/wiki/Jenkins_hash_function +uint32_t jenkins_hash(const uint8_t* key, size_t length) { + size_t i = 0; + uint32_t hash = 0; + + while (i != length) { + hash += key[i++]; + hash += hash << 10; + hash ^= hash >> 6; + } + hash += hash << 3; + hash ^= hash >> 11; + hash += hash << 15; + + return hash; +} + + +int main(int argc, char **argv) { + unsigned char reverse[4096]; + + if(argc != 2 || !argv[1]) + exit(1); + + int len, addr, end, flashsize, bi, ri; + char *base = strrchr(argv[1], '/'); + base = base? base+1: argv[1]; + + memset(reverse, 0, sizeof reverse); + + flashsize = bootloader_finish; + while(flashsize & (flashsize-1)) + flashsize++; + + int N = sizeof bootloader_length_of_sections/sizeof*bootloader_length_of_sections; + + ri = 0; // buffer index + bi = sizeof bootloader-1; // index in bootloader[] array, top to bottom + end = flashsize; + for(int i=N-1; i >= 0; i--) { + len = bootloader_length_of_sections[i]; + addr = bootloader_address[i]; + if(addr == 0) + break; + if(addr + len > end) { + printf("inconsistent %d + %d > %d\n", addr, len, end); + exit(1); + } + + int nff = end-addr-len; + if(ri+nff <= (int) sizeof reverse) + memset(reverse+ri, 0xff, nff); + else { + printf("buffer too small %d + %d > %d\n", ri, nff, (int) sizeof reverse); + exit(1); + } + ri += nff; + + for(int n=len; n; n--) { + if(ri >= (int) sizeof reverse) + goto done; + reverse[ri] = bootloader[bi]; + ri++; + bi--; + } + end = addr; + } + +done: + ; + printf(" { %4d, %d, 0x%08x, 0x%08x }, // %s\n", ri, + strstr(base, "bigboot") || strstr(base, "BIGBOOT"), + jenkins_hash(reverse, 256), jenkins_hash(reverse, ri), base); +} +END + + +for hn in $(find . -iname \*.hex -type f); do + srec_cat "$hn" -intel -o "$tmp.h" -c-array bootloader -c_compressed -line_length 96 + cc $tmp.c -o $tmp + ./$tmp $hn +done