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* par.c: changed order of port-read/writes in par_txrx().
This change should increase immunity to delays in the programmer-hardware. Also did some unrelated cleanup in par_txrx(). git-svn-id: svn://svn.savannah.nongnu.org/avrdude/trunk/avrdude@408 81a1dc3b-b13d-400b-aceb-764788c761c2
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48
par.c
48
par.c
@@ -225,34 +225,46 @@ static unsigned char par_txrx(PROGRAMMER * pgm, unsigned char byte)
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unsigned char r, b, rbyte;
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rbyte = 0;
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for (i=0; i<8; i++) {
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b = (byte >> (7-i)) & 0x01;
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for (i=7; i>=0; i--) {
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/*
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* Write and read one bit on SPI.
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* Some notes on timing: Let T be the time it takes to do
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* one par_setpin()-call resp. par clrpin()-call, then
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* - SCK is high for 2T
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* - SCK is low for 2T
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* - MOSI setuptime is 1T
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* - MOSI holdtime is 3T
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* - SCK low to MISO read is 2T to 3T
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* So we are within programming specs (expect for AT90S1200),
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* if and only if T>t_CLCL (t_CLCL=clock period of target system).
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*
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* Due to the delay introduced by "IN" and "OUT"-commands,
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* T is greater than 1us (more like 2us) on x86-architectures.
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* So programming works safely down to 1MHz target clock.
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*/
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b = (byte >> i) & 0x01;
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/*
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* read the result bit (it is either valid from a previous clock
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* pulse or it is ignored in the current context)
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*/
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r = par_getpin(pgm->fd, pgm->pinno[PIN_AVR_MISO]);
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/* set the data input line as desired */
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par_setpin(pgm->fd, pgm->pinno[PIN_AVR_MOSI], b);
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/*
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* pulse the clock line, clocking in the MOSI data, and clocking out
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* the next result bit
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*/
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par_pulsepin(pgm->fd, pgm->pinno[PIN_AVR_SCK]);
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rbyte = rbyte | (r << (7-i));
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par_setpin(pgm->fd, pgm->pinno[PIN_AVR_SCK], 1);
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/*
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* read the result bit (it is either valid from a previous falling
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* edge or it is ignored in the current context)
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*/
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r = par_getpin(pgm->fd, pgm->pinno[PIN_AVR_MISO]);
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par_setpin(pgm->fd, pgm->pinno[PIN_AVR_SCK], 0);
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rbyte |= r << i;
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}
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return rbyte;
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}
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static int par_rdy_led(PROGRAMMER * pgm, int value)
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{
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par_setpin(pgm->fd, pgm->pinno[PIN_LED_RDY], !value);
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