diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 804468c1..2cb8f5f1 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -252,6 +252,8 @@ add_executable(avrdude main.c term.c term.h + avrintel.c + avrintel.h developer_opts.c developer_opts.h developer_opts_private.h diff --git a/src/Makefile.am b/src/Makefile.am index 9e0929e1..cc1e2ee1 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -198,6 +198,8 @@ avrdude_SOURCES = \ main.c \ whereami.c \ whereami.h \ + avrintel.c \ + avrintel.h \ developer_opts.c \ developer_opts.h \ developer_opts_private.h \ diff --git a/src/avr.c b/src/avr.c index 7a1f34a6..7bfa1496 100644 --- a/src/avr.c +++ b/src/avr.c @@ -52,7 +52,7 @@ int avr_tpi_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { int err; AVRMEM *mem; - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { pgm->pgm_led(pgm, ON); /* Set Pointer Register */ @@ -102,7 +102,7 @@ int avr_tpi_program_enable(const PROGRAMMER *pgm, const AVRPART *p, unsigned cha unsigned char cmd[2]; unsigned char response; - if(p->flags & AVRPART_HAS_TPI) { + if(p->prog_modes & PM_TPI) { /* set guard time */ cmd[0] = (TPI_CMD_SSTCS | TPI_REG_TPIPCR); cmd[1] = guard_time; @@ -194,7 +194,7 @@ int avr_read_byte_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM pgm->pgm_led(pgm, ON); pgm->err_led(pgm, OFF); - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { if (pgm->cmd_tpi == NULL) { avrdude_message(MSG_INFO, "%s: Error: %s programmer does not support TPI\n", progname, pgm->type); @@ -342,7 +342,7 @@ int avr_read(const PROGRAMMER *pgm, const AVRPART *p, const char *memtype, memset(mem->buf, 0xff, mem->size); /* supports "paged load" thru post-increment */ - if ((p->flags & AVRPART_HAS_TPI) && mem->page_size > 1 && + if ((p->prog_modes & PM_TPI) && mem->page_size > 1 && mem->size % mem->page_size == 0 && pgm->cmd_tpi != NULL) { while (avr_tpi_poll_nvmbsy(pgm)); @@ -550,7 +550,7 @@ int avr_write_byte_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM return -1; } - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { if (pgm->cmd_tpi == NULL) { avrdude_message(MSG_INFO, "%s: Error: %s programmer does not support TPI\n", progname, pgm->type); @@ -596,8 +596,7 @@ int avr_write_byte_default(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM return 0; } - if (!mem->paged && - (p->flags & AVRPART_IS_AT90S1200) == 0) { + if (!mem->paged && (p->flags & AVRPART_IS_AT90S1200) == 0) { /* * check to see if the write is necessary by reading the existing * value and only write if we are changing the value; we can't @@ -839,9 +838,7 @@ int avr_write(const PROGRAMMER *pgm, const AVRPART *p, const char *memtype, } - if ((p->flags & AVRPART_HAS_TPI) && m->page_size > 1 && - pgm->cmd_tpi != NULL) { - + if ((p->prog_modes & PM_TPI) && m->page_size > 1 && pgm->cmd_tpi) { if (wsize == 1) { /* fuse (configuration) memory: only single byte to write */ return avr_write_byte(pgm, p, m, 0, m->buf[0]) == 0? 1: -1; diff --git a/src/avrdude.conf.in b/src/avrdude.conf.in index 5a68cff5..1152af77 100644 --- a/src/avrdude.conf.in +++ b/src/avrdude.conf.in @@ -17,54 +17,69 @@ # Possible entry formats are: # # programmer -# parent # optional parent -# id = [, [, ] ...] ; # are quoted strings -# desc = ; # quoted string -# type = ; # programmer type, quoted string -# # supported programmer types can be listed by "-c ?type" +# parent # optional parent +# id = [, ... ] ; # are quoted strings +# desc = ; # quoted string +# type = ; # programmer type, quoted string +# # supported types can be listed by "-c ?type" +# prog_modes = PM_ {| PM_} # interfaces, eg, PM_SPM|PM_PDI (1) # connection_type = parallel | serial | usb | spi -# baudrate = ; # baudrate for avr910-programmer -# vcc = [, ... ] ; # pin number(s) -# buff = [, ... ] ; # pin number(s) -# reset = ; # pin number -# sck = ; # pin number -# mosi = ; # pin number -# miso = ; # pin number -# errled = ; # pin number -# rdyled = ; # pin number -# pgmled = ; # pin number -# vfyled = ; # pin number -# usbvid = ; # USB VID (Vendor ID) -# usbpid = [, ...] ; # USB PID (Product ID) (1) -# usbdev = ; # USB interface or other device info -# usbvendor = ; # USB Vendor Name -# usbproduct = ; # USB Product Name -# usbsn = ; # USB Serial Number -# hvupdi_support = [, , ... ] ; # UPDI HV Variants Support -# -# To invert a bit, use = ~ , the spaces are important. -# For a pin list all pins must be inverted. -# A single pin can be specified as usual = ~ , for lists -# specify it as follows = ~ ( [, ... ] ) . -# -# (1) Not all programmer types can process a list of PIDs. +# baudrate = ; # baudrate for avr910-programmer +# vcc = [, ... ] ; # pin number(s) +# buff = [, ... ] ; # pin number(s) +# reset = ; # pin number +# sck = ; # pin number +# mosi = ; # pin number +# miso = ; # pin number +# errled = ; # pin number +# rdyled = ; # pin number +# pgmled = ; # pin number +# vfyled = ; # pin number +# usbvid = ; # USB VID (Vendor ID) +# usbpid = [, ...] ; # USB PID (Product ID) (2) +# usbdev = ; # USB interface or other device info +# usbvendor = ; # USB Vendor Name +# usbproduct = ; # USB Product Name +# usbsn = ; # USB Serial Number +# hvupdi_support = [, , ... ] ; # UPDI HV Variants Support # ; # +# # To invert a pin use = ~ +# # To invert a pin list (all pins get inverted) use ~ ( [, ... ] ) +# # +# # (1) The following program modes are known: +# # - PM_SPM: Bootloaders, self-programming with SPM opcodes or NVM Controllers +# # - PM_TPI: Tiny Programming Interface (t4, t5, t9, t10, t20, t40, t102, t104) +# # - PM_ISP: SPI programming for In-System Programming (almost all classic parts) +# # - PM_PDI: Program and Debug Interface (xmega parts) +# # - PM_UPDI: Unified Program and Debug Interface +# # - PM_HVSP: High Voltage Serial Programming (some classic parts) +# # - PM_HVPP: High Voltage Parallel Programming (most non-HVSP classic parts) +# # - PM_debugWIRE: Simpler alternative to JTAG (a subset of HVPP/HVSP parts) +# # - PM_JTAG: Joint Test Action Group standard (some classic parts, some xmega) +# # - PM_aWire: AVR32 parts +# # +# # (2) Not all programmer types can process a list of PIDs +# # part # desc = ; # quoted string # id = ; # quoted string # family_id = ; # quoted string, eg, "megaAVR" or "tinyAVR" +# prog_modes = PM_ {| PM_} # interfaces, eg, PM_SPM|PM_ISP|PM_HVPP|PM_debugWIRE +# mcuid = ; # unique id in 0..2039 for 8-bit AVRs +# n_interrupts = ; # number of interrupts, used for vector bootloaders +# n_page_erase = ; # if set, number of pages erased during NVM erase # hvupdi_variant = ; # numeric -1 (n/a) or 0..2 # devicecode = ; # deprecated, use stk500_devcode # stk500_devcode = ; # numeric # avr910_devcode = ; # numeric -# has_jtag = ; # part has JTAG i/f -# has_debugwire = ; # part has debugWire i/f -# has_pdi = ; # part has PDI i/f -# has_updi = ; # part has UPDI i/f -# has_tpi = ; # part has TPI i/f +# has_jtag = ; # part has JTAG i/f (deprecated, use prog_modes) +# has_debugwire = ; # part has debugWire i/f (deprecated, use prog_modes) +# has_pdi = ; # part has PDI i/f (deprecated, use prog_modes) +# has_updi = ; # part has UPDI i/f (deprecated, use prog_modes) +# has_tpi = ; # part has TPI i/f (deprecated, use prog_modes) +# is_avr32 = ; # AVR32 part (deprecated, use prog_modes) # is_at90s1200 = ; # AT90S1200 part -# is_avr32 = ; # AVR32 part # signature = ; # signature bytes # usbpid = ; # DFU USB PID # chip_erase_delay = ; # micro-seconds @@ -76,7 +91,7 @@ # bs2 = ; # pin name in hex, i.e., 0xA0 # serial = ; # can use serial downloading # parallel = ; # can use par. programming -# # STK500v2 parameters, to be taken from Atmel's XML files +# # STK500v2 parameters, to be taken from Atmel's ATDF files # timeout = ; # stabdelay = ; # cmdexedelay = ; @@ -88,13 +103,13 @@ # postdelay = ; # pollmethod = ; # hvspcmdexedelay = ; -# # STK500v2 HV programming parameters, from XML -# pp_controlstack = , , ... ; # PP only -# hvsp_controlstack = , , ... ; # HVSP only +# # STK500v2 HV programming parameters, from ATDFs +# pp_controlstack = , , ... ; # PP only +# hvsp_controlstack = , , ... ; # HVSP only # flash_instr = , , ; # eeprom_instr = , , ... ; # hventerstabdelay = ; -# progmodedelay = ; # PP only +# progmodedelay = ; # PP only # latchcycles = ; # togglevtg = ; # poweroffdelay = ; @@ -102,21 +117,21 @@ # resetdelayus = ; # hvleavestabdelay = ; # resetdelay = ; -# synchcycles = ; # HVSP only -# chiperasepulsewidth = ; # PP only +# synchcycles = ; # HVSP only +# chiperasepulsewidth = ; # PP only # chiperasepolltimeout = ; -# chiperasetime = ; # HVSP only -# programfusepulsewidth = ; # PP only +# chiperasetime = ; # HVSP only +# programfusepulsewidth = ; # PP only # programfusepolltimeout = ; -# programlockpulsewidth = ; # PP only +# programlockpulsewidth = ; # PP only # programlockpolltimeout = ; -# # JTAG ICE mkII parameters, also from XML files +# # JTAG ICE mkII parameters, also from ATDF files # allowfullpagebitstream = ; # enablepageprogramming = ; -# idr = ; # IO addr of IDR (OCD) reg -# rampz = ; # IO addr of RAMPZ reg -# spmcr = ; # mem addr of SPMC[S]R reg -# eecr = ; # mem addr of EECR reg only when != 0x3f +# idr = ; # IO addr of IDR (OCD) reg +# rampz = ; # IO addr of RAMPZ reg +# spmcr = ; # mem addr of SPMC[S]R reg +# eecr = ; # mem addr of EECR reg only when != 0x3f # mcu_base = ; # nvm_base = ; # ocd_base = ; @@ -136,7 +151,7 @@ # readback_p1 = ; # byte value (first component) # readback_p2 = ; # byte value (second component) # pwroff_after_write = ; # yes/no -# mode = ; # STK500 v2 file parameter, to be taken from Atmel's XML files +# mode = ; # STK500 v2 file parameter from ATDF files # delay = ; # " # blocksize = ; # " # readsize = ; # " @@ -153,10 +168,13 @@ # ; # # If any of the above parameters are not specified, the default value -# of 0 is used for numerics (except for hvupdi_variant and ocdrev, -# where the default value is -1) or the empty string ("") for string -# values. If a required parameter is left empty, AVRDUDE will -# complain. +# of 0 is used for numerics (except for mcuid, hvupdi_variant and +# ocdrev, where the default value is -1) or the empty string "" for +# string values. If a required parameter is left empty, AVRDUDE will +# complain. Almost all occurrences of numbers (with the exception of +# pin numbers and where they are separated by space, eg, in signature +# and readback) can also be given as simple expressions involving +# arithemtic and bitwise operators. # # Parts can also inherit parameters from previously defined parts # using the following syntax. In this case specified integer and @@ -167,7 +185,7 @@ # memory definition is extended, and components overwritten with new # values. Assigning NULL removes an inherited SPI instruction format, # memory definition, control stack, eeprom or flash instruction, eg, -# as in memory "efuse" = NULL; +# as in memory "efuse" = NULL; # # part parent # quoted string # id = ; # quoted string @@ -177,16 +195,16 @@ # NOTES: # * 'devicecode' is the device code used by the STK500 (see codes # listed below) -# * Not all memory types will implement all instructions. -# * AVR Fuse bits and Lock bits are implemented as a type of memory. +# * Not all memory types will implement all instructions +# * AVR Fuse bits and Lock bits are implemented as a type of memory # * Example memory types are: # "flash", "eeprom", "fuse", "lfuse" (low fuse), "hfuse" (high # fuse), "signature", "calibration", "lock" # * The memory type specified on the avrdude command line must match -# one of the memory types defined for the specified chip. +# one of the memory types defined for the specified chip # * The pwroff_after_write flag causes avrdude to attempt to # power the device off and back on after an unsuccessful write to -# the affected memory area if VCC programmer pins are defined. If +# the affected memory area if VCC programmer pins are defined. If # VCC pins are not defined for the programmer, a message # indicating that the device needs a power-cycle is printed out. # This flag was added to work around a problem with the @@ -247,7 +265,7 @@ # section avr061.zip which accompanies the application note # AVR061 available from: # -# http://www.atmel.com/dyn/resources/prod_documents/doc2525.pdf +# https://ww1.microchip.com/downloads/en/Appnotes/doc2525.pdf # #define ATTINY10 0x10 /* the _old_ one that never existed! */ @@ -2305,7 +2323,6 @@ programmer hvupdi_support = 1; ; - # # PART DEFINITIONS # @@ -2319,6 +2336,9 @@ programmer part desc = "ATtiny11"; id = "t11"; + prog_modes = PM_HVSP; + mcuid = 8; + n_interrupts = 5; stk500_devcode = 0x11; chip_erase_delay = 20000; signature = 0x1e 0x90 0x04; @@ -2379,6 +2399,9 @@ part part desc = "ATtiny12"; id = "t12"; + prog_modes = PM_ISP | PM_HVSP; + mcuid = 9; + n_interrupts = 6; stk500_devcode = 0x12; avr910_devcode = 0x55; chip_erase_delay = 20000; @@ -2472,10 +2495,12 @@ part part desc = "ATtiny13"; id = "t13"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 10; + n_interrupts = 10; stk500_devcode = 0x14; chip_erase_delay = 4000; signature = 0x1e 0x90 0x07; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -2587,6 +2612,7 @@ part part parent "t13" desc = "ATtiny13A"; id = "t13a"; + mcuid = 11; ; #------------------------------------------------------------ @@ -2596,6 +2622,9 @@ part parent "t13" part desc = "ATtiny15"; id = "t15"; + prog_modes = PM_ISP | PM_HVSP; + mcuid = 12; + n_interrupts = 9; stk500_devcode = 0x13; avr910_devcode = 0x56; chip_erase_delay = 8200; @@ -2690,6 +2719,9 @@ part part desc = "AT90S1200"; id = "1200"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 183; + n_interrupts = 4; stk500_devcode = 0x33; avr910_devcode = 0x13; chip_erase_delay = 20000; @@ -2769,6 +2801,9 @@ part part desc = "AT90S4414"; id = "4414"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 190; + n_interrupts = 13; stk500_devcode = 0x50; avr910_devcode = 0x28; chip_erase_delay = 20000; @@ -2846,6 +2881,9 @@ part part desc = "AT90S2313"; id = "2313"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 186; + n_interrupts = 11; stk500_devcode = 0x40; avr910_devcode = 0x20; chip_erase_delay = 20000; @@ -2924,6 +2962,9 @@ part ##### WARNING: No XML file for device 'AT90S2333'! ##### desc = "AT90S2333"; id = "2333"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 188; + n_interrupts = 14; stk500_devcode = 0x42; avr910_devcode = 0x34; chip_erase_delay = 20000; @@ -3007,6 +3048,9 @@ part part desc = "AT90S2343"; id = "2343"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP; + mcuid = 189; + n_interrupts = 3; stk500_devcode = 0x43; avr910_devcode = 0x4c; chip_erase_delay = 18000; @@ -3094,6 +3138,9 @@ part part desc = "AT90S4433"; id = "4433"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 191; + n_interrupts = 14; stk500_devcode = 0x51; avr910_devcode = 0x30; chip_erase_delay = 20000; @@ -3178,6 +3225,9 @@ part ##### WARNING: No XML file for device 'AT90S4434'! ##### desc = "AT90S4434"; id = "4434"; + prog_modes = PM_SPM | PM_ISP; + mcuid = 192; + n_interrupts = 17; stk500_devcode = 0x52; avr910_devcode = 0x6c; chip_erase_delay = 20000; @@ -3234,6 +3284,9 @@ part part desc = "AT90S8515"; id = "8515"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 193; + n_interrupts = 13; stk500_devcode = 0x60; avr910_devcode = 0x38; chip_erase_delay = 20000; @@ -3312,6 +3365,9 @@ part part desc = "AT90S8535"; id = "8535"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 195; + n_interrupts = 17; stk500_devcode = 0x61; avr910_devcode = 0x68; chip_erase_delay = 20000; @@ -3394,6 +3450,9 @@ part part desc = "ATmega103"; id = "m103"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 84; + n_interrupts = 24; stk500_devcode = 0xb1; avr910_devcode = 0x41; chip_erase_delay = 112000; @@ -3480,6 +3539,9 @@ part part desc = "ATmega64"; id = "m64"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 72; + n_interrupts = 35; stk500_devcode = 0xa0; avr910_devcode = 0x45; chip_erase_delay = 9000; @@ -3487,7 +3549,6 @@ part bs2 = 0xa0; signature = 0x1e 0x96 0x02; reset = io; - has_jtag = yes; allowfullpagebitstream = yes; timeout = 200; stabdelay = 100; @@ -3597,6 +3658,7 @@ part part parent "m64" desc = "ATmega64A"; id = "m64a"; + mcuid = 73; ; #------------------------------------------------------------ @@ -3606,6 +3668,9 @@ part parent "m64" part desc = "ATmega128"; id = "m128"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 85; + n_interrupts = 35; stk500_devcode = 0xb2; avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -3613,7 +3678,6 @@ part bs2 = 0xa0; signature = 0x1e 0x97 0x02; reset = io; - has_jtag = yes; allowfullpagebitstream = yes; timeout = 200; stabdelay = 100; @@ -3724,6 +3788,7 @@ part part parent "m128" desc = "ATmega128A"; id = "m128a"; + mcuid = 86; ; #------------------------------------------------------------ @@ -3733,6 +3798,9 @@ part parent "m128" part desc = "AT90CAN128"; id = "c128"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 176; + n_interrupts = 37; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -3740,7 +3808,6 @@ part # avr910_devcode = 0x43; signature = 0x1e 0x97 0x81; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -3854,6 +3921,9 @@ part part desc = "AT90CAN64"; id = "c64"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 172; + n_interrupts = 37; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -3861,7 +3931,6 @@ part # avr910_devcode = 0x43; signature = 0x1e 0x96 0x81; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -3975,6 +4044,9 @@ part part desc = "AT90CAN32"; id = "c32"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 171; + n_interrupts = 37; stk500_devcode = 0xb3; chip_erase_delay = 9000; pagel = 0xd7; @@ -3982,7 +4054,6 @@ part # avr910_devcode = 0x43; signature = 0x1e 0x95 0x81; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -4096,6 +4167,9 @@ part part desc = "ATmega16"; id = "m16"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 49; + n_interrupts = 21; stk500_devcode = 0x82; avr910_devcode = 0x74; chip_erase_delay = 9000; @@ -4103,7 +4177,6 @@ part bs2 = 0xa0; signature = 0x1e 0x94 0x03; reset = io; - has_jtag = yes; allowfullpagebitstream = yes; timeout = 200; stabdelay = 100; @@ -4209,6 +4282,7 @@ part part parent "m16" desc = "ATmega16A"; id = "m16a"; + mcuid = 50; ; #------------------------------------------------------------ @@ -4218,6 +4292,9 @@ part parent "m16" part desc = "ATmega324P"; id = "m324p"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 111; + n_interrupts = 31; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4225,7 +4302,6 @@ part bs2 = 0xa0; signature = 0x1e 0x95 0x08; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -4339,6 +4415,7 @@ part part parent "m324p" desc = "ATmega164P"; id = "m164p"; + mcuid = 93; signature = 0x1e 0x94 0x0a; memory "eeprom" @@ -4358,6 +4435,7 @@ part parent "m324p" part parent "m164p" desc = "ATmega164PA"; id = "m164pa"; + mcuid = 94; ; #------------------------------------------------------------ @@ -4367,6 +4445,7 @@ part parent "m164p" part parent "m164p" desc = "ATmega164A"; id = "m164a"; + mcuid = 92; signature = 0x1e 0x94 0x0f; ; @@ -4377,6 +4456,7 @@ part parent "m164p" part parent "m324p" desc = "ATmega324PB"; id = "m324pb"; + mcuid = 113; signature = 0x1e 0x95 0x17; ; @@ -4387,6 +4467,7 @@ part parent "m324p" part parent "m324p" desc = "ATmega324PA"; id = "m324pa"; + mcuid = 112; signature = 0x1e 0x95 0x11; ; @@ -4397,6 +4478,7 @@ part parent "m324p" part parent "m324p" desc = "ATmega324A"; id = "m324a"; + mcuid = 110; signature = 0x1e 0x95 0x15; ; @@ -4407,6 +4489,9 @@ part parent "m324p" part desc = "ATmega644"; id = "m644"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 127; + n_interrupts = 28; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4414,7 +4499,6 @@ part bs2 = 0xa0; signature = 0x1e 0x96 0x09; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -4525,6 +4609,8 @@ part part parent "m644" desc = "ATmega644A"; id = "m644a"; + mcuid = 128; + n_interrupts = 31; ; #------------------------------------------------------------ @@ -4534,6 +4620,8 @@ part parent "m644" part parent "m644" desc = "ATmega644P"; id = "m644p"; + mcuid = 129; + n_interrupts = 31; signature = 0x1e 0x96 0x0a; ; @@ -4544,6 +4632,8 @@ part parent "m644" part parent "m644" desc = "ATmega644PA"; id = "m644pa"; + mcuid = 130; + n_interrupts = 31; signature = 0x1e 0x96 0x0a; ; @@ -4554,6 +4644,9 @@ part parent "m644" part desc = "ATmega1284"; id = "m1284"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 140; + n_interrupts = 35; stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one avr910_devcode = 0x74; chip_erase_delay = 55000; @@ -4561,7 +4654,6 @@ part bs2 = 0xa0; signature = 0x1e 0x97 0x06; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -4676,6 +4768,7 @@ part part parent "m1284" desc = "ATmega1284P"; id = "m1284p"; + mcuid = 141; signature = 0x1e 0x97 0x05; ; @@ -4686,6 +4779,9 @@ part parent "m1284" part desc = "ATmega162"; id = "m162"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 90; + n_interrupts = 28; stk500_devcode = 0x83; avr910_devcode = 0x63; chip_erase_delay = 9000; @@ -4693,7 +4789,6 @@ part bs2 = 0xa0; signature = 0x1e 0x94 0x04; reset = io; - has_jtag = yes; allowfullpagebitstream = yes; timeout = 200; stabdelay = 100; @@ -4805,6 +4900,9 @@ part part desc = "ATmega163"; id = "m163"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 91; + n_interrupts = 18; stk500_devcode = 0x81; avr910_devcode = 0x64; chip_erase_delay = 32000; @@ -4906,11 +5004,13 @@ part part desc = "ATmega169"; id = "m169"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 104; + n_interrupts = 23; stk500_devcode = 0x85; avr910_devcode = 0x78; chip_erase_delay = 9000; signature = 0x1e 0x94 0x05; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -5025,6 +5125,7 @@ part part parent "m169" desc = "ATmega169A"; id = "m169a"; + mcuid = 105; signature = 0x1e 0x94 0x11; reset = io; ; @@ -5036,6 +5137,7 @@ part parent "m169" part parent "m169" desc = "ATmega169P"; id = "m169p"; + mcuid = 106; reset = io; ; @@ -5046,6 +5148,7 @@ part parent "m169" part parent "m169" desc = "ATmega169PA"; id = "m169pa"; + mcuid = 107; reset = io; ; @@ -5056,13 +5159,15 @@ part parent "m169" part desc = "ATmega329"; id = "m329"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 121; + n_interrupts = 23; # stk500_devcode = 0x85; # no STK500 support, only STK500v2 # avr910_devcode = 0x?; # try the ATmega169 one: avr910_devcode = 0x75; chip_erase_delay = 9000; signature = 0x1e 0x95 0x03; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -5177,6 +5282,7 @@ part part parent "m329" desc = "ATmega329A"; id = "m329a"; + mcuid = 122; ; #------------------------------------------------------------ @@ -5186,6 +5292,7 @@ part parent "m329" part parent "m329" desc = "ATmega329P"; id = "m329p"; + mcuid = 123; signature = 0x1e 0x95 0x0b; ; @@ -5196,6 +5303,7 @@ part parent "m329" part parent "m329" desc = "ATmega329PA"; id = "m329pa"; + mcuid = 124; signature = 0x1e 0x95 0x0b; ; @@ -5206,6 +5314,8 @@ part parent "m329" part parent "m329" desc = "ATmega3290"; id = "m3290"; + mcuid = 150; + n_interrupts = 25; signature = 0x1e 0x95 0x04; ; @@ -5216,6 +5326,8 @@ part parent "m329" part parent "m329" desc = "ATmega3290A"; id = "m3290a"; + mcuid = 151; + n_interrupts = 25; signature = 0x1e 0x95 0x04; ; @@ -5226,6 +5338,8 @@ part parent "m329" part parent "m329" desc = "ATmega3290P"; id = "m3290p"; + mcuid = 152; + n_interrupts = 25; signature = 0x1e 0x95 0x0c; ; @@ -5236,6 +5350,8 @@ part parent "m329" part parent "m329" desc = "ATmega3290PA"; id = "m3290pa"; + mcuid = 153; + n_interrupts = 25; signature = 0x1e 0x95 0x0c; ; @@ -5246,13 +5362,15 @@ part parent "m329" part desc = "ATmega649"; id = "m649"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 135; + n_interrupts = 23; # stk500_devcode = 0x85; # no STK500 support, only STK500v2 # avr910_devcode = 0x?; # try the ATmega169 one: avr910_devcode = 0x75; chip_erase_delay = 9000; signature = 0x1e 0x96 0x03; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -5367,6 +5485,7 @@ part part parent "m649" desc = "ATmega649A"; id = "m649a"; + mcuid = 136; ; #------------------------------------------------------------ @@ -5376,6 +5495,7 @@ part parent "m649" part parent "m649" desc = "ATmega649P"; id = "m649p"; + mcuid = 137; signature = 0x1e 0x96 0x0b; ; @@ -5386,6 +5506,8 @@ part parent "m649" part parent "m649" desc = "ATmega6490"; id = "m6490"; + mcuid = 157; + n_interrupts = 25; signature = 0x1e 0x96 0x04; ; @@ -5396,6 +5518,8 @@ part parent "m649" part parent "m649" desc = "ATmega6490A"; id = "m6490a"; + mcuid = 158; + n_interrupts = 25; signature = 0x1e 0x96 0x04; ; @@ -5406,6 +5530,8 @@ part parent "m649" part parent "m649" desc = "ATmega6490P"; id = "m6490p"; + mcuid = 159; + n_interrupts = 25; signature = 0x1e 0x96 0x0c; ; @@ -5416,6 +5542,9 @@ part parent "m649" part desc = "ATmega32"; id = "m32"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 58; + n_interrupts = 21; stk500_devcode = 0x91; avr910_devcode = 0x72; chip_erase_delay = 9000; @@ -5423,7 +5552,6 @@ part bs2 = 0xa0; signature = 0x1e 0x95 0x02; reset = io; - has_jtag = yes; allowfullpagebitstream = yes; timeout = 200; stabdelay = 100; @@ -5527,6 +5655,9 @@ part part desc = "ATmega161"; id = "m161"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 89; + n_interrupts = 21; stk500_devcode = 0x80; avr910_devcode = 0x60; chip_erase_delay = 28000; @@ -5615,6 +5746,7 @@ part part parent "m32" desc = "ATmega32A"; id = "m32a"; + mcuid = 59; ; #------------------------------------------------------------ @@ -5624,6 +5756,9 @@ part parent "m32" part desc = "ATmega8"; id = "m8"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 45; + n_interrupts = 19; stk500_devcode = 0x70; avr910_devcode = 0x76; chip_erase_delay = 10000; @@ -5732,6 +5867,7 @@ part part parent "m8" desc = "ATmega8A"; id = "m8a"; + mcuid = 46; ; #------------------------------------------------------------ @@ -5741,6 +5877,9 @@ part parent "m8" part desc = "ATmega8515"; id = "m8515"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 160; + n_interrupts = 17; stk500_devcode = 0x63; avr910_devcode = 0x3a; chip_erase_delay = 9000; @@ -5841,6 +5980,9 @@ part part desc = "ATmega8535"; id = "m8535"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP; + mcuid = 161; + n_interrupts = 21; stk500_devcode = 0x64; avr910_devcode = 0x69; chip_erase_delay = 9000; @@ -5943,6 +6085,9 @@ part part desc = "ATtiny26"; id = "t26"; + prog_modes = PM_ISP | PM_HVPP; + mcuid = 17; + n_interrupts = 12; stk500_devcode = 0x21; avr910_devcode = 0x5e; chip_erase_delay = 9000; @@ -6048,13 +6193,15 @@ part part desc = "ATtiny261"; id = "t261"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 30; + n_interrupts = 19; chip_erase_delay = 4000; pagel = 0xb3; bs2 = 0xb2; # stk500_devcode = 0x21; # avr910_devcode = 0x5e; signature = 0x1e 0x91 0x0c; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6172,6 +6319,7 @@ part part parent "t261" desc = "ATtiny261A"; id = "t261a"; + mcuid = 31; ; #------------------------------------------------------------ @@ -6181,13 +6329,15 @@ part parent "t261" part desc = "ATtiny461"; id = "t461"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 33; + n_interrupts = 19; chip_erase_delay = 4000; pagel = 0xb3; bs2 = 0xb2; # stk500_devcode = 0x21; # avr910_devcode = 0x5e; signature = 0x1e 0x92 0x08; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6305,6 +6455,7 @@ part part parent "t461" desc = "ATtiny461A"; id = "t461a"; + mcuid = 34; ; #------------------------------------------------------------ @@ -6314,13 +6465,15 @@ part parent "t461" part desc = "ATtiny861"; id = "t861"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 38; + n_interrupts = 19; chip_erase_delay = 4000; pagel = 0xb3; bs2 = 0xb2; # stk500_devcode = 0x21; # avr910_devcode = 0x5e; signature = 0x1e 0x93 0x0d; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6438,6 +6591,7 @@ part part parent "t861" desc = "ATtiny861A"; id = "t861a"; + mcuid = 39; ; #------------------------------------------------------------ @@ -6449,6 +6603,9 @@ part parent "t861" part desc = "ATtiny28"; id = "t28"; + prog_modes = PM_HVPP; + mcuid = 18; + n_interrupts = 6; stk500_devcode = 0x22; avr910_devcode = 0x5c; signature = 0x1e 0x91 0x07; @@ -6496,6 +6653,9 @@ part part desc = "ATmega48"; id = "m48"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 67; + n_interrupts = 26; stk500_devcode = 0x59; chip_erase_delay = 45000; pagel = 0xd7; @@ -6503,7 +6663,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x92 0x05; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6621,6 +6780,7 @@ part part parent "m48" desc = "ATmega48A"; id = "m48a"; + mcuid = 68; ; #------------------------------------------------------------ @@ -6630,6 +6790,7 @@ part parent "m48" part parent "m48" desc = "ATmega48P"; id = "m48p"; + mcuid = 69; signature = 0x1e 0x92 0x0a; ; @@ -6640,6 +6801,7 @@ part parent "m48" part parent "m48" desc = "ATmega48PA"; id = "m48pa"; + mcuid = 70; signature = 0x1e 0x92 0x0a; ; @@ -6650,6 +6812,8 @@ part parent "m48" part parent "m48" desc = "ATmega48PB"; id = "m48pb"; + mcuid = 71; + n_interrupts = 27; chip_erase_delay = 10500; signature = 0x1e 0x92 0x10; ; @@ -6661,6 +6825,9 @@ part parent "m48" part desc = "ATmega88"; id = "m88"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 79; + n_interrupts = 26; stk500_devcode = 0x73; chip_erase_delay = 9000; pagel = 0xd7; @@ -6668,7 +6835,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x93 0x0a; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6787,6 +6953,7 @@ part part parent "m88" desc = "ATmega88A"; id = "m88a"; + mcuid = 80; ; #------------------------------------------------------------ @@ -6796,6 +6963,7 @@ part parent "m88" part parent "m88" desc = "ATmega88P"; id = "m88p"; + mcuid = 81; signature = 0x1e 0x93 0x0f; ; @@ -6806,6 +6974,7 @@ part parent "m88" part parent "m88" desc = "ATmega88PA"; id = "m88pa"; + mcuid = 82; signature = 0x1e 0x93 0x0f; ; @@ -6816,6 +6985,8 @@ part parent "m88" part parent "m88" desc = "ATmega88PB"; id = "m88pb"; + mcuid = 83; + n_interrupts = 27; chip_erase_delay = 10500; signature = 0x1e 0x93 0x16; ; @@ -6827,6 +6998,9 @@ part parent "m88" part desc = "ATmega168"; id = "m168"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 99; + n_interrupts = 26; stk500_devcode = 0x86; chip_erase_delay = 9000; pagel = 0xd7; @@ -6834,7 +7008,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x94 0x06; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -6953,6 +7126,7 @@ part part parent "m168" desc = "ATmega168A"; id = "m168a"; + mcuid = 100; ; #------------------------------------------------------------ @@ -6962,6 +7136,7 @@ part parent "m168" part parent "m168" desc = "ATmega168P"; id = "m168p"; + mcuid = 101; signature = 0x1e 0x94 0x0b; ; @@ -6972,6 +7147,7 @@ part parent "m168" part parent "m168" desc = "ATmega168PA"; id = "m168pa"; + mcuid = 102; signature = 0x1e 0x94 0x0b; ; @@ -6982,6 +7158,8 @@ part parent "m168" part parent "m168" desc = "ATmega168PB"; id = "m168pb"; + mcuid = 103; + n_interrupts = 27; chip_erase_delay = 10500; signature = 0x1e 0x94 0x15; ; @@ -6993,6 +7171,9 @@ part parent "m168" part desc = "ATtiny828"; id = "t828"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 35; + n_interrupts = 26; stk500_devcode = 0x86; chip_erase_delay = 15000; pagel = 0xd7; @@ -7000,7 +7181,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x93 0x14; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7118,6 +7298,7 @@ part part parent "t828" desc = "ATtiny828R"; id = "t828r"; + mcuid = 36; ; #------------------------------------------------------------ @@ -7127,6 +7308,9 @@ part parent "t828" part desc = "ATtiny87"; id = "t87"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 27; + n_interrupts = 20; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # Try the AT90S2313 devcode: @@ -7134,7 +7318,6 @@ part chip_erase_delay = 15000; signature = 0x1e 0x93 0x87; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7251,6 +7434,9 @@ part part desc = "ATtiny167"; id = "t167"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 29; + n_interrupts = 20; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = 0x??; @@ -7259,7 +7445,6 @@ part chip_erase_delay = 15000; signature = 0x1e 0x94 0x87; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7376,6 +7561,9 @@ part part desc = "ATtiny48"; id = "t48"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 23; + n_interrupts = 20; stk500_devcode = 0x73; chip_erase_delay = 15000; pagel = 0xd7; @@ -7383,7 +7571,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x92 0x09; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7502,6 +7689,9 @@ part part desc = "ATtiny88"; id = "t88"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 28; + n_interrupts = 20; stk500_devcode = 0x73; chip_erase_delay = 9000; pagel = 0xd7; @@ -7509,7 +7699,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x93 0x11; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7628,6 +7817,9 @@ part part desc = "ATmega328"; id = "m328"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 118; + n_interrupts = 26; stk500_devcode = 0x86; chip_erase_delay = 9000; pagel = 0xd7; @@ -7635,7 +7827,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x95 0x14; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7754,6 +7945,7 @@ part part parent "m328" desc = "ATmega328P"; id = "m328p"; + mcuid = 119; signature = 0x1e 0x95 0x0f; ; @@ -7764,6 +7956,8 @@ part parent "m328" part parent "m328" desc = "ATmega328PB"; id = "m328pb"; + mcuid = 120; + n_interrupts = 45; chip_erase_delay = 10500; signature = 0x1e 0x95 0x16; @@ -7779,6 +7973,8 @@ part parent "m328" part parent "m328" desc = "ATmega32M1"; id = "m32m1"; + mcuid = 63; + n_interrupts = 31; bs2 = 0xe2; # stk500_devcode = 0x??; # avr910_devcode = 0x??; @@ -7796,6 +7992,8 @@ part parent "m328" part parent "m328" desc = "ATmega64M1"; id = "m64m1"; + mcuid = 76; + n_interrupts = 31; bs2 = 0xe2; # stk500_devcode = 0x??; # avr910_devcode = 0x??; @@ -7832,6 +8030,9 @@ part parent "m328" part desc = "ATtiny2313"; id = "t2313"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 42; + n_interrupts = 19; stk500_devcode = 0x23; # Use the ATtiny26 devcode: avr910_devcode = 0x5e; @@ -7840,7 +8041,6 @@ part bs2 = 0xd6; signature = 0x1e 0x91 0x0a; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -7963,6 +8163,8 @@ part part parent "t2313" desc = "ATtiny2313A"; id = "t2313a"; + mcuid = 43; + n_interrupts = 21; ; #------------------------------------------------------------ @@ -7972,6 +8174,9 @@ part parent "t2313" part desc = "ATtiny4313"; id = "t4313"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 44; + n_interrupts = 21; stk500_devcode = 0x23; # Use the ATtiny26 devcode: avr910_devcode = 0x5e; @@ -7980,7 +8185,6 @@ part bs2 = 0xd6; signature = 0x1e 0x92 0x0d; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8098,6 +8302,9 @@ part part desc = "AT90PWM2"; id = "pwm2"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 167; + n_interrupts = 32; stk500_devcode = 0x65; chip_erase_delay = 9000; pagel = 0xd8; @@ -8105,7 +8312,6 @@ part # avr910_devcode = ?; signature = 0x1e 0x93 0x81; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8224,6 +8430,7 @@ part part parent "pwm2" desc = "AT90PWM3"; id = "pwm3"; + mcuid = 169; ; #------------------------------------------------------------ @@ -8234,6 +8441,7 @@ part parent "pwm2" part parent "pwm2" desc = "AT90PWM2B"; id = "pwm2b"; + mcuid = 168; signature = 0x1e 0x93 0x83; ocdrev = 1; ; @@ -8247,6 +8455,7 @@ part parent "pwm2" part parent "pwm2b" desc = "AT90PWM3B"; id = "pwm3b"; + mcuid = 170; ; #------------------------------------------------------------ @@ -8258,6 +8467,7 @@ part parent "pwm2b" part parent "pwm3b" desc = "AT90PWM316"; id = "pwm316"; + mcuid = 180; signature = 0x1e 0x94 0x83; memory "flash" @@ -8281,6 +8491,7 @@ part parent "pwm3b" part parent "pwm316" desc = "AT90PWM216"; id = "pwm216"; + mcuid = 179; ; #------------------------------------------------------------ @@ -8290,6 +8501,9 @@ part parent "pwm316" part desc = "ATtiny25"; id = "t25"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 16; + n_interrupts = 15; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = ?; @@ -8298,7 +8512,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x91 0x08; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8418,6 +8631,9 @@ part part desc = "ATtiny45"; id = "t45"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 22; + n_interrupts = 15; stk500_devcode = 0x14; # avr910_devcode = ?; # Try the AT90S2313 devcode: @@ -8425,7 +8641,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x92 0x06; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8545,6 +8760,9 @@ part part desc = "ATtiny85"; id = "t85"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 26; + n_interrupts = 15; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = ?; @@ -8553,7 +8771,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x93 0x0b; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8674,6 +8891,9 @@ part part desc = "ATmega640"; id = "m640"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 126; + n_interrupts = 57; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -8681,7 +8901,6 @@ part bs2 = 0xa0; signature = 0x1e 0x96 0x08; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8795,6 +9014,9 @@ part part desc = "ATmega1280"; id = "m1280"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 138; + n_interrupts = 57; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -8802,7 +9024,6 @@ part bs2 = 0xa0; signature = 0x1e 0x97 0x03; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -8917,6 +9138,8 @@ part part parent "m1280" desc = "ATmega1281"; id = "m1281"; + mcuid = 139; + n_interrupts = 51; signature = 0x1e 0x97 0x04; ; @@ -8927,6 +9150,9 @@ part parent "m1280" part desc = "ATmega2560"; id = "m2560"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 143; + n_interrupts = 57; stk500_devcode = 0xb2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -8934,7 +9160,6 @@ part bs2 = 0xa0; signature = 0x1e 0x98 0x01; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9049,6 +9274,8 @@ part part parent "m2560" desc = "ATmega2561"; id = "m2561"; + mcuid = 144; + n_interrupts = 51; signature = 0x1e 0x98 0x02; ; @@ -9060,6 +9287,8 @@ part parent "m2560" part parent "m2561" desc = "ATmega128RFA1"; id = "m128rfa1"; + mcuid = 87; + n_interrupts = 72; chip_erase_delay = 55000; bs2 = 0xe2; signature = 0x1e 0xa7 0x01; @@ -9082,6 +9311,8 @@ part parent "m2561" part parent "m2561" desc = "ATmega256RFR2"; id = "m256rfr2"; + mcuid = 108; + n_interrupts = 77; chip_erase_delay = 18500; bs2 = 0xe2; signature = 0x1e 0xa8 0x02; @@ -9103,6 +9334,8 @@ part parent "m2561" part parent "m128rfa1" desc = "ATmega128RFR2"; id = "m128rfr2"; + mcuid = 88; + n_interrupts = 77; signature = 0x1e 0xa7 0x02; ; @@ -9113,6 +9346,8 @@ part parent "m128rfa1" part parent "m128rfa1" desc = "ATmega64RFR2"; id = "m64rfr2"; + mcuid = 78; + n_interrupts = 77; signature = 0x1e 0xa6 0x02; memory "eeprom" @@ -9140,6 +9375,7 @@ part parent "m128rfa1" part parent "m256rfr2" desc = "ATmega2564RFR2"; id = "m2564rfr2"; + mcuid = 145; signature = 0x1e 0xa8 0x03; ; @@ -9150,6 +9386,7 @@ part parent "m256rfr2" part parent "m128rfr2" desc = "ATmega1284RFR2"; id = "m1284rfr2"; + mcuid = 142; signature = 0x1e 0xa7 0x03; ; @@ -9160,6 +9397,7 @@ part parent "m128rfr2" part parent "m64rfr2" desc = "ATmega644RFR2"; id = "m644rfr2"; + mcuid = 131; signature = 0x1e 0xa6 0x03; ; @@ -9170,6 +9408,9 @@ part parent "m64rfr2" part desc = "ATtiny24"; id = "t24"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 14; + n_interrupts = 17; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = ?; @@ -9178,7 +9419,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x91 0x0b; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9298,6 +9538,7 @@ part part parent "t24" desc = "ATtiny24A"; id = "t24a"; + mcuid = 15; ; #------------------------------------------------------------ @@ -9307,6 +9548,9 @@ part parent "t24" part desc = "ATtiny44"; id = "t44"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 20; + n_interrupts = 17; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = ?; @@ -9315,7 +9559,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x92 0x07; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9435,6 +9678,7 @@ part part parent "t44" desc = "ATtiny44A"; id = "t44a"; + mcuid = 21; ; #------------------------------------------------------------ @@ -9444,6 +9688,9 @@ part parent "t44" part desc = "ATtiny84"; id = "t84"; + prog_modes = PM_SPM | PM_ISP | PM_HVSP | PM_debugWIRE; + mcuid = 24; + n_interrupts = 17; # no STK500 devcode in XML file, use the ATtiny45 one stk500_devcode = 0x14; # avr910_devcode = ?; @@ -9452,7 +9699,6 @@ part chip_erase_delay = 4500; signature = 0x1e 0x93 0x0c; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9572,6 +9818,7 @@ part part parent "t84" desc = "ATtiny84A"; id = "t84a"; + mcuid = 25; ; #------------------------------------------------------------ @@ -9581,6 +9828,9 @@ part parent "t84" part parent "t44" desc = "ATtiny441"; id = "t441"; + mcuid = 32; + n_interrupts = 30; + n_page_erase = 4; signature = 0x1e 0x92 0x15; memory "flash" @@ -9604,6 +9854,9 @@ part parent "t44" part parent "t84" desc = "ATtiny841"; id = "t841"; + mcuid = 37; + n_interrupts = 30; + n_page_erase = 4; signature = 0x1e 0x93 0x15; memory "flash" @@ -9627,6 +9880,9 @@ part parent "t84" part desc = "ATtiny43U"; id = "t43u"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 19; + n_interrupts = 16; stk500_devcode = 0x14; # avr910_devcode = ?; # Try the AT90S2313 devcode: @@ -9634,7 +9890,6 @@ part chip_erase_delay = 1000; signature = 0x1e 0x92 0x0c; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9754,6 +10009,9 @@ part part desc = "ATmega16U4"; id = "m16u4"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 57; + n_interrupts = 43; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -9762,7 +10020,6 @@ part signature = 0x1e 0x94 0x88; usbpid = 0x2ff4; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9876,6 +10133,9 @@ part part desc = "ATmega32U4"; id = "m32u4"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 65; + n_interrupts = 43; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -9884,7 +10144,6 @@ part signature = 0x1e 0x95 0x87; usbpid = 0x2ff4; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -9998,6 +10257,9 @@ part part desc = "AT90USB646"; id = "usb646"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 181; + n_interrupts = 38; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10006,7 +10268,6 @@ part signature = 0x1e 0x96 0x82; usbpid = 0x2ff9; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10121,6 +10382,7 @@ part part parent "usb646" desc = "AT90USB647"; id = "usb647"; + mcuid = 182; ; #------------------------------------------------------------ @@ -10130,6 +10392,9 @@ part parent "usb646" part desc = "AT90USB1286"; id = "usb1286"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 184; + n_interrupts = 38; # stk500_devcode = 0xB2; # avr910_devcode = 0x43; chip_erase_delay = 9000; @@ -10138,7 +10403,6 @@ part signature = 0x1e 0x97 0x82; usbpid = 0x2ffb; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10253,6 +10517,7 @@ part part parent "usb1286" desc = "AT90USB1287"; id = "usb1287"; + mcuid = 185; ; #------------------------------------------------------------ @@ -10262,13 +10527,15 @@ part parent "usb1286" part desc = "AT90USB162"; id = "usb162"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 178; + n_interrupts = 29; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; signature = 0x1e 0x94 0x82; usbpid = 0x2ffa; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10380,13 +10647,15 @@ part part desc = "AT90USB82"; id = "usb82"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 174; + n_interrupts = 58; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; signature = 0x1e 0x93 0x82; usbpid = 0x2ff7; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10498,13 +10767,15 @@ part part desc = "ATmega32U2"; id = "m32u2"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 64; + n_interrupts = 29; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; signature = 0x1e 0x95 0x8a; usbpid = 0x2ff0; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10616,13 +10887,15 @@ part part desc = "ATmega16U2"; id = "m16u2"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 56; + n_interrupts = 29; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; signature = 0x1e 0x94 0x89; usbpid = 0x2fef; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10734,13 +11007,15 @@ part part desc = "ATmega8U2"; id = "m8u2"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 48; + n_interrupts = 58; chip_erase_delay = 9000; pagel = 0xd7; bs2 = 0xc6; signature = 0x1e 0x93 0x89; usbpid = 0x2fee; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10852,6 +11127,9 @@ part part desc = "ATmega165"; id = "m165"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 95; + n_interrupts = 22; # stk500_devcode = 0x??; # avr910_devcode = 0x??; chip_erase_delay = 9000; @@ -10859,7 +11137,6 @@ part bs2 = 0xa0; signature = 0x1e 0x94 0x10; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -10972,6 +11249,7 @@ part part parent "m165" desc = "ATmega165A"; id = "m165a"; + mcuid = 96; ; #------------------------------------------------------------ @@ -10981,6 +11259,7 @@ part parent "m165" part parent "m165" desc = "ATmega165P"; id = "m165p"; + mcuid = 97; signature = 0x1e 0x94 0x07; ; @@ -10991,6 +11270,7 @@ part parent "m165" part parent "m165" desc = "ATmega165PA"; id = "m165pa"; + mcuid = 98; signature = 0x1e 0x94 0x07; ; @@ -11001,6 +11281,9 @@ part parent "m165" part desc = "ATmega325"; id = "m325"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 114; + n_interrupts = 23; # stk500_devcode = 0x??; # No STK500v1 support? # avr910_devcode = 0x??; # Try the ATmega16 one avr910_devcode = 0x74; @@ -11009,7 +11292,6 @@ part bs2 = 0xa0; signature = 0x1e 0x95 0x05; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -11124,6 +11406,7 @@ part part parent "m325" desc = "ATmega325A"; id = "m325a"; + mcuid = 115; ; #------------------------------------------------------------ @@ -11133,6 +11416,7 @@ part parent "m325" part parent "m325" desc = "ATmega325P"; id = "m325p"; + mcuid = 116; signature = 0x1e 0x95 0x0d; ; @@ -11143,6 +11427,8 @@ part parent "m325" part parent "m325" desc = "ATmega325PA"; id = "m325pa"; + mcuid = 117; + n_interrupts = 22; signature = 0x1e 0x95 0x0d; ; @@ -11153,6 +11439,9 @@ part parent "m325" part desc = "ATmega645"; id = "m645"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_JTAG; + mcuid = 132; + n_interrupts = 23; # stk500_devcode = 0x??; # No STK500v1 support? # avr910_devcode = 0x??; # Try the ATmega16 one avr910_devcode = 0x74; @@ -11161,7 +11450,6 @@ part bs2 = 0xa0; signature = 0x1e 0x96 0x05; reset = io; - has_jtag = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -11276,6 +11564,7 @@ part part parent "m645" desc = "ATmega645A"; id = "m645a"; + mcuid = 133; ; #------------------------------------------------------------ @@ -11285,6 +11574,7 @@ part parent "m645" part parent "m645" desc = "ATmega645P"; id = "m645p"; + mcuid = 134; signature = 0x1e 0x96 0x0d; ; @@ -11295,6 +11585,8 @@ part parent "m645" part parent "m325" desc = "ATmega3250"; id = "m3250"; + mcuid = 146; + n_interrupts = 25; signature = 0x1e 0x95 0x06; ; @@ -11305,6 +11597,8 @@ part parent "m325" part parent "m325" desc = "ATmega3250A"; id = "m3250a"; + mcuid = 147; + n_interrupts = 25; signature = 0x1e 0x95 0x06; ; @@ -11315,6 +11609,8 @@ part parent "m325" part parent "m325" desc = "ATmega3250P"; id = "m3250p"; + mcuid = 148; + n_interrupts = 25; signature = 0x1e 0x95 0x0e; ; @@ -11325,6 +11621,8 @@ part parent "m325" part parent "m325" desc = "ATmega3250PA"; id = "m3250pa"; + mcuid = 149; + n_interrupts = 25; signature = 0x1e 0x95 0x0e; ; @@ -11335,6 +11633,8 @@ part parent "m325" part parent "m645" desc = "ATmega6450"; id = "m6450"; + mcuid = 154; + n_interrupts = 25; signature = 0x1e 0x96 0x06; ; @@ -11345,6 +11645,8 @@ part parent "m645" part parent "m645" desc = "ATmega6450A"; id = "m6450a"; + mcuid = 155; + n_interrupts = 25; signature = 0x1e 0x96 0x06; ; @@ -11355,6 +11657,8 @@ part parent "m645" part parent "m645" desc = "ATmega6450P"; id = "m6450p"; + mcuid = 156; + n_interrupts = 25; signature = 0x1e 0x96 0x0e; ; @@ -11365,7 +11669,7 @@ part parent "m645" part desc = "AVR XMEGA family common values"; id = ".xmega"; - has_pdi = yes; + prog_modes = PM_SPM | PM_PDI; mcu_base = 0x0090; nvm_base = 0x01c0; @@ -11419,6 +11723,8 @@ part part parent ".xmega" desc = "ATxmega16A4U"; id = "x16a4u"; + mcuid = 232; + n_interrupts = 127; signature = 0x1e 0x94 0x41; usbpid = 0x2fe3; @@ -11472,6 +11778,7 @@ part parent ".xmega" part parent "x16a4u" desc = "ATxmega16C4"; id = "x16c4"; + mcuid = 233; signature = 0x1e 0x94 0x43; ; @@ -11482,6 +11789,8 @@ part parent "x16a4u" part parent "x16a4u" desc = "ATxmega16D4"; id = "x16d4"; + mcuid = 234; + n_interrupts = 91; signature = 0x1e 0x94 0x42; ; @@ -11492,6 +11801,8 @@ part parent "x16a4u" part parent "x16a4u" desc = "ATxmega16A4"; id = "x16a4"; + mcuid = 231; + n_interrupts = 94; memory "fuse0" size = 1; @@ -11506,6 +11817,8 @@ part parent "x16a4u" part parent ".xmega" desc = "ATxmega32A4U"; id = "x32a4u"; + mcuid = 239; + n_interrupts = 127; signature = 0x1e 0x95 0x41; usbpid = 0x2fe4; @@ -11559,6 +11872,7 @@ part parent ".xmega" part parent "x32a4u" desc = "ATxmega32C4"; id = "x32c4"; + mcuid = 240; signature = 0x1e 0x95 0x44; ; @@ -11569,6 +11883,8 @@ part parent "x32a4u" part parent "x32a4u" desc = "ATxmega32D4"; id = "x32d4"; + mcuid = 241; + n_interrupts = 91; signature = 0x1e 0x95 0x42; ; @@ -11579,6 +11895,8 @@ part parent "x32a4u" part parent "x32a4u" desc = "ATxmega32A4"; id = "x32a4"; + mcuid = 238; + n_interrupts = 94; memory "fuse0" size = 1; @@ -11593,6 +11911,8 @@ part parent "x32a4u" part parent ".xmega" desc = "ATxmega64A4U"; id = "x64a4u"; + mcuid = 252; + n_interrupts = 127; signature = 0x1e 0x96 0x46; usbpid = 0x2fe5; @@ -11646,6 +11966,7 @@ part parent ".xmega" part parent "x64a4u" desc = "ATxmega64C3"; id = "x64c3"; + mcuid = 249; signature = 0x1e 0x96 0x49; usbpid = 0x2fd6; ; @@ -11657,6 +11978,8 @@ part parent "x64a4u" part parent "x64a4u" desc = "ATxmega64D3"; id = "x64d3"; + mcuid = 250; + n_interrupts = 114; signature = 0x1e 0x96 0x4a; ; @@ -11667,6 +11990,8 @@ part parent "x64a4u" part parent "x64a4u" desc = "ATxmega64D4"; id = "x64d4"; + mcuid = 253; + n_interrupts = 91; signature = 0x1e 0x96 0x47; ; @@ -11677,8 +12002,10 @@ part parent "x64a4u" part parent "x64a4u" desc = "ATxmega64A1"; id = "x64a1"; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 243; + n_interrupts = 125; signature = 0x1e 0x96 0x4e; - has_jtag = yes; memory "fuse0" size = 1; @@ -11693,6 +12020,8 @@ part parent "x64a4u" part parent "x64a1" desc = "ATxmega64A1U"; id = "x64a1u"; + mcuid = 244; + n_interrupts = 127; usbpid = 0x2fe8; ; @@ -11703,6 +12032,8 @@ part parent "x64a1" part parent "x64a1" desc = "ATxmega64A3"; id = "x64a3"; + mcuid = 246; + n_interrupts = 122; signature = 0x1e 0x96 0x42; ; @@ -11713,6 +12044,8 @@ part parent "x64a1" part parent "x64a1" desc = "ATxmega64A3U"; id = "x64a3u"; + mcuid = 247; + n_interrupts = 127; signature = 0x1e 0x96 0x42; ; @@ -11723,6 +12056,7 @@ part parent "x64a1" part parent "x64a1" desc = "ATxmega64A4"; id = "x64a4"; + mcuid = 251; signature = 0x1e 0x96 0x46; ; @@ -11733,6 +12067,8 @@ part parent "x64a1" part parent "x64a1" desc = "ATxmega64B1"; id = "x64b1"; + mcuid = 245; + n_interrupts = 81; signature = 0x1e 0x96 0x52; usbpid = 0x2fe1; ; @@ -11744,6 +12080,8 @@ part parent "x64a1" part parent "x64a1" desc = "ATxmega64B3"; id = "x64b3"; + mcuid = 248; + n_interrupts = 54; signature = 0x1e 0x96 0x51; usbpid = 0x2fdf; ; @@ -11755,6 +12093,8 @@ part parent "x64a1" part parent ".xmega" desc = "ATxmega128C3"; id = "x128c3"; + mcuid = 261; + n_interrupts = 127; signature = 0x1e 0x97 0x52; usbpid = 0x2fd7; @@ -11808,6 +12148,8 @@ part parent ".xmega" part parent "x128c3" desc = "ATxmega128D3"; id = "x128d3"; + mcuid = 262; + n_interrupts = 114; signature = 0x1e 0x97 0x48; ; @@ -11818,6 +12160,8 @@ part parent "x128c3" part parent "x128c3" desc = "ATxmega128D4"; id = "x128d4"; + mcuid = 265; + n_interrupts = 91; signature = 0x1e 0x97 0x47; memory "flash" @@ -11832,8 +12176,10 @@ part parent "x128c3" part parent "x128c3" desc = "ATxmega128A1"; id = "x128a1"; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 254; + n_interrupts = 125; signature = 0x1e 0x97 0x4c; - has_jtag = yes; memory "fuse0" size = 1; @@ -11848,6 +12194,7 @@ part parent "x128c3" part parent "x128a1" desc = "ATxmega128A1revD"; id = "x128a1d"; + mcuid = 255; signature = 0x1e 0x97 0x41; ; @@ -11858,6 +12205,8 @@ part parent "x128a1" part parent "x128a1" desc = "ATxmega128A1U"; id = "x128a1u"; + mcuid = 256; + n_interrupts = 127; usbpid = 0x2fed; ; @@ -11868,6 +12217,8 @@ part parent "x128a1" part parent "x128a1" desc = "ATxmega128A3"; id = "x128a3"; + mcuid = 258; + n_interrupts = 122; signature = 0x1e 0x97 0x42; ; @@ -11878,6 +12229,8 @@ part parent "x128a1" part parent "x128a1" desc = "ATxmega128A3U"; id = "x128a3u"; + mcuid = 259; + n_interrupts = 127; signature = 0x1e 0x97 0x42; usbpid = 0x2fe6; ; @@ -11889,8 +12242,9 @@ part parent "x128a1" part parent ".xmega" desc = "ATxmega128A4"; id = "x128a4"; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 263; signature = 0x1e 0x97 0x46; - has_jtag = yes; memory "eeprom" size = 2048; @@ -11947,6 +12301,8 @@ part parent ".xmega" part parent ".xmega" desc = "ATxmega128A4U"; id = "x128a4u"; + mcuid = 264; + n_interrupts = 127; signature = 0x1e 0x97 0x46; usbpid = 0x2fde; @@ -12000,9 +12356,11 @@ part parent ".xmega" part parent ".xmega" desc = "ATxmega128B1"; id = "x128b1"; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 257; + n_interrupts = 81; signature = 0x1e 0x97 0x4d; usbpid = 0x2fea; - has_jtag = yes; memory "eeprom" size = 2048; @@ -12059,6 +12417,8 @@ part parent ".xmega" part parent "x128b1" desc = "ATxmega128B3"; id = "x128b3"; + mcuid = 260; + n_interrupts = 54; signature = 0x1e 0x97 0x4b; usbpid = 0x2fe0; ; @@ -12070,6 +12430,8 @@ part parent "x128b1" part parent ".xmega" desc = "ATxmega192C3"; id = "x192c3"; + mcuid = 269; + n_interrupts = 127; signature = 0x1e 0x97 0x51; # usbpid = 0x2f??; @@ -12123,6 +12485,8 @@ part parent ".xmega" part parent "x192c3" desc = "ATxmega192D3"; id = "x192d3"; + mcuid = 270; + n_interrupts = 114; signature = 0x1e 0x97 0x49; ; @@ -12133,8 +12497,9 @@ part parent "x192c3" part parent "x192c3" desc = "ATxmega192A1"; id = "x192a1"; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 266; signature = 0x1e 0x97 0x4e; - has_jtag = yes; memory "fuse0" size = 1; @@ -12149,6 +12514,8 @@ part parent "x192c3" part parent "x192a1" desc = "ATxmega192A3"; id = "x192a3"; + mcuid = 267; + n_interrupts = 122; signature = 0x1e 0x97 0x44; ; @@ -12159,6 +12526,7 @@ part parent "x192a1" part parent "x192a1" desc = "ATxmega192A3U"; id = "x192a3u"; + mcuid = 268; signature = 0x1e 0x97 0x44; usbpid = 0x2fe7; ; @@ -12170,6 +12538,8 @@ part parent "x192a1" part parent ".xmega" desc = "ATxmega256C3"; id = "x256c3"; + mcuid = 276; + n_interrupts = 127; signature = 0x1e 0x98 0x46; usbpid = 0x2fda; @@ -12223,6 +12593,8 @@ part parent ".xmega" part parent "x256c3" desc = "ATxmega256D3"; id = "x256d3"; + mcuid = 277; + n_interrupts = 114; signature = 0x1e 0x98 0x44; ; @@ -12233,7 +12605,8 @@ part parent "x256c3" part parent "x256c3" desc = "ATxmega256A1"; id = "x256a1"; - has_jtag = yes; + prog_modes = PM_SPM | PM_PDI | PM_JTAG; + mcuid = 271; memory "fuse0" size = 1; @@ -12248,6 +12621,8 @@ part parent "x256c3" part parent "x256a1" desc = "ATxmega256A3"; id = "x256a3"; + mcuid = 272; + n_interrupts = 122; signature = 0x1e 0x98 0x42; ; @@ -12258,6 +12633,7 @@ part parent "x256a1" part parent "x256a1" desc = "ATxmega256A3U"; id = "x256a3u"; + mcuid = 275; signature = 0x1e 0x98 0x42; usbpid = 0x2fec; ; @@ -12269,6 +12645,8 @@ part parent "x256a1" part parent "x256a1" desc = "ATxmega256A3B"; id = "x256a3b"; + mcuid = 273; + n_interrupts = 122; signature = 0x1e 0x98 0x43; ; @@ -12279,6 +12657,7 @@ part parent "x256a1" part parent "x256a1" desc = "ATxmega256A3BU"; id = "x256a3bu"; + mcuid = 274; signature = 0x1e 0x98 0x43; usbpid = 0x2fe2; ; @@ -12290,6 +12669,8 @@ part parent "x256a1" part parent ".xmega" desc = "ATxmega384C3"; id = "x384c3"; + mcuid = 278; + n_interrupts = 127; signature = 0x1e 0x98 0x45; usbpid = 0x2fdb; @@ -12343,6 +12724,8 @@ part parent ".xmega" part parent "x384c3" desc = "ATxmega384D3"; id = "x384d3"; + mcuid = 279; + n_interrupts = 114; signature = 0x1e 0x98 0x47; ; @@ -12353,6 +12736,8 @@ part parent "x384c3" part parent ".xmega" desc = "ATxmega8E5"; id = "x8e5"; + mcuid = 230; + n_interrupts = 43; signature = 0x1e 0x93 0x41; memory "eeprom" @@ -12405,6 +12790,8 @@ part parent ".xmega" part parent ".xmega" desc = "ATxmega16E5"; id = "x16e5"; + mcuid = 235; + n_interrupts = 43; signature = 0x1e 0x94 0x45; memory "eeprom" @@ -12457,6 +12844,8 @@ part parent ".xmega" part parent ".xmega" desc = "ATxmega32E5"; id = "x32e5"; + mcuid = 242; + n_interrupts = 43; signature = 0x1e 0x95 0x4c; memory "eeprom" @@ -12509,9 +12898,8 @@ part parent ".xmega" part desc = "AT32UC3A0512"; id = "uc3a0512"; + prog_modes = PM_JTAG | PM_aWire; signature = 0xed 0xc0 0x3f; - has_jtag = yes; - is_avr32 = yes; memory "flash" paged = yes; @@ -12539,6 +12927,10 @@ part parent "uc3a0512" part desc = "ATtiny1634"; id = "t1634"; + prog_modes = PM_SPM | PM_ISP | PM_HVPP | PM_debugWIRE; + mcuid = 40; + n_interrupts = 28; + n_page_erase = 4; stk500_devcode = 0x86; chip_erase_delay = 9000; pagel = 0xb3; @@ -12546,7 +12938,6 @@ part # avr910_devcode = 0x??; signature = 0x1e 0x94 0x12; reset = io; - has_debugwire = yes; timeout = 200; stabdelay = 100; cmdexedelay = 25; @@ -12663,6 +13054,7 @@ part part parent "t1634" desc = "ATtiny1634R"; id = "t1634r"; + mcuid = 41; ; #------------------------------------------------------------ @@ -12672,7 +13064,7 @@ part parent "t1634" part desc = "Common values for reduced core tinys"; id = ".reduced_core_tiny"; - has_tpi = yes; + prog_modes = PM_TPI; memory "fuse" size = 1; @@ -12713,6 +13105,8 @@ part part parent ".reduced_core_tiny" desc = "ATtiny4"; id = "t4"; + mcuid = 0; + n_interrupts = 10; signature = 0x1e 0x8f 0x0a; memory "flash" @@ -12730,6 +13124,8 @@ part parent ".reduced_core_tiny" part parent "t4" desc = "ATtiny5"; id = "t5"; + mcuid = 1; + n_interrupts = 11; signature = 0x1e 0x8f 0x09; ; @@ -12740,6 +13136,8 @@ part parent "t4" part parent ".reduced_core_tiny" desc = "ATtiny9"; id = "t9"; + mcuid = 2; + n_interrupts = 10; signature = 0x1e 0x90 0x08; memory "flash" @@ -12757,6 +13155,8 @@ part parent ".reduced_core_tiny" part parent "t9" desc = "ATtiny10"; id = "t10"; + mcuid = 3; + n_interrupts = 11; signature = 0x1e 0x90 0x03; ; @@ -12767,6 +13167,8 @@ part parent "t9" part parent ".reduced_core_tiny" desc = "ATtiny20"; id = "t20"; + mcuid = 4; + n_interrupts = 17; signature = 0x1e 0x91 0x0f; memory "flash" @@ -12784,6 +13186,8 @@ part parent ".reduced_core_tiny" part parent ".reduced_core_tiny" desc = "ATtiny40"; id = "t40"; + mcuid = 5; + n_interrupts = 18; signature = 0x1e 0x92 0x0e; memory "flash" @@ -12801,6 +13205,7 @@ part parent ".reduced_core_tiny" part parent ".reduced_core_tiny" desc = "ATtiny102"; id = "t102"; + mcuid = 6; signature = 0x1e 0x90 0x0c; memory "flash" @@ -12818,6 +13223,7 @@ part parent ".reduced_core_tiny" part parent ".reduced_core_tiny" desc = "ATtiny104"; id = "t104"; + mcuid = 7; signature = 0x1e 0x90 0x0b; memory "flash" @@ -12835,12 +13241,14 @@ part parent ".reduced_core_tiny" part desc = "ATmega406"; id = "m406"; + prog_modes = PM_SPM | PM_HVPP | PM_JTAG; + mcuid = 125; + n_interrupts = 23; # STK500 parameters (parallel programming IO lines) pagel = 0xa7; bs2 = 0xa0; signature = 0x1e 0x95 0x07; reset = io; - has_jtag = yes; serial = no; # STK500v2 HV programming parameters, from XML pp_controlstack = @@ -12897,7 +13305,7 @@ part part desc = "AVR8X family common values"; id = ".avr8x"; - has_updi = yes; + prog_modes = PM_SPM | PM_UPDI; nvm_base = 0x1000; ocd_base = 0x0f80; @@ -13110,6 +13518,8 @@ part parent ".avr8x" part parent ".avr8x_tiny" desc = "ATtiny202"; id = "t202"; + mcuid = 280; + n_interrupts = 26; signature = 0x1e 0x91 0x23; memory "eeprom" @@ -13134,6 +13544,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny204"; id = "t204"; + mcuid = 281; + n_interrupts = 26; signature = 0x1e 0x91 0x22; memory "eeprom" @@ -13158,6 +13570,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny402"; id = "t402"; + mcuid = 284; + n_interrupts = 26; signature = 0x1e 0x92 0x27; memory "eeprom" @@ -13182,6 +13596,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny404"; id = "t404"; + mcuid = 285; + n_interrupts = 26; signature = 0x1e 0x92 0x26; memory "eeprom" @@ -13206,6 +13622,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny406"; id = "t406"; + mcuid = 286; + n_interrupts = 26; signature = 0x1e 0x92 0x25; memory "eeprom" @@ -13230,6 +13648,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny804"; id = "t804"; + mcuid = 295; + n_interrupts = 31; signature = 0x1e 0x93 0x25; memory "eeprom" @@ -13254,6 +13674,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny806"; id = "t806"; + mcuid = 296; + n_interrupts = 31; signature = 0x1e 0x93 0x24; memory "eeprom" @@ -13278,6 +13700,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny807"; id = "t807"; + mcuid = 297; + n_interrupts = 31; signature = 0x1e 0x93 0x23; memory "eeprom" @@ -13302,6 +13726,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1604"; id = "t1604"; + mcuid = 304; + n_interrupts = 31; signature = 0x1e 0x94 0x25; memory "eeprom" @@ -13326,6 +13752,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1606"; id = "t1606"; + mcuid = 305; + n_interrupts = 31; signature = 0x1e 0x94 0x24; memory "eeprom" @@ -13350,6 +13778,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1607"; id = "t1607"; + mcuid = 306; + n_interrupts = 31; signature = 0x1e 0x94 0x23; memory "eeprom" @@ -13374,6 +13804,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny212"; id = "t212"; + mcuid = 282; + n_interrupts = 26; signature = 0x1e 0x91 0x21; memory "eeprom" @@ -13398,6 +13830,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny214"; id = "t214"; + mcuid = 283; + n_interrupts = 26; signature = 0x1e 0x91 0x20; memory "eeprom" @@ -13422,6 +13856,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny412"; id = "t412"; + mcuid = 287; + n_interrupts = 26; signature = 0x1e 0x92 0x23; memory "eeprom" @@ -13446,6 +13882,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny414"; id = "t414"; + mcuid = 288; + n_interrupts = 26; signature = 0x1e 0x92 0x22; memory "eeprom" @@ -13470,6 +13908,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny416"; id = "t416"; + mcuid = 289; + n_interrupts = 26; signature = 0x1e 0x92 0x21; memory "eeprom" @@ -13494,6 +13934,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny417"; id = "t417"; + mcuid = 291; + n_interrupts = 26; signature = 0x1e 0x92 0x20; memory "eeprom" @@ -13518,6 +13960,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny814"; id = "t814"; + mcuid = 298; + n_interrupts = 26; signature = 0x1e 0x93 0x22; memory "eeprom" @@ -13542,6 +13986,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny816"; id = "t816"; + mcuid = 299; + n_interrupts = 26; signature = 0x1e 0x93 0x21; memory "eeprom" @@ -13566,6 +14012,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny817"; id = "t817"; + mcuid = 300; + n_interrupts = 26; signature = 0x1e 0x93 0x20; memory "eeprom" @@ -13590,6 +14038,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1614"; id = "t1614"; + mcuid = 307; + n_interrupts = 31; signature = 0x1e 0x94 0x22; memory "eeprom" @@ -13614,6 +14064,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1616"; id = "t1616"; + mcuid = 308; + n_interrupts = 31; signature = 0x1e 0x94 0x21; memory "eeprom" @@ -13638,6 +14090,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1617"; id = "t1617"; + mcuid = 309; + n_interrupts = 31; signature = 0x1e 0x94 0x20; memory "eeprom" @@ -13662,6 +14116,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny3216"; id = "t3216"; + mcuid = 314; + n_interrupts = 31; signature = 0x1e 0x95 0x21; memory "eeprom" @@ -13686,6 +14142,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny3217"; id = "t3217"; + mcuid = 315; + n_interrupts = 31; signature = 0x1e 0x95 0x22; memory "eeprom" @@ -13710,6 +14168,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny424"; id = "t424"; + mcuid = 292; signature = 0x1e 0x92 0x2c; memory "eeprom" @@ -13734,6 +14193,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny426"; id = "t426"; + mcuid = 293; signature = 0x1e 0x92 0x2b; memory "eeprom" @@ -13758,6 +14218,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny427"; id = "t427"; + mcuid = 294; signature = 0x1e 0x92 0x2a; memory "eeprom" @@ -13782,6 +14243,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny824"; id = "t824"; + mcuid = 301; signature = 0x1e 0x93 0x29; memory "eeprom" @@ -13806,6 +14268,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny826"; id = "t826"; + mcuid = 302; signature = 0x1e 0x93 0x28; memory "eeprom" @@ -13830,6 +14293,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny827"; id = "t827"; + mcuid = 303; signature = 0x1e 0x93 0x27; memory "eeprom" @@ -13854,6 +14318,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1624"; id = "t1624"; + mcuid = 310; signature = 0x1e 0x94 0x2a; memory "eeprom" @@ -13878,6 +14343,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1626"; id = "t1626"; + mcuid = 311; signature = 0x1e 0x94 0x29; memory "eeprom" @@ -13902,6 +14368,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny1627"; id = "t1627"; + mcuid = 312; signature = 0x1e 0x94 0x28; memory "eeprom" @@ -13926,6 +14393,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny3224"; id = "t3224"; + mcuid = 316; signature = 0x1e 0x95 0x28; memory "eeprom" @@ -13950,6 +14418,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny3226"; id = "t3226"; + mcuid = 317; signature = 0x1e 0x95 0x27; memory "eeprom" @@ -13974,6 +14443,7 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATtiny3227"; id = "t3227"; + mcuid = 318; signature = 0x1e 0x95 0x26; memory "eeprom" @@ -13998,6 +14468,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATmega808"; id = "m808"; + mcuid = 319; + n_interrupts = 36; signature = 0x1e 0x93 0x26; memory "eeprom" @@ -14022,6 +14494,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATmega809"; id = "m809"; + mcuid = 320; + n_interrupts = 40; signature = 0x1e 0x93 0x2a; memory "eeprom" @@ -14046,6 +14520,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATmega1608"; id = "m1608"; + mcuid = 321; + n_interrupts = 36; signature = 0x1e 0x94 0x27; memory "eeprom" @@ -14070,6 +14546,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_tiny" desc = "ATmega1609"; id = "m1609"; + mcuid = 322; + n_interrupts = 40; signature = 0x1e 0x94 0x26; memory "eeprom" @@ -14094,6 +14572,8 @@ part parent ".avr8x_tiny" part parent ".avr8x_mega" desc = "ATmega3208"; id = "m3208"; + mcuid = 323; + n_interrupts = 36; signature = 0x1e 0x95 0x30; memory "eeprom" @@ -14118,6 +14598,8 @@ part parent ".avr8x_mega" part parent ".avr8x_mega" desc = "ATmega3209"; id = "m3209"; + mcuid = 324; + n_interrupts = 40; signature = 0x1e 0x95 0x31; memory "eeprom" @@ -14142,6 +14624,8 @@ part parent ".avr8x_mega" part parent ".avr8x_mega" desc = "ATmega4808"; id = "m4808"; + mcuid = 325; + n_interrupts = 36; signature = 0x1e 0x96 0x50; memory "eeprom" @@ -14166,6 +14650,8 @@ part parent ".avr8x_mega" part parent ".avr8x_mega" desc = "ATmega4809"; id = "m4809"; + mcuid = 326; + n_interrupts = 40; signature = 0x1e 0x96 0x51; memory "eeprom" @@ -14190,9 +14676,9 @@ part parent ".avr8x_mega" part desc = "AVR-Dx family common values"; id = ".avrdx"; + prog_modes = PM_SPM | PM_UPDI; # Dedicated UPDI pin, no HV hvupdi_variant = 1; - has_updi = yes; nvm_base = 0x1000; ocd_base = 0x0f80; @@ -14346,6 +14832,7 @@ part part parent ".avrdx" desc = "AVR32DA28"; id = "avr32da28"; + mcuid = 338; signature = 0x1e 0x95 0x34; memory "eeprom" @@ -14369,6 +14856,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DA32"; id = "avr32da32"; + mcuid = 342; signature = 0x1e 0x95 0x33; memory "eeprom" @@ -14392,6 +14880,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DA48"; id = "avr32da48"; + mcuid = 346; signature = 0x1e 0x95 0x32; memory "eeprom" @@ -14415,6 +14904,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DA28"; id = "avr64da28"; + mcuid = 351; signature = 0x1e 0x96 0x15; memory "eeprom" @@ -14438,6 +14928,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DA32"; id = "avr64da32"; + mcuid = 355; signature = 0x1e 0x96 0x14; memory "eeprom" @@ -14461,6 +14952,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DA48"; id = "avr64da48"; + mcuid = 359; signature = 0x1e 0x96 0x13; memory "eeprom" @@ -14484,6 +14976,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DA64"; id = "avr64da64"; + mcuid = 362; signature = 0x1e 0x96 0x12; memory "eeprom" @@ -14507,6 +15000,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DA28"; id = "avr128da28"; + mcuid = 364; signature = 0x1e 0x97 0x0a; memory "eeprom" @@ -14530,6 +15024,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DA32"; id = "avr128da32"; + mcuid = 366; signature = 0x1e 0x97 0x09; memory "eeprom" @@ -14553,6 +15048,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DA48"; id = "avr128da48"; + mcuid = 368; signature = 0x1e 0x97 0x08; memory "eeprom" @@ -14576,6 +15072,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DA64"; id = "avr128da64"; + mcuid = 370; signature = 0x1e 0x97 0x07; memory "eeprom" @@ -14599,6 +15096,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DB28"; id = "avr32db28"; + mcuid = 339; signature = 0x1e 0x95 0x37; memory "eeprom" @@ -14622,6 +15120,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DB32"; id = "avr32db32"; + mcuid = 343; signature = 0x1e 0x95 0x36; memory "eeprom" @@ -14645,6 +15144,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DB48"; id = "avr32db48"; + mcuid = 347; signature = 0x1e 0x95 0x35; memory "eeprom" @@ -14668,6 +15168,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DB28"; id = "avr64db28"; + mcuid = 352; signature = 0x1e 0x96 0x19; memory "eeprom" @@ -14691,6 +15192,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DB32"; id = "avr64db32"; + mcuid = 356; signature = 0x1e 0x96 0x18; memory "eeprom" @@ -14714,6 +15216,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DB48"; id = "avr64db48"; + mcuid = 360; signature = 0x1e 0x96 0x17; memory "eeprom" @@ -14737,6 +15240,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DB64"; id = "avr64db64"; + mcuid = 363; signature = 0x1e 0x96 0x16; memory "eeprom" @@ -14760,6 +15264,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DB28"; id = "avr128db28"; + mcuid = 365; signature = 0x1e 0x97 0x0e; memory "eeprom" @@ -14783,6 +15288,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DB32"; id = "avr128db32"; + mcuid = 367; signature = 0x1e 0x97 0x0d; memory "eeprom" @@ -14806,6 +15312,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DB48"; id = "avr128db48"; + mcuid = 369; signature = 0x1e 0x97 0x0c; memory "eeprom" @@ -14829,6 +15336,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR128DB64"; id = "avr128db64"; + mcuid = 371; signature = 0x1e 0x97 0x0b; memory "eeprom" @@ -14852,6 +15360,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR16DD14"; id = "avr16dd14"; + mcuid = 329; hvupdi_variant = 2; signature = 0x1e 0x94 0x34; @@ -14876,6 +15385,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR16DD20"; id = "avr16dd20"; + mcuid = 330; hvupdi_variant = 2; signature = 0x1e 0x94 0x33; @@ -14900,6 +15410,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR16DD28"; id = "avr16dd28"; + mcuid = 331; hvupdi_variant = 2; signature = 0x1e 0x94 0x32; @@ -14924,6 +15435,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR16DD32"; id = "avr16dd32"; + mcuid = 333; hvupdi_variant = 2; signature = 0x1e 0x94 0x31; @@ -14948,6 +15460,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DD14"; id = "avr32dd14"; + mcuid = 336; hvupdi_variant = 2; signature = 0x1e 0x95 0x3b; @@ -14972,6 +15485,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DD20"; id = "avr32dd20"; + mcuid = 337; hvupdi_variant = 2; signature = 0x1e 0x95 0x3a; @@ -14996,6 +15510,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DD28"; id = "avr32dd28"; + mcuid = 340; hvupdi_variant = 2; signature = 0x1e 0x95 0x39; @@ -15020,6 +15535,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR32DD32"; id = "avr32dd32"; + mcuid = 344; hvupdi_variant = 2; signature = 0x1e 0x95 0x38; @@ -15044,6 +15560,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DD14"; id = "avr64dd14"; + mcuid = 349; hvupdi_variant = 2; signature = 0x1e 0x96 0x1d; @@ -15068,6 +15585,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DD20"; id = "avr64dd20"; + mcuid = 350; hvupdi_variant = 2; signature = 0x1e 0x96 0x1c; @@ -15092,6 +15610,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DD28"; id = "avr64dd28"; + mcuid = 353; hvupdi_variant = 2; signature = 0x1e 0x96 0x1b; @@ -15116,6 +15635,7 @@ part parent ".avrdx" part parent ".avrdx" desc = "AVR64DD32"; id = "avr64dd32"; + mcuid = 357; hvupdi_variant = 2; signature = 0x1e 0x96 0x1a; @@ -15161,6 +15681,7 @@ part parent ".avrdx" part parent ".avrex" desc = "AVR8EA28"; id = "avr8ea28"; + mcuid = 327; signature = 0x1e 0x93 0x2c; memory "eeprom" @@ -15185,6 +15706,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR8EA32"; id = "avr8ea32"; + mcuid = 328; signature = 0x1e 0x93 0x2b; memory "eeprom" @@ -15209,6 +15731,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR16EA28"; id = "avr16ea28"; + mcuid = 332; signature = 0x1e 0x94 0x37; memory "eeprom" @@ -15233,6 +15756,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR16EA32"; id = "avr16ea32"; + mcuid = 334; signature = 0x1e 0x94 0x36; memory "eeprom" @@ -15257,6 +15781,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR16EA48"; id = "avr16ea48"; + mcuid = 335; signature = 0x1e 0x94 0x35; memory "eeprom" @@ -15281,6 +15806,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR32EA28"; id = "avr32ea28"; + mcuid = 341; signature = 0x1e 0x95 0x3e; memory "eeprom" @@ -15305,6 +15831,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR32EA32"; id = "avr32ea32"; + mcuid = 345; signature = 0x1e 0x95 0x3d; memory "eeprom" @@ -15329,6 +15856,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR32EA48"; id = "avr32ea48"; + mcuid = 348; signature = 0x1e 0x95 0x3c; memory "eeprom" @@ -15353,6 +15881,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR64EA28"; id = "avr64ea28"; + mcuid = 354; signature = 0x1e 0x96 0x20; memory "eeprom" @@ -15377,6 +15906,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR64EA32"; id = "avr64ea32"; + mcuid = 358; signature = 0x1e 0x96 0x1f; memory "eeprom" @@ -15401,6 +15931,7 @@ part parent ".avrex" part parent ".avrex" desc = "AVR64EA48"; id = "avr64ea48"; + mcuid = 361; signature = 0x1e 0x96 0x1e; memory "eeprom" @@ -15425,6 +15956,7 @@ part parent ".avrex" part parent "m88" desc = "LGT8F88P"; id = "lgt8f88p"; + mcuid = 227; signature = 0x1e 0x93 0x0f; ; @@ -15435,6 +15967,7 @@ part parent "m88" part parent "m168" desc = "LGT8F168P"; id = "lgt8f168p"; + mcuid = 228; signature = 0x1e 0x94 0x0b; ; @@ -15445,5 +15978,6 @@ part parent "m168" part parent "m328" desc = "LGT8F328P"; id = "lgt8f328p"; + mcuid = 229; signature = 0x1e 0x95 0x0f; ; diff --git a/src/avrftdi.c b/src/avrftdi.c index e80df3c0..febc4005 100644 --- a/src/avrftdi.c +++ b/src/avrftdi.c @@ -267,7 +267,7 @@ static void avrftdi_enable(PROGRAMMER *pgm, const AVRPART *p) { set_pin(pgm, PPI_AVR_BUFF, ON); // Switch to TPI initialisation in avrftdi_tpi.c - if(p->flags & AVRPART_HAS_TPI) + if(p->prog_modes & PM_TPI) avrftdi_tpi_initpgm(pgm); } @@ -808,7 +808,7 @@ static void avrftdi_close(PROGRAMMER * pgm) static int avrftdi_initialize(const PROGRAMMER *pgm, const AVRPART *p) { avrftdi_powerup(pgm); - if(p->flags & AVRPART_HAS_TPI) + if(p->prog_modes & PM_TPI) { /* see avrftdi_tpi.c */ avrftdi_tpi_initialize(pgm, p); diff --git a/src/avrintel.c b/src/avrintel.c new file mode 100644 index 00000000..edf7d114 --- /dev/null +++ b/src/avrintel.c @@ -0,0 +1,5458 @@ +/* + * Do not edit: automatically generated by mkavrintel.pl + * + * avrintel.c + * + * Atmel AVR8L, AVR8, XMEGA and AVR8X family description of interrupts and more + * + * published under GNU General Public License, version 3 (GPL-3.0) + * meta-author Stefan Rueger + * + * v 1.1 + * 30.08.2022 + * + */ + +#include "ac_cfg.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "avrintel.h" + +const uPcore_t uP_table[] = { // Value of -1 typically means unknown + //{mcu_name, mcuid, family, {sig, na, ture}, flstart, flsize, pgsiz, nb, bootsz, eestart, eesize, ep, rambeg, ramsiz, nf, nl, ni, isr_names}, // Source + {"ATtiny4", 0, F_AVR8L, {0x1E, 0x8F, 0x0A}, 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 10, vtab_attiny9}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny5", 1, F_AVR8L, {0x1E, 0x8F, 0x09}, 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 11, vtab_attiny10}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny9", 2, F_AVR8L, {0x1E, 0x90, 0x08}, 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 10, vtab_attiny9}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny10", 3, F_AVR8L, {0x1E, 0x90, 0x03}, 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 11, vtab_attiny10}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny20", 4, F_AVR8L, {0x1E, 0x91, 0x0F}, 0, 0x00800, 0x020, 0, 0, 0, 0, 0, 0x0040, 0x0080, 1, 1, 17, vtab_attiny20}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny40", 5, F_AVR8L, {0x1E, 0x92, 0x0E}, 0, 0x01000, 0x040, 0, 0, 0, 0, 0, 0x0040, 0x0100, 1, 1, 18, vtab_attiny40}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATtiny102", 6, F_AVR8L, {0x1E, 0x90, 0x0C}, 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 16, vtab_attiny104}, // atdf, avrdude, boot size (manual) + {"ATtiny104", 7, F_AVR8L, {0x1E, 0x90, 0x0B}, 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, 1, 1, 16, vtab_attiny104}, // atdf, avrdude, boot size (manual) + + {"ATtiny11", 8, F_AVR8, {0x1E, 0x90, 0x04}, 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 1, 0x0060, 0x0020, 1, 1, 5, vtab_attiny11}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny12", 9, F_AVR8, {0x1E, 0x90, 0x05}, 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, 1, 1, 6, vtab_attiny12}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny13", 10, F_AVR8, {0x1E, 0x90, 0x07}, 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, 2, 1, 10, vtab_attiny13a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny13A", 11, F_AVR8, {0x1E, 0x90, 0x07}, 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, 2, 1, 10, vtab_attiny13a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny15", 12, F_AVR8, {0x1E, 0x90, 0x06}, 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, 1, 1, 9, vtab_attiny15}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny22", 13, F_AVR8, {0x1E, 0x91, 0x06}, 0, 0x00800, -1, -1, -1, -1, -1, -1, 0x0060, 0x0080, 1, 1, 3, vtab_attiny22}, // avr-gcc 12.2.0 + {"ATtiny24", 14, F_AVR8, {0x1E, 0x91, 0x0B}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny24A", 15, F_AVR8, {0x1E, 0x91, 0x0B}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny25", 16, F_AVR8, {0x1E, 0x91, 0x08}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 15, vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny26", 17, F_AVR8, {0x1E, 0x91, 0x09}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 2, 1, 12, vtab_attiny26}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny28", 18, F_AVR8, {0x1E, 0x91, 0x07}, 0, 0x00800, 0x002, 0, 0, 0, 0, 0, 0x0060, 0x0020, 1, 1, 6, vtab_attiny28}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny43U", 19, F_AVR8, {0x1E, 0x92, 0x0C}, 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0060, 0x0100, 3, 1, 16, vtab_attiny43u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny44", 20, F_AVR8, {0x1E, 0x92, 0x07}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny44A", 21, F_AVR8, {0x1E, 0x92, 0x07}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny45", 22, F_AVR8, {0x1E, 0x92, 0x06}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 15, vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny48", 23, F_AVR8, {0x1E, 0x92, 0x09}, 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0100, 3, 1, 20, vtab_attiny88}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny84", 24, F_AVR8, {0x1E, 0x93, 0x0C}, 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny84A", 25, F_AVR8, {0x1E, 0x93, 0x0C}, 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, 3, 1, 17, vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny85", 26, F_AVR8, {0x1E, 0x93, 0x0B}, 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, 3, 1, 15, vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny87", 27, F_AVR8, {0x1E, 0x93, 0x87}, 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny88", 28, F_AVR8, {0x1E, 0x93, 0x11}, 0, 0x02000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny88}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny167", 29, F_AVR8, {0x1E, 0x94, 0x87}, 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny261", 30, F_AVR8, {0x1E, 0x91, 0x0C}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny261A", 31, F_AVR8, {0x1E, 0x91, 0x0C}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny441", 32, F_AVR8, {0x1E, 0x92, 0x15}, 0, 0x01000, 0x010, 0, 0, 0, 0x0100, 4, 0x0100, 0x0100, 3, 1, 30, vtab_attiny841}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny461", 33, F_AVR8, {0x1E, 0x92, 0x08}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny461A", 34, F_AVR8, {0x1E, 0x92, 0x08}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny828", 35, F_AVR8, {0x1E, 0x93, 0x14}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 26, vtab_attiny828}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny828R", 36, F_AVR8, {0x1E, 0x93, 0x14}, 0, 0x02000, 0x040, -1, -1, 0, 0x0100, 4, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATtiny841", 37, F_AVR8, {0x1E, 0x93, 0x15}, 0, 0x02000, 0x010, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 30, vtab_attiny841}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny861", 38, F_AVR8, {0x1E, 0x93, 0x0D}, 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny861A", 39, F_AVR8, {0x1E, 0x93, 0x0D}, 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, 3, 1, 19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1634", 40, F_AVR8, {0x1E, 0x94, 0x12}, 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, 3, 1, 28, vtab_attiny1634}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1634R", 41, F_AVR8, {0x1E, 0x94, 0x12}, 0, 0x04000, 0x020, -1, -1, 0, 0x0100, 4, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATtiny2313", 42, F_AVR8, {0x1E, 0x91, 0x0A}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 19, vtab_attiny2313}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny2313A", 43, F_AVR8, {0x1E, 0x91, 0x0A}, 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, 3, 1, 21, vtab_attiny4313}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny4313", 44, F_AVR8, {0x1E, 0x92, 0x0D}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, 3, 1, 21, vtab_attiny4313}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega8", 45, F_AVR8, {0x1E, 0x93, 0x07}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, 2, 1, 19, vtab_atmega8a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega8A", 46, F_AVR8, {0x1E, 0x93, 0x07}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, 2, 1, 19, vtab_atmega8a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega8HVA", 47, F_AVR8, {0x1E, 0x93, 0x10}, 0, 0x02000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 1, 1, 21, vtab_atmega16hva}, // atdf, avr-gcc 12.2.0 + {"ATmega8U2", 48, F_AVR8, {0x1E, 0x93, 0x89}, 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega16", 49, F_AVR8, {0x1E, 0x94, 0x03}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, 2, 1, 21, vtab_atmega16a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega16A", 50, F_AVR8, {0x1E, 0x94, 0x03}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, 2, 1, 21, vtab_atmega16a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega16HVA", 51, F_AVR8, {0x1E, 0x94, 0x0C}, 0, 0x04000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 1, 1, 21, vtab_atmega16hva}, // atdf, avr-gcc 12.2.0 + {"ATmega16HVB", 52, F_AVR8, {0x1E, 0x94, 0x0D}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, 2, 1, 29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0 + {"ATmega16HVBrevB", 53, F_AVR8, {0x1E, 0x94, 0x0D}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, 2, 1, 29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0 + {"ATmega16M1", 54, F_AVR8, {0x1E, 0x94, 0x84}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0 + {"ATmega16HVA2", 55, F_AVR8, {0x1E, 0x94, 0x0E}, 0, 0x04000, 0x080, -1, -1, -1, -1, -1, 0x0100, 0x0400, 2, 1, 22, vtab_atmega16hva2}, // avr-gcc 12.2.0 + {"ATmega16U2", 56, F_AVR8, {0x1E, 0x94, 0x89}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega16U4", 57, F_AVR8, {0x1E, 0x94, 0x88}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0500, 3, 1, 43, vtab_atmega32u4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32", 58, F_AVR8, {0x1E, 0x95, 0x02}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, 2, 1, 21, vtab_atmega323}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32A", 59, F_AVR8, {0x1E, 0x95, 0x02}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, 2, 1, 21, vtab_atmega323}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32HVB", 60, F_AVR8, {0x1E, 0x95, 0x10}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 2, 1, 29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0 + {"ATmega32HVBrevB", 61, F_AVR8, {0x1E, 0x95, 0x10}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 2, 1, 29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0 + {"ATmega32C1", 62, F_AVR8, {0x1E, 0x95, 0x86}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0 + {"ATmega32M1", 63, F_AVR8, {0x1E, 0x95, 0x84}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32U2", 64, F_AVR8, {0x1E, 0x95, 0x8A}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0400, 3, 1, 29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32U4", 65, F_AVR8, {0x1E, 0x95, 0x87}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0a00, 3, 1, 43, vtab_atmega32u4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega32U6", 66, F_AVR8, {0x1E, 0x95, 0x88}, 0, 0x08000, 0x080, 4, 0x0200, -1, -1, -1, 0x0100, 0x0a00, 3, 1, 38, vtab_atmega32u6}, // avr-gcc 12.2.0, boot size (manual) + {"ATmega48", 67, F_AVR8, {0x1E, 0x92, 0x05}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega48A", 68, F_AVR8, {0x1E, 0x92, 0x05}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega48P", 69, F_AVR8, {0x1E, 0x92, 0x0A}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega48PA", 70, F_AVR8, {0x1E, 0x92, 0x0A}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega48PB", 71, F_AVR8, {0x1E, 0x92, 0x10}, 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, 3, 1, 27, vtab_atmega168pb}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega64", 72, F_AVR8, {0x1E, 0x96, 0x02}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega64A", 73, F_AVR8, {0x1E, 0x96, 0x02}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega64HVE", 74, F_AVR8, {0x1E, 0x96, 0x10}, 0, 0x10000, 0x080, 4, 0x0400, -1, -1, -1, 0x0100, 0x1000, 2, 1, 25, vtab_atmega64hve2}, // avr-gcc 12.2.0, boot size (manual) + {"ATmega64C1", 75, F_AVR8, {0x1E, 0x96, 0x86}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0 + {"ATmega64M1", 76, F_AVR8, {0x1E, 0x96, 0x84}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega64HVE2", 77, F_AVR8, {0x1E, 0x96, 0x10}, 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, 4, 0x0100, 0x1000, 2, 1, 25, vtab_atmega64hve2}, // atdf, avr-gcc 12.2.0 + {"ATmega64RFR2", 78, F_AVR8, {0x1E, 0xA6, 0x02}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega88", 79, F_AVR8, {0x1E, 0x93, 0x0A}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega88A", 80, F_AVR8, {0x1E, 0x93, 0x0A}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega88P", 81, F_AVR8, {0x1E, 0x93, 0x0F}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega88PA", 82, F_AVR8, {0x1E, 0x93, 0x0F}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega88PB", 83, F_AVR8, {0x1E, 0x93, 0x16}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 27, vtab_atmega168pb}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega103", 84, F_AVR8, {0x1E, 0x97, 0x01}, 0, 0x20000, 0x100, -1, -1, 0, 0x1000, 1, 0x0060, 0x0fa0, 1, 1, 24, vtab_atmega103}, // avr-gcc 12.2.0, avrdude + {"ATmega128", 85, F_AVR8, {0x1E, 0x97, 0x02}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, 3, 1, 35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega128A", 86, F_AVR8, {0x1E, 0x97, 0x02}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, 3, 1, 35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega128RFA1", 87, F_AVR8, {0x1E, 0xA7, 0x01}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, 3, 1, 72, vtab_atmega128rfa1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega128RFR2", 88, F_AVR8, {0x1E, 0xA7, 0x02}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega161", 89, F_AVR8, {0x1E, 0x94, 0x01}, 0, 0x04000, 0x080, 1, 0x0400, 0, 0x0200, 1, 0x0060, 0x0400, 1, 1, 21, vtab_atmega161}, // avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATmega162", 90, F_AVR8, {0x1E, 0x94, 0x04}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 28, vtab_atmega162}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega163", 91, F_AVR8, {0x1E, 0x94, 0x02}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 1, 0x0060, 0x0400, 2, 1, 18, vtab_atmega163}, // avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATmega164A", 92, F_AVR8, {0x1E, 0x94, 0x0F}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega164P", 93, F_AVR8, {0x1E, 0x94, 0x0A}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega164PA", 94, F_AVR8, {0x1E, 0x94, 0x0A}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega165", 95, F_AVR8, {0x1E, 0x94, 0x10}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 22, vtab_atmega645p}, // avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATmega165A", 96, F_AVR8, {0x1E, 0x94, 0x10}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega165P", 97, F_AVR8, {0x1E, 0x94, 0x07}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega165PA", 98, F_AVR8, {0x1E, 0x94, 0x07}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega168", 99, F_AVR8, {0x1E, 0x94, 0x06}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega168A", 100, F_AVR8, {0x1E, 0x94, 0x06}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega168P", 101, F_AVR8, {0x1E, 0x94, 0x0B}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega168PA", 102, F_AVR8, {0x1E, 0x94, 0x0B}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega168PB", 103, F_AVR8, {0x1E, 0x94, 0x15}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 27, vtab_atmega168pb}, // atdf, avr-gcc 7.3.0, avrdude + {"ATmega169", 104, F_AVR8, {0x1E, 0x94, 0x05}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 23, vtab_atmega649p}, // avr-gcc 12.2.0, avrdude, boot size (manual) + {"ATmega169A", 105, F_AVR8, {0x1E, 0x94, 0x11}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega169P", 106, F_AVR8, {0x1E, 0x94, 0x05}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega169PA", 107, F_AVR8, {0x1E, 0x94, 0x05}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega256RFR2", 108, F_AVR8, {0x1E, 0xA8, 0x02}, 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega323", 109, F_AVR8, {0x1E, 0x95, 0x01}, 0, 0x08000, 0x080, 4, 0x0200, -1, -1, -1, 0x0060, 0x0800, 2, 1, 21, vtab_atmega323}, // avr-gcc 12.2.0, boot size (manual) + {"ATmega324A", 110, F_AVR8, {0x1E, 0x95, 0x15}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega324P", 111, F_AVR8, {0x1E, 0x95, 0x08}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega324PA", 112, F_AVR8, {0x1E, 0x95, 0x11}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega324PB", 113, F_AVR8, {0x1E, 0x95, 0x17}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 51, vtab_atmega324pb}, // atdf, avrdude + {"ATmega325", 114, F_AVR8, {0x1E, 0x95, 0x05}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega325A", 115, F_AVR8, {0x1E, 0x95, 0x05}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega325P", 116, F_AVR8, {0x1E, 0x95, 0x0D}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega325PA", 117, F_AVR8, {0x1E, 0x95, 0x0D}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega328", 118, F_AVR8, {0x1E, 0x95, 0x14}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 26, vtab_atmega328}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega328P", 119, F_AVR8, {0x1E, 0x95, 0x0F}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega328PB", 120, F_AVR8, {0x1E, 0x95, 0x16}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 45, vtab_atmega328pb}, // atdf, avr-gcc 7.3.0, avrdude + {"ATmega329", 121, F_AVR8, {0x1E, 0x95, 0x03}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega329A", 122, F_AVR8, {0x1E, 0x95, 0x03}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega329P", 123, F_AVR8, {0x1E, 0x95, 0x0B}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega329PA", 124, F_AVR8, {0x1E, 0x95, 0x0B}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega406", 125, F_AVR8, {0x1E, 0x95, 0x07}, 0, 0x0a000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0800, 2, 1, 23, vtab_atmega406}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega640", 126, F_AVR8, {0x1E, 0x96, 0x08}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, 3, 1, 57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega644", 127, F_AVR8, {0x1E, 0x96, 0x09}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 28, vtab_atmega644}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega644A", 128, F_AVR8, {0x1E, 0x96, 0x09}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega644P", 129, F_AVR8, {0x1E, 0x96, 0x0A}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega644PA", 130, F_AVR8, {0x1E, 0x96, 0x0A}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega644RFR2", 131, F_AVR8, {0x1E, 0xA6, 0x03}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega645", 132, F_AVR8, {0x1E, 0x96, 0x05}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega645A", 133, F_AVR8, {0x1E, 0x96, 0x05}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega645P", 134, F_AVR8, {0x1E, 0x96, 0x0D}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega649", 135, F_AVR8, {0x1E, 0x96, 0x03}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega649A", 136, F_AVR8, {0x1E, 0x96, 0x03}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega649P", 137, F_AVR8, {0x1E, 0x96, 0x0B}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1280", 138, F_AVR8, {0x1E, 0x97, 0x03}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, 3, 1, 57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1281", 139, F_AVR8, {0x1E, 0x97, 0x04}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, 3, 1, 57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1284", 140, F_AVR8, {0x1E, 0x97, 0x06}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, 3, 1, 35, vtab_atmega1284p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1284P", 141, F_AVR8, {0x1E, 0x97, 0x05}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, 3, 1, 35, vtab_atmega1284p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1284RFR2", 142, F_AVR8, {0x1E, 0xA7, 0x03}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega2560", 143, F_AVR8, {0x1E, 0x98, 0x01}, 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, 3, 1, 57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega2561", 144, F_AVR8, {0x1E, 0x98, 0x02}, 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, 3, 1, 57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega2564RFR2", 145, F_AVR8, {0x1E, 0xA8, 0x03}, 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, 3, 1, 77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3250", 146, F_AVR8, {0x1E, 0x95, 0x06}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3250A", 147, F_AVR8, {0x1E, 0x95, 0x06}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3250P", 148, F_AVR8, {0x1E, 0x95, 0x0E}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3250PA", 149, F_AVR8, {0x1E, 0x95, 0x0E}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3290", 150, F_AVR8, {0x1E, 0x95, 0x04}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3290A", 151, F_AVR8, {0x1E, 0x95, 0x04}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3290P", 152, F_AVR8, {0x1E, 0x95, 0x0C}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3290PA", 153, F_AVR8, {0x1E, 0x95, 0x0C}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6450", 154, F_AVR8, {0x1E, 0x96, 0x06}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6450A", 155, F_AVR8, {0x1E, 0x96, 0x06}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6450P", 156, F_AVR8, {0x1E, 0x96, 0x0E}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6490", 157, F_AVR8, {0x1E, 0x96, 0x04}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6490A", 158, F_AVR8, {0x1E, 0x96, 0x04}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega6490P", 159, F_AVR8, {0x1E, 0x96, 0x0C}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega8515", 160, F_AVR8, {0x1E, 0x93, 0x06}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, 2, 1, 17, vtab_atmega8515}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega8535", 161, F_AVR8, {0x1E, 0x93, 0x08}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, 2, 1, 21, vtab_atmega8535}, // atdf, avr-gcc 12.2.0, avrdude + {"AT43USB320", 162, F_AVR8, {0xff, -1, -1}, 0, 0x10000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0200, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"AT43USB355", 163, F_AVR8, {0xff, -1, -1}, 0, 0x06000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0400, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"AT76C711", 164, F_AVR8, {0xff, -1, -1}, 0, 0x04000, -1, -1, -1, -1, -1, -1, 0x0060, 0x07a0, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"AT86RF401", 165, F_AVR8, {0x1E, 0x91, 0x81}, 0, 0x00800, -1, -1, -1, -1, -1, -1, 0x0060, 0x0080, 0, 1, 3, vtab_at86rf401}, // avr-gcc 12.2.0 + {"AT90PWM1", 166, F_AVR8, {0x1E, 0x93, 0x83}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0 + {"AT90PWM2", 167, F_AVR8, {0x1E, 0x93, 0x81}, 0, 0x02000, 0x040, 4, -1, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 32, vtab_at90pwm2}, // avr-gcc 12.2.0, avrdude + {"AT90PWM2B", 168, F_AVR8, {0x1E, 0x93, 0x83}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 32, vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM3", 169, F_AVR8, {0x1E, 0x93, 0x81}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 32, vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM3B", 170, F_AVR8, {0x1E, 0x93, 0x83}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 32, vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90CAN32", 171, F_AVR8, {0x1E, 0x95, 0x81}, 0, 0x08000, 0x100, 4, 0x0400, 0, 0x0400, 8, 0x0100, 0x0800, 3, 1, 37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90CAN64", 172, F_AVR8, {0x1E, 0x96, 0x81}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM81", 173, F_AVR8, {0x1E, 0x93, 0x88}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0100, 3, 1, 20, vtab_at90pwm161}, // atdf, avr-gcc 12.2.0 + {"AT90USB82", 174, F_AVR8, {0x1E, 0x93, 0x82}, 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90SCR100", 175, F_AVR8, {0x1E, 0x96, 0xC1}, 0, 0x10000, 0x100, 4, 0x0200, -1, -1, -1, 0x0100, 0x1000, 3, 1, 38, vtab_at90scr100}, // avr-gcc 12.2.0, boot size (manual) + {"AT90CAN128", 176, F_AVR8, {0x1E, 0x97, 0x81}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, 3, 1, 37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM161", 177, F_AVR8, {0x1E, 0x94, 0x8B}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 20, vtab_at90pwm161}, // atdf, avr-gcc 12.2.0 + {"AT90USB162", 178, F_AVR8, {0x1E, 0x94, 0x82}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM216", 179, F_AVR8, {0x1E, 0x94, 0x83}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90PWM316", 180, F_AVR8, {0x1E, 0x94, 0x83}, 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90USB646", 181, F_AVR8, {0x1E, 0x96, 0x82}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90USB647", 182, F_AVR8, {0x1E, 0x96, 0x82}, 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, 3, 1, 38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90S1200", 183, F_AVR8, {0x1E, 0x90, 0x01}, 0, 0x00400, 0x001, -1, -1, 0, 0x0040, 1, 0x0060, 0x0020, 1, 1, 4, vtab_at90s1200}, // avr-gcc 12.2.0, avrdude + {"AT90USB1286", 184, F_AVR8, {0x1E, 0x97, 0x82}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, 3, 1, 38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90USB1287", 185, F_AVR8, {0x1E, 0x97, 0x82}, 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, 3, 1, 38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude + {"AT90S2313", 186, F_AVR8, {0x1E, 0x91, 0x01}, 0, 0x00800, 0x001, -1, -1, 0, 0x0080, 1, 0x0060, 0x0080, 1, 1, 11, vtab_at90s2313}, // avr-gcc 12.2.0, avrdude + {"AT90S2323", 187, F_AVR8, {0x1E, 0x91, 0x02}, 0, 0x00800, -1, -1, -1, -1, -1, -1, 0x0060, 0x0080, 1, 1, 3, vtab_attiny22}, // avr-gcc 12.2.0 + {"AT90S2333", 188, F_AVR8, {0x1E, 0x91, 0x05}, 0, 0x00800, 0x001, -1, -1, 0, 0x0080, 1, 0x0060, 0x0080, -1, -1, 14, vtab_at90s4433}, // avr-gcc 12.2.0, avrdude + {"AT90S2343", 189, F_AVR8, {0x1E, 0x91, 0x03}, 0, 0x00800, 0x001, -1, -1, 0, 0x0080, 1, 0x0060, 0x0080, 1, 1, 3, vtab_attiny22}, // avr-gcc 12.2.0, avrdude + {"AT90S4414", 190, F_AVR8, {0x1E, 0x92, 0x01}, 0, 0x01000, 0x001, -1, -1, 0, 0x0100, 1, 0x0060, 0x0100, 1, 1, 13, vtab_at90s8515}, // avr-gcc 12.2.0, avrdude + {"AT90S4433", 191, F_AVR8, {0x1E, 0x92, 0x03}, 0, 0x01000, 0x001, -1, -1, 0, 0x0100, 1, 0x0060, 0x0080, 1, 1, 14, vtab_at90s4433}, // avr-gcc 12.2.0, avrdude + {"AT90S4434", 192, F_AVR8, {0x1E, 0x92, 0x02}, 0, 0x01000, 0x001, -1, -1, 0, 0x0100, 1, 0x0060, 0x0100, 1, 1, 17, vtab_at90s8535}, // avr-gcc 12.2.0, avrdude + {"AT90S8515", 193, F_AVR8, {0x1E, 0x93, 0x01}, 0, 0x02000, 0x001, -1, -1, 0, 0x0200, 1, 0x0060, 0x0200, 1, 1, 13, vtab_at90s8515}, // avr-gcc 12.2.0, avrdude + {"AT90C8534", 194, F_AVR8, {0xff, -1, -1}, 0, 0x02000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0100, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"AT90S8535", 195, F_AVR8, {0x1E, 0x93, 0x03}, 0, 0x02000, 0x001, -1, -1, 0, 0x0200, 1, 0x0060, 0x0200, 1, 1, 17, vtab_at90s8535}, // avr-gcc 12.2.0, avrdude + {"AT94K", 196, F_AVR8, {0xff, -1, -1}, 0, 0x08000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0fa0, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"ATA5272", 197, F_AVR8, {0x1E, 0x93, 0x87}, 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 37, vtab_ata5272}, // atdf, avr-gcc 12.2.0 + {"ATA5505", 198, F_AVR8, {0x1E, 0x94, 0x87}, 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0 + {"ATA5700M322", 199, F_AVR8, {0x1E, 0x95, 0x67}, 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, 1, 1, 51, vtab_ata5702m322}, // atdf + {"ATA5702M322", 200, F_AVR8, {0x1E, 0x95, 0x69}, 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, 1, 1, 51, vtab_ata5702m322}, // atdf, avr-gcc 12.2.0 + {"ATA5781", 201, F_AVR8, {0x1E, 0x95, 0x64}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA5782", 202, F_AVR8, {0x1E, 0x95, 0x65}, 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf, avr-gcc 12.2.0 + {"ATA5783", 203, F_AVR8, {0x1E, 0x95, 0x66}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA5787", 204, F_AVR8, {0x1E, 0x94, 0x6C}, 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, 1, 1, 44, vtab_ata5835}, // atdf + {"ATA5790", 205, F_AVR8, {0x1E, 0x94, 0x61}, 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, 1, 1, 30, vtab_ata5790}, // atdf, avr-gcc 12.2.0 + {"ATA5790N", 206, F_AVR8, {0x1E, 0x94, 0x62}, 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, 1, 1, 31, vtab_ata5791}, // atdf, avr-gcc 12.2.0 + {"ATA5791", 207, F_AVR8, {0x1E, 0x94, 0x62}, 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, 1, 1, 31, vtab_ata5791}, // atdf, avr-gcc 7.3.0 + {"ATA5795", 208, F_AVR8, {0x1E, 0x93, 0x61}, 0, 0x02000, 0x040, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, 1, 1, 23, vtab_ata5795}, // atdf, avr-gcc 12.2.0 + {"ATA5831", 209, F_AVR8, {0x1E, 0x95, 0x61}, 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf, avr-gcc 12.2.0 + {"ATA5832", 210, F_AVR8, {0x1E, 0x95, 0x62}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA5833", 211, F_AVR8, {0x1E, 0x95, 0x63}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA5835", 212, F_AVR8, {0x1E, 0x94, 0x6B}, 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, 1, 1, 44, vtab_ata5835}, // atdf + {"ATA6285", 213, F_AVR8, {0x1E, 0x93, 0x82}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, 2, 1, 27, vtab_ata6289}, // atdf, avr-gcc 12.2.0 + {"ATA6286", 214, F_AVR8, {0x1E, 0x93, 0x82}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, 2, 1, 27, vtab_ata6289}, // atdf, avr-gcc 12.2.0 + {"ATA6289", 215, F_AVR8, {0x1E, 0x93, 0x82}, 0, 0x02000, 0x040, 4, 0x0100, -1, -1, -1, 0x0100, 0x0200, 2, 1, 27, vtab_ata6289}, // avr-gcc 12.2.0, boot size (manual) + {"ATA6612C", 216, F_AVR8, {0x1E, 0x93, 0x0A}, 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0 + {"ATA6613C", 217, F_AVR8, {0x1E, 0x94, 0x06}, 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0 + {"ATA6614Q", 218, F_AVR8, {0x1E, 0x95, 0x0F}, 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, 3, 1, 26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0 + {"ATA6616C", 219, F_AVR8, {0x1E, 0x93, 0x87}, 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0 + {"ATA6617C", 220, F_AVR8, {0x1E, 0x94, 0x87}, 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0 + {"ATA8210", 221, F_AVR8, {0x1E, 0x95, 0x65}, 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf, avr-gcc 7.3.0 + {"ATA8215", 222, F_AVR8, {0x1E, 0x95, 0x64}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA8510", 223, F_AVR8, {0x1E, 0x95, 0x61}, 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf, avr-gcc 7.3.0 + {"ATA8515", 224, F_AVR8, {0x1E, 0x95, 0x63}, -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, 1, 1, 42, vtab_ata8515}, // atdf + {"ATA664251", 225, F_AVR8, {0x1E, 0x94, 0x87}, 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, 3, 1, 20, vtab_attiny167}, // atdf, avr-gcc 12.2.0 + {"M3000", 226, F_AVR8, {0xff, -1, -1}, 0, 0x10000, -1, -1, -1, -1, -1, -1, 0x1000, 0x1000, -1, -1, 0, NULL}, // avr-gcc 12.2.0 + {"LGT8F88P", 227, F_AVR8, {0x1E, 0x93, 0x0F}, 0, 0x02000, 0x040, -1, -1, 0, 0x0200, 4, -1, -1, -1, -1, 0, NULL}, // avrdude + {"LGT8F168P", 228, F_AVR8, {0x1E, 0x94, 0x0B}, 0, 0x04000, 0x080, -1, -1, 0, 0x0200, 4, -1, -1, -1, -1, 0, NULL}, // avrdude + {"LGT8F328P", 229, F_AVR8, {0x1E, 0x95, 0x0F}, 0, 0x08000, 0x080, -1, -1, 0, 0x0400, 4, -1, -1, -1, -1, 0, NULL}, // avrdude + + {"ATxmega8E5", 230, F_XMEGA, {0x1E, 0x93, 0x41}, 0, 0x02800, 0x080, 1, 0x0800, 0, 0x0200, 32, 0x2000, 0x0400, 7, 1, 43, vtab_atxmega32e5}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega16A4", 231, F_XMEGA, {0x1E, 0x94, 0x41}, 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, 6, 1, 94, vtab_atxmega32a4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega16A4U", 232, F_XMEGA, {0x1E, 0x94, 0x41}, 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, 6, 1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega16C4", 233, F_XMEGA, {0x1E, 0x94, 0x43}, 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, 6, 1, 127, vtab_atxmega32c4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega16D4", 234, F_XMEGA, {0x1E, 0x94, 0x42}, 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, 6, 1, 91, vtab_atxmega32d4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega16E5", 235, F_XMEGA, {0x1E, 0x94, 0x45}, 0, 0x05000, 0x080, 1, 0x1000, 0, 0x0200, 32, 0x2000, 0x0800, 7, 1, 43, vtab_atxmega32e5}, // atdf, avr-gcc 7.3.0, avrdude + {"ATxmega32C3", 236, F_XMEGA, {0x1E, 0x95, 0x49}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0 + {"ATxmega32D3", 237, F_XMEGA, {0x1E, 0x95, 0x4A}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0 + {"ATxmega32A4", 238, F_XMEGA, {0x1E, 0x95, 0x41}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 94, vtab_atxmega32a4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega32A4U", 239, F_XMEGA, {0x1E, 0x95, 0x41}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega32C4", 240, F_XMEGA, {0x1E, 0x95, 0x44}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega32c4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega32D4", 241, F_XMEGA, {0x1E, 0x95, 0x42}, 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 6, 1, 91, vtab_atxmega32d4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega32E5", 242, F_XMEGA, {0x1E, 0x95, 0x4C}, 0, 0x09000, 0x080, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, 7, 1, 43, vtab_atxmega32e5}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64A1", 243, F_XMEGA, {0x1E, 0x96, 0x4E}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 125, vtab_atxmega128a1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64A1U", 244, F_XMEGA, {0x1E, 0x96, 0x4E}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega128a1u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64B1", 245, F_XMEGA, {0x1E, 0x96, 0x52}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 81, vtab_atxmega128b1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64A3", 246, F_XMEGA, {0x1E, 0x96, 0x42}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64A3U", 247, F_XMEGA, {0x1E, 0x96, 0x42}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64B3", 248, F_XMEGA, {0x1E, 0x96, 0x51}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 54, vtab_atxmega128b3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64C3", 249, F_XMEGA, {0x1E, 0x96, 0x49}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64D3", 250, F_XMEGA, {0x1E, 0x96, 0x4A}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64A4", 251, F_XMEGA, {0x1E, 0x96, 0x46}, 0, 0x11000, 0x100, -1, -1, 0, 0x0800, 32, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATxmega64A4U", 252, F_XMEGA, {0x1E, 0x96, 0x46}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega64D4", 253, F_XMEGA, {0x1E, 0x96, 0x47}, 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, 6, 1, 91, vtab_atxmega128d4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128A1", 254, F_XMEGA, {0x1E, 0x97, 0x4C}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 125, vtab_atxmega128a1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128A1revD", 255, F_XMEGA, {0x1E, 0x97, 0x41}, 0, 0x22000, 0x200, -1, -1, 0, 0x0800, 32, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATxmega128A1U", 256, F_XMEGA, {0x1E, 0x97, 0x4C}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 127, vtab_atxmega128a1u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128B1", 257, F_XMEGA, {0x1E, 0x97, 0x4D}, 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 81, vtab_atxmega128b1}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128A3", 258, F_XMEGA, {0x1E, 0x97, 0x42}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128A3U", 259, F_XMEGA, {0x1E, 0x97, 0x42}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128B3", 260, F_XMEGA, {0x1E, 0x97, 0x4B}, 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 54, vtab_atxmega128b3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128C3", 261, F_XMEGA, {0x1E, 0x97, 0x52}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128D3", 262, F_XMEGA, {0x1E, 0x97, 0x48}, 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128A4", 263, F_XMEGA, {0x1E, 0x97, 0x46}, 0, 0x22000, 0x200, -1, -1, 0, 0x0800, 32, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATxmega128A4U", 264, F_XMEGA, {0x1E, 0x97, 0x46}, 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega128D4", 265, F_XMEGA, {0x1E, 0x97, 0x47}, 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, 6, 1, 91, vtab_atxmega128d4}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega192A1", 266, F_XMEGA, {0x1E, 0x97, 0x4E}, 0, 0x32000, 0x200, -1, -1, 0, 0x0800, 32, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATxmega192A3", 267, F_XMEGA, {0x1E, 0x97, 0x44}, 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, 6, 1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega192A3U", 268, F_XMEGA, {0x1E, 0x97, 0x44}, 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, 6, 1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega192C3", 269, F_XMEGA, {0x1E, 0x97, 0x51}, 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, 6, 1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega192D3", 270, F_XMEGA, {0x1E, 0x97, 0x49}, 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256A1", 271, F_XMEGA, {0x1E, 0x98, 0x46}, 0, 0x42000, 0x200, -1, -1, 0, 0x1000, 32, -1, -1, -1, -1, 0, NULL}, // avrdude + {"ATxmega256A3", 272, F_XMEGA, {0x1E, 0x98, 0x42}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256A3B", 273, F_XMEGA, {0x1E, 0x98, 0x43}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 122, vtab_atxmega256a3b}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256A3BU", 274, F_XMEGA, {0x1E, 0x98, 0x43}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 127, vtab_atxmega256a3bu}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256A3U", 275, F_XMEGA, {0x1E, 0x98, 0x42}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256C3", 276, F_XMEGA, {0x1E, 0x98, 0x46}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega256D3", 277, F_XMEGA, {0x1E, 0x98, 0x44}, 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega384C3", 278, F_XMEGA, {0x1E, 0x98, 0x45}, 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, 6, 1, 127, vtab_atxmega384c3}, // atdf, avr-gcc 12.2.0, avrdude + {"ATxmega384D3", 279, F_XMEGA, {0x1E, 0x98, 0x47}, 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, 6, 1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude + + {"ATtiny202", 280, F_AVR8X, {0x1E, 0x91, 0x23}, 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10, 1, 26, vtab_attiny402}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny204", 281, F_AVR8X, {0x1E, 0x91, 0x22}, 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10, 1, 26, vtab_attiny404}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny212", 282, F_AVR8X, {0x1E, 0x91, 0x21}, 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10, 1, 26, vtab_attiny412}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny214", 283, F_AVR8X, {0x1E, 0x91, 0x20}, 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10, 1, 26, vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny402", 284, F_AVR8X, {0x1E, 0x92, 0x27}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny402}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny404", 285, F_AVR8X, {0x1E, 0x92, 0x26}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny404}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny406", 286, F_AVR8X, {0x1E, 0x92, 0x25}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny406}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny412", 287, F_AVR8X, {0x1E, 0x92, 0x23}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny412}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny414", 288, F_AVR8X, {0x1E, 0x92, 0x22}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny416", 289, F_AVR8X, {0x1E, 0x92, 0x21}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny416auto", 290, F_AVR8X, {0x1E, 0x92, 0x28}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny817}, // atdf + {"ATtiny417", 291, F_AVR8X, {0x1E, 0x92, 0x20}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10, 1, 26, vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny424", 292, F_AVR8X, {0x1E, 0x92, 0x2C}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny426", 293, F_AVR8X, {0x1E, 0x92, 0x2B}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny427", 294, F_AVR8X, {0x1E, 0x92, 0x2A}, 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny804", 295, F_AVR8X, {0x1E, 0x93, 0x25}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny806", 296, F_AVR8X, {0x1E, 0x93, 0x24}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny807", 297, F_AVR8X, {0x1E, 0x93, 0x23}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny814", 298, F_AVR8X, {0x1E, 0x93, 0x22}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 26, vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny816", 299, F_AVR8X, {0x1E, 0x93, 0x21}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 26, vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny817", 300, F_AVR8X, {0x1E, 0x93, 0x20}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10, 1, 26, vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny824", 301, F_AVR8X, {0x1E, 0x93, 0x29}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny826", 302, F_AVR8X, {0x1E, 0x93, 0x28}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny827", 303, F_AVR8X, {0x1E, 0x93, 0x27}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny1604", 304, F_AVR8X, {0x1E, 0x94, 0x25}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1606", 305, F_AVR8X, {0x1E, 0x94, 0x24}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1607", 306, F_AVR8X, {0x1E, 0x94, 0x23}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10, 1, 31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1614", 307, F_AVR8X, {0x1E, 0x94, 0x22}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 31, vtab_attiny1614}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1616", 308, F_AVR8X, {0x1E, 0x94, 0x21}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1617", 309, F_AVR8X, {0x1E, 0x94, 0x20}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny1624", 310, F_AVR8X, {0x1E, 0x94, 0x2A}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny1626", 311, F_AVR8X, {0x1E, 0x94, 0x29}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny1627", 312, F_AVR8X, {0x1E, 0x94, 0x28}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny3214", 313, F_AVR8X, {0x1E, 0x95, 0x20}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10, 1, 31, vtab_attiny3214}, // avr-gcc 12.2.0 + {"ATtiny3216", 314, F_AVR8X, {0x1E, 0x95, 0x21}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10, 1, 31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny3217", 315, F_AVR8X, {0x1E, 0x95, 0x22}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10, 1, 31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude + {"ATtiny3224", 316, F_AVR8X, {0x1E, 0x95, 0x28}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny3226", 317, F_AVR8X, {0x1E, 0x95, 0x27}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATtiny3227", 318, F_AVR8X, {0x1E, 0x95, 0x26}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10, 1, 30, vtab_attiny3227}, // atdf, avrdude + {"ATmega808", 319, F_AVR8X, {0x1E, 0x93, 0x26}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10, 1, 36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega809", 320, F_AVR8X, {0x1E, 0x93, 0x2A}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10, 1, 40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1608", 321, F_AVR8X, {0x1E, 0x94, 0x27}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega1609", 322, F_AVR8X, {0x1E, 0x94, 0x26}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10, 1, 40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3208", 323, F_AVR8X, {0x1E, 0x95, 0x30}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3000, 0x1000, 10, 1, 36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega3209", 324, F_AVR8X, {0x1E, 0x95, 0x31}, 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3000, 0x1000, 10, 1, 40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega4808", 325, F_AVR8X, {0x1E, 0x96, 0x50}, 0, 0x0c000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x2800, 0x1800, 10, 1, 36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude + {"ATmega4809", 326, F_AVR8X, {0x1E, 0x96, 0x51}, 0, 0x0c000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x2800, 0x1800, 10, 1, 40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude + {"AVR8EA28", 327, F_AVR8X, {0x1E, 0x93, 0x2C}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR8EA32", 328, F_AVR8X, {0x1E, 0x93, 0x2B}, 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR16DD14", 329, F_AVR8X, {0x1E, 0x94, 0x34}, 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR16DD20", 330, F_AVR8X, {0x1E, 0x94, 0x33}, 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR16DD28", 331, F_AVR8X, {0x1E, 0x94, 0x32}, 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR16EA28", 332, F_AVR8X, {0x1E, 0x94, 0x37}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR16DD32", 333, F_AVR8X, {0x1E, 0x94, 0x31}, 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR16EA32", 334, F_AVR8X, {0x1E, 0x94, 0x36}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR16EA48", 335, F_AVR8X, {0x1E, 0x94, 0x35}, 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR32DD14", 336, F_AVR8X, {0x1E, 0x95, 0x3B}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR32DD20", 337, F_AVR8X, {0x1E, 0x95, 0x3A}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR32DA28", 338, F_AVR8X, {0x1E, 0x95, 0x34}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 41, vtab_avr128da28}, // atdf, avrdude + {"AVR32DB28", 339, F_AVR8X, {0x1E, 0x95, 0x37}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 42, vtab_avr128db28}, // atdf, avrdude + {"AVR32DD28", 340, F_AVR8X, {0x1E, 0x95, 0x39}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR32EA28", 341, F_AVR8X, {0x1E, 0x95, 0x3E}, 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR32DA32", 342, F_AVR8X, {0x1E, 0x95, 0x33}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 44, vtab_avr128da32}, // atdf, avrdude + {"AVR32DB32", 343, F_AVR8X, {0x1E, 0x95, 0x36}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 44, vtab_avr128db32}, // atdf, avrdude + {"AVR32DD32", 344, F_AVR8X, {0x1E, 0x95, 0x38}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR32EA32", 345, F_AVR8X, {0x1E, 0x95, 0x3D}, 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR32DA48", 346, F_AVR8X, {0x1E, 0x95, 0x32}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 58, vtab_avr128da48}, // atdf, avrdude + {"AVR32DB48", 347, F_AVR8X, {0x1E, 0x95, 0x35}, 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, 16, 4, 61, vtab_avr128db48}, // atdf, avrdude + {"AVR32EA48", 348, F_AVR8X, {0x1E, 0x95, 0x3C}, 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, -1, -1, 0, NULL}, // avrdude + {"AVR64DD14", 349, F_AVR8X, {0x1E, 0x96, 0x1D}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR64DD20", 350, F_AVR8X, {0x1E, 0x96, 0x1C}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR64DA28", 351, F_AVR8X, {0x1E, 0x96, 0x15}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 41, vtab_avr128da28}, // atdf, avrdude + {"AVR64DB28", 352, F_AVR8X, {0x1E, 0x96, 0x19}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 42, vtab_avr128db28}, // atdf, avrdude + {"AVR64DD28", 353, F_AVR8X, {0x1E, 0x96, 0x1B}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR64EA28", 354, F_AVR8X, {0x1E, 0x96, 0x20}, 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, 16, 4, 37, vtab_avr64ea32}, // atdf, avrdude + {"AVR64DA32", 355, F_AVR8X, {0x1E, 0x96, 0x14}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 44, vtab_avr128da32}, // atdf, avrdude + {"AVR64DB32", 356, F_AVR8X, {0x1E, 0x96, 0x18}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 44, vtab_avr128db32}, // atdf, avrdude + {"AVR64DD32", 357, F_AVR8X, {0x1E, 0x96, 0x1A}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, 16, 4, 36, vtab_avr64dd32}, // atdf, avrdude + {"AVR64EA32", 358, F_AVR8X, {0x1E, 0x96, 0x1F}, 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, 16, 4, 37, vtab_avr64ea32}, // atdf, avrdude + {"AVR64DA48", 359, F_AVR8X, {0x1E, 0x96, 0x13}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 58, vtab_avr128da48}, // atdf, avrdude + {"AVR64DB48", 360, F_AVR8X, {0x1E, 0x96, 0x17}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 61, vtab_avr128db48}, // atdf, avrdude + {"AVR64EA48", 361, F_AVR8X, {0x1E, 0x96, 0x1E}, 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, 16, 4, 45, vtab_avr64ea48}, // atdf, avrdude + {"AVR64DA64", 362, F_AVR8X, {0x1E, 0x96, 0x12}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 64, vtab_avr128da64}, // atdf, avrdude + {"AVR64DB64", 363, F_AVR8X, {0x1E, 0x96, 0x16}, 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, 16, 4, 65, vtab_avr128db64}, // atdf, avrdude + {"AVR128DA28", 364, F_AVR8X, {0x1E, 0x97, 0x0A}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 41, vtab_avr128da28}, // atdf, avrdude + {"AVR128DB28", 365, F_AVR8X, {0x1E, 0x97, 0x0E}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 42, vtab_avr128db28}, // atdf, avrdude + {"AVR128DA32", 366, F_AVR8X, {0x1E, 0x97, 0x09}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 44, vtab_avr128da32}, // atdf, avrdude + {"AVR128DB32", 367, F_AVR8X, {0x1E, 0x97, 0x0D}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 44, vtab_avr128db32}, // atdf, avrdude + {"AVR128DA48", 368, F_AVR8X, {0x1E, 0x97, 0x08}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 58, vtab_avr128da48}, // atdf, avrdude + {"AVR128DB48", 369, F_AVR8X, {0x1E, 0x97, 0x0C}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 61, vtab_avr128db48}, // atdf, avrdude + {"AVR128DA64", 370, F_AVR8X, {0x1E, 0x97, 0x07}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 64, vtab_avr128da64}, // atdf, avrdude + {"AVR128DB64", 371, F_AVR8X, {0x1E, 0x97, 0x0B}, 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, 16, 4, 65, vtab_avr128db64}, // atdf, avrdude +}; + +const char * const vtab_attiny9[vts_attiny9] = { // ATtiny9, ATtiny4 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIM0_CAPT", // 3: Timer 0 Capture Event + "TIM0_OVF", // 4: Timer 0 Overflow + "TIM0_COMPA", // 5: Timer 0 Compare Match A + "TIM0_COMPB", // 6: Timer 0 Compare Match B + "ANA_COMP", // 7: Analog Comparator + "WDT", // 8: Watchdog Time-out + "VLM", // 9: Vcc Voltage Level Monitor +}; + +const char * const vtab_attiny10[vts_attiny10] = { // ATtiny10, ATtiny5 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIM0_CAPT", // 3: Timer 0 Capture Event + "TIM0_OVF", // 4: Timer 0 Overflow + "TIM0_COMPA", // 5: Timer 0 Compare Match A + "TIM0_COMPB", // 6: Timer 0 Compare Match B + "ANA_COMP", // 7: Analog Comparator + "WDT", // 8: Watchdog Time-out + "VLM", // 9: Vcc Voltage Level Monitor + "ADC", // 10: ADC Conversion Complete +}; + +const char * const vtab_attiny20[vts_attiny20] = { // ATtiny20 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIM1_CAPT", // 5: Timer 1 Capture Event + "TIM1_COMPA", // 6: Timer 1 Compare Match A + "TIM1_COMPB", // 7: Timer 1 Compare Match B + "TIM1_OVF", // 8: Timer 1 Overflow + "TIM0_COMPA", // 9: Timer 0 Compare Match A + "TIM0_COMPB", // 10: Timer 0 Compare Match B + "TIM0_OVF", // 11: Timer 0 Overflow + "ANA_COMP", // 12: Analog Comparator + "ADC_ADC", // 13: Conversion Complete + "TWI_SLAVE", // 14: 2-Wire Interface Periphery + "SPI", // 15: SPI Serial Peripheral Interface + "QTRIP", // 16: Touch Sensing +}; + +const char * const vtab_attiny40[vts_attiny40] = { // ATtiny40 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "PCINT2", // 4: Pin Change Interrupt 2 + "WDT", // 5: Watchdog Time-out + "TIM1_CAPT", // 6: Timer 1 Capture Event + "TIM1_COMPA", // 7: Timer 1 Compare Match A + "TIM1_COMPB", // 8: Timer 1 Compare Match B + "TIM1_OVF", // 9: Timer 1 Overflow + "TIM0_COMPA", // 10: Timer 0 Compare Match A + "TIM0_COMPB", // 11: Timer 0 Compare Match B + "TIM0_OVF", // 12: Timer 0 Overflow + "ANA_COMP", // 13: Analog Comparator + "ADC", // 14: ADC Conversion Complete + "TWI_SLAVE", // 15: 2-Wire Interface Periphery + "SPI", // 16: SPI Serial Peripheral Interface + "QTRIP", // 17: Touch Sensing +}; + +const char * const vtab_attiny104[vts_attiny104] = { // ATtiny104, ATtiny102 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIM0_CAPT", // 4: Timer 0 Capture Event + "TIM0_OVF", // 5: Timer 0 Overflow + "TIM0_COMPA", // 6: Timer 0 Compare Match A + "TIM0_COMPB", // 7: Timer 0 Compare Match B + "ANA_COMP", // 8: Analog Comparator + "WDT", // 9: Watchdog Time-out + "VLM", // 10: Vcc Voltage Level Monitor + "ADC", // 11: ADC Conversion Complete + "USART_RXS", // 12: USART Receive Start + "USART_RXC", // 13: USART Receive Complete + "USART_DRE", // 14: USART Data Register Empty + "USART_TXC", // 15: USART Transmit Complete +}; + +const char * const vtab_attiny11[vts_attiny11] = { // ATtiny11 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER0_OVF", // 3: Timer 0 Overflow + "ANA_COMP", // 4: Analog Comparator +}; + +const char * const vtab_attiny12[vts_attiny12] = { // ATtiny12 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER0_OVF", // 3: Timer 0 Overflow + "EE_RDY", // 4: EEPROM Ready + "ANA_COMP", // 5: Analog Comparator +}; + +const char * const vtab_attiny13a[vts_attiny13a] = { // ATtiny13A, ATtiny13 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIM0_OVF", // 3: Timer 0 Overflow + "EE_RDY", // 4: EEPROM Ready + "ANA_COMP", // 5: Analog Comparator + "TIM0_COMPA", // 6: Timer 0 Compare Match A + "TIM0_COMPB", // 7: Timer 0 Compare Match B + "WDT", // 8: Watchdog Time-out + "ADC", // 9: ADC Conversion Complete +}; + +const char * const vtab_attiny15[vts_attiny15] = { // ATtiny15 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER1_COMP", // 3: Timer 1 Compare + "TIMER1_OVF", // 4: Timer 1 Overflow + "TIMER0_OVF", // 5: Timer 0 Overflow + "EE_RDY", // 6: EEPROM Ready + "ANA_COMP", // 7: Analog Comparator + "ADC", // 8: ADC Conversion Complete +}; + +const char * const vtab_attiny22[vts_attiny22] = { // ATtiny22, AT90S2343, AT90S2323 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "TIMER0_OVF0", // 2: Timer 0 Overflow +}; + +const char * const vtab_attiny26[vts_attiny26] = { // ATtiny26 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER1_CMPA", // 3: Timer 1 Compare Match A + "TIMER1_CMPB", // 4: Timer 1 Compare Match B + "TIMER1_OVF1", // 5: Timer 1 Overflow + "TIMER0_OVF0", // 6: Timer 0 Overflow + "USI_STRT", // 7: USI Start Condition + "USI_OVF", // 8: USI Overflow + "EE_RDY", // 9: EEPROM Ready + "ANA_COMP", // 10: Analog Comparator + "ADC", // 11: ADC Conversion Complete +}; + +const char * const vtab_attiny28[vts_attiny28] = { // ATtiny28 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "LOW_LEVEL_IO_PINS", // 3: Low-level Input + "TIMER0_OVF", // 4: Timer 0 Overflow + "ANA_COMP", // 5: Analog Comparator +}; + +const char * const vtab_attiny43u[vts_attiny43u] = { // ATtiny43U + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIM1_COMPA", // 5: Timer 1 Compare Match A + "TIM1_COMPB", // 6: Timer 1 Compare Match B + "TIM1_OVF", // 7: Timer 1 Overflow + "TIM0_COMPA", // 8: Timer 0 Compare Match A + "TIM0_COMPB", // 9: Timer 0 Compare Match B + "TIM0_OVF", // 10: Timer 0 Overflow + "ANA_COMP", // 11: Analog Comparator + "ADC", // 12: ADC Conversion Complete + "EE_RDY", // 13: EEPROM Ready + "USI_START", // 14: USI Start Condition + "USI_OVF", // 15: USI Overflow +}; + +const char * const vtab_attiny84a[vts_attiny84a] = { // ATtiny84A, ATtiny84, ATtiny44A, ATtiny44, ATtiny24A, ATtiny24 + "RESET", // 0: Reset (various reasons) + "EXT_INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIM1_CAPT", // 5: Timer 1 Capture Event + "TIM1_COMPA", // 6: Timer 1 Compare Match A + "TIM1_COMPB", // 7: Timer 1 Compare Match B + "TIM1_OVF", // 8: Timer 1 Overflow + "TIM0_COMPA", // 9: Timer 0 Compare Match A + "TIM0_COMPB", // 10: Timer 0 Compare Match B + "TIM0_OVF", // 11: Timer 0 Overflow + "ANA_COMP", // 12: Analog Comparator + "ADC", // 13: ADC Conversion Complete + "EE_RDY", // 14: EEPROM Ready + "USI_STR", // 15: USI Start Condition + "USI_OVF", // 16: USI Overflow +}; + +const char * const vtab_attiny85[vts_attiny85] = { // ATtiny85, ATtiny45, ATtiny25 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIMER1_COMPA", // 3: Timer 1 Compare Match A + "TIMER1_OVF", // 4: Timer 1 Overflow + "TIMER0_OVF", // 5: Timer 0 Overflow + "EE_RDY", // 6: EEPROM Ready + "ANA_COMP", // 7: Analog Comparator + "ADC", // 8: ADC Conversion Complete + "TIMER1_COMPB", // 9: Timer 1 Compare Match B + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_COMPB", // 11: Timer 0 Compare Match B + "WDT", // 12: Watchdog Time-out + "USI_START", // 13: USI Start Condition + "USI_OVF", // 14: USI Overflow +}; + +const char * const vtab_attiny88[vts_attiny88] = { // ATtiny88, ATtiny48 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "PCINT3", // 6: Pin Change Interrupt 3 + "WDT", // 7: Watchdog Time-out + "TIMER1_CAPT", // 8: Timer 1 Capture Event + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow + "SPI_STC", // 15: SPI Serial Transfer Complete + "ADC", // 16: ADC Conversion Complete + "EE_RDY", // 17: EEPROM Ready + "ANALOG_COMP", // 18: Analog Comparator + "TWI", // 19: 2-Wire Interface +}; + +const char * const vtab_attiny167[vts_attiny167] = { // ATtiny167, ATtiny87, ATA664251, ATA6617C, ATA6616C, ATA5505 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "WDT", // 5: Watchdog Time-out + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_OVF", // 11: Timer 0 Overflow + "LIN_TC", // 12: LIN Transfer Complete + "LIN_ERR", // 13: LIN Error + "SPI_STC", // 14: SPI Serial Transfer Complete + "ADC", // 15: ADC Conversion Complete + "EE_RDY", // 16: EEPROM Ready + "ANA_COMP", // 17: Analog Comparator + "USI_START", // 18: USI Start Condition + "USI_OVF", // 19: USI Overflow +}; + +const char * const vtab_attiny828[vts_attiny828] = { // ATtiny828 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "PCINT3", // 6: Pin Change Interrupt 3 + "WDT", // 7: Watchdog Time-out + "TIMER1_CAPT", // 8: Timer 1 Capture Event + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow + "SPI_STC", // 15: SPI Serial Transfer Complete + "USART_START", // 16: USART Start + "USART_RX", // 17: USART Receive Complete + "USART_UDRE", // 18: USART Data Register Empty + "USART_TX", // 19: USART Transmit Complete + "ADC", // 20: ADC Conversion Complete + "EE_READY", // 21: EEPROM Ready + "ANALOG_COMP", // 22: Analog Comparator + "TWI_SLAVE", // 23: 2-Wire Interface Periphery + "SPM_Ready", // 24: Store Program Memory Ready + "QTRIP", // 25: Touch Sensing +}; + +const char * const vtab_attiny841[vts_attiny841] = { // ATtiny841, ATtiny441 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_COMPA", // 9: Timer 0 Compare Match A + "TIMER0_COMPB", // 10: Timer 0 Compare Match B + "TIMER0_OVF", // 11: Timer 0 Overflow + "ANA_COMP0", // 12: Analog Comparator 0 + "ADC", // 13: ADC Conversion Complete + "EE_RDY", // 14: EEPROM Ready + "ANA_COMP1", // 15: Analog Comparator 1 + "TIMER2_CAPT", // 16: Timer 2 Capture Event + "TIMER2_COMPA", // 17: Timer 2 Compare Match A + "TIMER2_COMPB", // 18: Timer 2 Compare Match B + "TIMER2_OVF", // 19: Timer 2 Overflow + "SPI", // 20: SPI Serial Peripheral Interface + "USART0_START", // 21: USART 0 Receive Start + "USART0_RX", // 22: USART 0 Receive Complete + "USART0_UDRE", // 23: USART 0 Data Register Empty + "USART0_TX", // 24: USART 0 Transmit Complete + "USART1_START", // 25: USART 1 Receive Start + "USART1_RX", // 26: USART 1 Receive Complete + "USART1_UDRE", // 27: USART 1 Data Register Empty + "USART1_TX", // 28: USART 1 Transmit Complete + "TWI_SLAVE", // 29: 2-Wire Interface Periphery +}; + +const char * const vtab_attiny861a[vts_attiny861a] = { // ATtiny861A, ATtiny861, ATtiny461A, ATtiny461, ATtiny261A, ATtiny261 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT", // 2: Pin Change Interrupt + "TIMER1_COMPA", // 3: Timer 1 Compare Match A + "TIMER1_COMPB", // 4: Timer 1 Compare Match B + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USI_START", // 7: USI Start Condition + "USI_OVF", // 8: USI Overflow + "EE_RDY", // 9: EEPROM Ready + "ANA_COMP", // 10: Analog Comparator + "ADC", // 11: ADC Conversion Complete + "WDT", // 12: Watchdog Time-out + "INT1", // 13: External Interrupt 1 + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_CAPT", // 16: Timer 0 Capture Event + "TIMER1_COMPD", // 17: Timer 1 Compare Match D + "FAULT_PROTECTION", // 18: Timer 1 Fault Protection +}; + +const char * const vtab_attiny1634[vts_attiny1634] = { // ATtiny1634 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "PCINT2", // 4: Pin Change Interrupt 2 + "WDT", // 5: Watchdog Time-out + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_COMPB", // 11: Timer 0 Compare Match B + "TIMER0_OVF", // 12: Timer 0 Overflow + "ANA_COMP", // 13: Analog Comparator + "ADC_READY", // 14: ADC Conversion Complete + "USART0_START", // 15: USART 0 Receive Start + "USART0_RXC", // 16: USART 0 Receive Complete + "USART0_UDRE", // 17: USART 0 Data Register Empty + "USART0_TXC", // 18: USART 0 Transmit Complete + "USART1_START", // 19: USART 1 Receive Start + "USART1_RXC", // 20: USART 1 Receive Complete + "USART1_UDRE", // 21: USART 1 Data Register Empty + "USART1_TXC", // 22: USART 1 Transmit Complete + "USI_START", // 23: USI Start Condition + "USI_OVERFLOW", // 24: USI Overflow + "TWI/TWI_SLAVE", // 25: 2-Wire Interface/2-Wire Interface Periphery + "EE_RDY", // 26: EEPROM Ready + "QTRIP", // 27: Touch Sensing +}; + +const char * const vtab_attiny2313[vts_attiny2313] = { // ATtiny2313 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USART_RX", // 7: USART Receive Complete + "USART_UDRE", // 8: USART Data Register Empty + "USART_TX", // 9: USART Transmit Complete + "ANA_COMP", // 10: Analog Comparator + "PCINT", // 11: Pin Change Interrupt + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "USI_START", // 15: USI Start Condition + "USI_OVERFLOW", // 16: USI Overflow + "EEPROM_Ready", // 17: EEPROM Ready + "WDT_OVERFLOW", // 18: Watchdog Timer Overflow +}; + +const char * const vtab_attiny4313[vts_attiny4313] = { // ATtiny4313, ATtiny2313A + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USART_RX", // 7: USART Receive Complete + "USART_UDRE", // 8: USART Data Register Empty + "USART_TX", // 9: USART Transmit Complete + "ANA_COMP", // 10: Analog Comparator + "PCINT_B", // 11: Pin Change Interrupt B + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "USI_START", // 15: USI Start Condition + "USI_OVERFLOW", // 16: USI Overflow + "EEPROM_Ready", // 17: EEPROM Ready + "WDT_OVERFLOW", // 18: Watchdog Timer Overflow + "PCINT_A", // 19: Pin Change Interrupt A + "PCINT_D", // 20: Pin Change Interrupt D +}; + +const char * const vtab_atmega8a[vts_atmega8a] = { // ATmega8A, ATmega8 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "USART_RXC", // 11: USART Receive Complete + "USART_UDRE", // 12: USART Data Register Empty + "USART_TXC", // 13: USART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface + "SPM_RDY", // 18: Store Program Memory Ready +}; + +const char * const vtab_atmega16a[vts_atmega16a] = { // ATmega16A, ATmega16 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "USART_RXC", // 11: USART Receive Complete + "USART_UDRE", // 12: USART Data Register Empty + "USART_TXC", // 13: USART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface + "INT2", // 18: External Interrupt 2 + "TIMER0_COMP", // 19: Timer 0 Compare Match + "SPM_RDY", // 20: Store Program Memory Ready +}; + +const char * const vtab_atmega16hva[vts_atmega16hva] = { // ATmega16HVA, ATmega8HVA + "RESET", // 0: Reset (various reasons) + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER1_IC", // 7: Timer 1 Input Capture + "TIMER1_COMPA", // 8: Timer 1 Compare Match A + "TIMER1_COMPB", // 9: Timer 1 Compare Match B + "TIMER1_OVF", // 10: Timer 1 Overflow + "TIMER0_IC", // 11: Timer 0 Capture Event + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow + "SPI_STC", // 15: SPI Serial Transfer Complete + "VADC", // 16: Voltage ADC Conversion Complete + "CCADC_CONV", // 17: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 18: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 19: Coloumb Counter ADC Accumulator + "EE_READY", // 20: EEPROM Ready +}; + +const char * const vtab_atmega16hva2[vts_atmega16hva2] = { // ATmega16HVA2 + "RESET", // 0: Reset (various reasons) + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "PCINT0", // 6: Pin Change Interrupt 0 + "WDT", // 7: Watchdog Time-out + "TIMER1_IC", // 8: Timer 1 Input Capture + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_IC", // 12: Timer 0 Capture Event + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "TIMER0_OVF", // 15: Timer 0 Overflow + "SPI_STC", // 16: SPI Serial Transfer Complete + "VADC", // 17: Voltage ADC Conversion Complete + "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator + "EE_READY", // 21: EEPROM Ready +}; + +const char * const vtab_atmega32hvbrevb[vts_atmega32hvbrevb] = { // ATmega32HVBrevB, ATmega32HVB, ATmega16HVBrevB, ATmega16HVB + "RESET", // 0: Reset (various reasons) + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "INT3", // 6: External Interrupt 3 + "PCINT0", // 7: Pin Change Interrupt 0 + "PCINT1", // 8: Pin Change Interrupt 1 + "WDT", // 9: Watchdog Time-out + "BGSCD", // 10: Bandgap Buffer Short Circuit Detected + "CHDET", // 11: Charger Detect + "TIMER1_IC", // 12: Timer 1 Input Capture + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_IC", // 16: Timer 0 Capture Event + "TIMER0_COMPA", // 17: Timer 0 Compare Match A + "TIMER0_COMPB", // 18: Timer 0 Compare Match B + "TIMER0_OVF", // 19: Timer 0 Overflow + "TWIBUSCD", // 20: 2-Wire Interface Bus Connect/Disconnect + "TWI", // 21: 2-Wire Interface + "SPI_STC", // 22: SPI Serial Transfer Complete + "VADC", // 23: Voltage ADC Conversion Complete + "CCADC_CONV", // 24: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 25: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 26: Coloumb Counter ADC Accumulator + "EE_READY", // 27: EEPROM Ready + "SPM", // 28: SPM Ready +}; + +const char * const vtab_atmega32u2[vts_atmega32u2] = { // ATmega32U2, ATmega16U2, ATmega8U2, AT90USB162, AT90USB82 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "USB_GEN", // 11: USB General + "USB_COM", // 12: USB Endpoint/Pipe Interrupt Communication Request + "WDT", // 13: Watchdog Time-out + "TIMER1_CAPT", // 14: Timer 1 Capture Event + "TIMER1_COMPA", // 15: Timer 1 Compare Match A + "TIMER1_COMPB", // 16: Timer 1 Compare Match B + "TIMER1_COMPC", // 17: Timer 1 Compare Match C + "TIMER1_OVF", // 18: Timer 1 Overflow + "TIMER0_COMPA", // 19: Timer 0 Compare Match A + "TIMER0_COMPB", // 20: Timer 0 Compare Match B + "TIMER0_OVF", // 21: Timer 0 Overflow + "SPI_STC", // 22: SPI Serial Transfer Complete + "USART1_RX", // 23: USART 1 Receive Complete + "USART1_UDRE", // 24: USART 1 Data Register Empty + "USART1_TX", // 25: USART 1 Transmit Complete + "ANALOG_COMP", // 26: Analog Comparator + "EE_READY", // 27: EEPROM Ready + "SPM_READY", // 28: Store Program Memory Ready +}; + +const char * const vtab_atmega32u4[vts_atmega32u4] = { // ATmega32U4, ATmega16U4 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "Reserved1", // 5: Reserved 1 + "Reserved2", // 6: Reserved 2 + "INT6", // 7: External Interrupt 6 + "Reserved3", // 8: Reserved 3 + "PCINT0", // 9: Pin Change Interrupt 0 + "USB_GEN", // 10: USB General + "USB_COM", // 11: USB Endpoint/Pipe Interrupt Communication Request + "WDT", // 12: Watchdog Time-out + "Reserved4", // 13: Reserved 4 + "Reserved5", // 14: Reserved 5 + "Reserved6", // 15: Reserved 6 + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART1_RX", // 25: USART 1 Receive Complete + "USART1_UDRE", // 26: USART 1 Data Register Empty + "USART1_TX", // 27: USART 1 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "TWI", // 36: 2-Wire Interface + "SPM_READY", // 37: Store Program Memory Ready + "TIMER4_COMPA", // 38: Timer 4 Compare Match A + "TIMER4_COMPB", // 39: Timer 4 Compare Match B + "TIMER4_COMPD", // 40: Timer 4 Compare Match D + "TIMER4_OVF", // 41: Timer 4 Overflow + "TIMER4_FPF", // 42: Timer 4 Fault Protection +}; + +const char * const vtab_atmega32u6[vts_atmega32u6] = { // ATmega32U6, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "USB_GEN", // 10: USB General + "USB_COM", // 11: USB Endpoint/Pipe Interrupt Communication Request + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART1_RX", // 25: USART 1 Receive Complete + "USART1_UDRE", // 26: USART 1 Data Register Empty + "USART1_TX", // 27: USART 1 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "TWI", // 36: 2-Wire Interface + "SPM_READY", // 37: Store Program Memory Ready +}; + +const char * const vtab_atmega64m1[vts_atmega64m1] = { // ATmega64M1, ATmega64C1, ATmega32M1, ATmega32C1, ATmega16M1 + "RESET", // 0: Reset (various reasons) + "ANACOMP0", // 1: Analog Comparator 0 + "ANACOMP1", // 2: Analog Comparator 1 + "ANACOMP2", // 3: Analog Comparator 2 + "ANACOMP3", // 4: Analog Comparator 3 + "PSC_FAULT", // 5: PSC Fault + "PSC_EC", // 6: PSC End of Cycle + "INT0", // 7: External Interrupt 0 + "INT1", // 8: External Interrupt 1 + "INT2", // 9: External Interrupt 2 + "INT3", // 10: External Interrupt 3 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_OVF", // 14: Timer 1 Overflow + "TIMER0_COMPA", // 15: Timer 0 Compare Match A + "TIMER0_COMPB", // 16: Timer 0 Compare Match B + "TIMER0_OVF", // 17: Timer 0 Overflow + "CAN_INT", // 18: CAN MOB, Burst, General Errors + "CAN_TOVF", // 19: CAN Timer Overflow + "LIN_TC", // 20: LIN Transfer Complete + "LIN_ERR", // 21: LIN Error + "PCINT0", // 22: Pin Change Interrupt 0 + "PCINT1", // 23: Pin Change Interrupt 1 + "PCINT2", // 24: Pin Change Interrupt 2 + "PCINT3", // 25: Pin Change Interrupt 3 + "SPI_STC", // 26: SPI Serial Transfer Complete + "ADC", // 27: ADC Conversion Complete + "WDT", // 28: Watchdog Time-out + "EE_READY", // 29: EEPROM Ready + "SPM_READY", // 30: Store Program Memory Ready +}; + +const char * const vtab_atmega64hve2[vts_atmega64hve2] = { // ATmega64HVE2, ATmega64HVE + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "WAKEUP", // 5: Wake Up + "TIMER1_IC", // 6: Timer 1 Input Capture + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_IC", // 10: Timer 0 Capture Event + "TIMER0_COMPA", // 11: Timer 0 Compare Match A + "TIMER0_COMPB", // 12: Timer 0 Compare Match B + "TIMER0_OVF", // 13: Timer 0 Overflow + "LIN_STATUS", // 14: Local Interconnect Network Status + "LIN_ERROR", // 15: Local Interconnect Network Error + "SPI_STC", // 16: SPI Serial Transfer Complete + "VADC_CONV", // 17: Versatile Analog to Digital Conversion + "VADC_ACC", // 18: Versatile Analog to Digital Compare or Capture + "CADC_CONV", // 19: C-ADC Instantaneous Conversion Complete + "CADC_REG_CUR", // 20: C-ADC Regular Current + "CADC_ACC", // 21: C-ADC Accumulated Conversion Complete + "EE_READY", // 22: EEPROM Ready + "SPM", // 23: SPM Ready + "PLL", // 24: PLL +}; + +const char * const vtab_atmega103[vts_atmega103] = { // ATmega103 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "TIMER2_COMP", // 9: Timer 2 Compare Match + "TIMER2_OVF", // 10: Timer 2 Overflow + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_OVF", // 14: Timer 1 Overflow + "TIMER0_COMP", // 15: Timer 0 Compare Match + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "UART_RX", // 18: UART Receive Complete + "UART_UDRE", // 19: UART Data Register Empty + "UART_TX", // 20: UART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator +}; + +const char * const vtab_atmega128a[vts_atmega128a] = { // ATmega128A, ATmega128, ATmega64A, ATmega64 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "TIMER2_COMP", // 9: Timer 2 Compare Match + "TIMER2_OVF", // 10: Timer 2 Overflow + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_OVF", // 14: Timer 1 Overflow + "TIMER0_COMP", // 15: Timer 0 Compare Match + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART0_RX", // 18: USART 0 Receive Complete + "USART0_UDRE", // 19: USART 0 Data Register Empty + "USART0_TX", // 20: USART 0 Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TIMER1_COMPC", // 24: Timer 1 Compare Match C + "TIMER3_CAPT", // 25: Timer 3 Capture Event + "TIMER3_COMPA", // 26: Timer 3 Compare Match A + "TIMER3_COMPB", // 27: Timer 3 Compare Match B + "TIMER3_COMPC", // 28: Timer 3 Compare Match C + "TIMER3_OVF", // 29: Timer 3 Overflow + "USART1_RX", // 30: USART 1 Receive Complete + "USART1_UDRE", // 31: USART 1 Data Register Empty + "USART1_TX", // 32: USART 1 Transmit Complete + "TWI", // 33: 2-Wire Interface + "SPM_READY", // 34: Store Program Memory Ready +}; + +const char * const vtab_atmega128rfa1[vts_atmega128rfa1] = { // ATmega128RFA1 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "PCINT2", // 11: Pin Change Interrupt 2 + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART0_RX", // 25: USART 0 Receive Complete + "USART0_UDRE", // 26: USART 0 Data Register Empty + "USART0_TX", // 27: USART 0 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "USART1_RX", // 36: USART 1 Receive Complete + "USART1_UDRE", // 37: USART 1 Data Register Empty + "USART1_TX", // 38: USART 1 Transmit Complete + "TWI", // 39: 2-Wire Interface + "SPM_READY", // 40: Store Program Memory Ready + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_COMPC", // 44: Timer 4 Compare Match C + "TIMER4_OVF", // 45: Timer 4 Overflow + "TIMER5_CAPT", // 46: Timer 5 Capture Event + "TIMER5_COMPA", // 47: Timer 5 Compare Match A + "TIMER5_COMPB", // 48: Timer 5 Compare Match B + "TIMER5_COMPC", // 49: Timer 5 Compare Match C + "TIMER5_OVF", // 50: Timer 5 Overflow + "USART2_RX", // 51: USART 2 Receive Complete + "USART2_UDRE", // 52: USART 2 Data Register Empty + "USART2_TX", // 53: USART 2 Transmit Complete + "USART3_RX", // 54: USART 3 Receive Complete + "USART3_UDRE", // 55: USART 3 Data Register Empty + "USART3_TX", // 56: USART 3 Transmit Complete + "TRX24_PLL_LOCK", // 57: TRX24 PLL Lock + "TRX24_PLL_UNLOCK", // 58: TRX24 PLL Unlock + "TRX24_RX_START", // 59: TRX24 Receive Start + "TRX24_RX_END", // 60: TRX24 Receive End + "TRX24_CCA_ED_DONE", // 61: TRX24 CCA/ED Done + "TRX24_XAH_AMI", // 62: TRX24 XAH/AMI + "TRX24_TX_END", // 63: TRX24 Transmit End + "TRX24_AWAKE", // 64: TRX24 AWAKE - Transceiver is Reaching State TRX_OFF + "SCNT_CMP1", // 65: Symbol Counter - Compare Match 1 Interrupt + "SCNT_CMP2", // 66: Symbol Counter - Compare Match 2 Interrupt + "SCNT_CMP3", // 67: Symbol Counter - Compare Match 3 Interrupt + "SCNT_OVFL", // 68: Symbol Counter - Overflow Interrupt + "SCNT_BACKOFF", // 69: Symbol Counter - Backoff Interrupt + "AES_READY", // 70: AES Engine Ready + "BAT_LOW", // 71: Battery Voltage Below Threshold +}; + +const char * const vtab_atmega161[vts_atmega161] = { // ATmega161 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "UART0_RX", // 13: UART 0 Receive Complete + "UART1_RX", // 14: UART 1 Receive Complete + "UART0_UDRE", // 15: UART 0 Data Register Empty + "UART1_UDRE", // 16: UART 1 Data Register Empty + "UART0_TX", // 17: UART 0 Transmit Complete + "UART1_TX", // 18: UART 1 Transmit Complete + "EE_RDY", // 19: EEPROM Ready + "ANA_COMP", // 20: Analog Comparator +}; + +const char * const vtab_atmega162[vts_atmega162] = { // ATmega162 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "TIMER3_CAPT", // 6: Timer 3 Capture Event + "TIMER3_COMPA", // 7: Timer 3 Compare Match A + "TIMER3_COMPB", // 8: Timer 3 Compare Match B + "TIMER3_OVF", // 9: Timer 3 Overflow + "TIMER2_COMP", // 10: Timer 2 Compare Match + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP", // 16: Timer 0 Compare Match + "TIMER0_OVF", // 17: Timer 0 Overflow + "SPI_STC", // 18: SPI Serial Transfer Complete + "USART0_RXC", // 19: USART 0 Receive Complete + "USART1_RXC", // 20: USART 1 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART1_UDRE", // 22: USART 1 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "USART1_TXC", // 24: USART 1 Transmit Complete + "EE_RDY", // 25: EEPROM Ready + "ANA_COMP", // 26: Analog Comparator + "SPM_RDY", // 27: Store Program Memory Ready +}; + +const char * const vtab_atmega163[vts_atmega163] = { // ATmega163 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "UART_RX", // 11: UART Receive Complete + "UART_UDRE", // 12: UART Data Register Empty + "UART_TX", // 13: UART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface +}; + +const char * const vtab_atmega168pb[vts_atmega168pb] = { // ATmega168PB, ATmega88PB, ATmega48PB + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_Ready", // 25: Store Program Memory Ready + "USART_START", // 26: USART Start +}; + +const char * const vtab_atmega323[vts_atmega323] = { // ATmega323, ATmega32A, ATmega32 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART_RXC", // 13: USART Receive Complete + "USART_UDRE", // 14: USART Data Register Empty + "USART_TXC", // 15: USART Transmit Complete + "ADC", // 16: ADC Conversion Complete + "EE_RDY", // 17: EEPROM Ready + "ANA_COMP", // 18: Analog Comparator + "TWI", // 19: 2-Wire Interface + "SPM_RDY", // 20: Store Program Memory Ready +}; + +const char * const vtab_atmega324pb[vts_atmega324pb] = { // ATmega324PB + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI0_STC", // 19: SPI 0 Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI0", // 26: 2-Wire Interface 0 + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_OVF", // 34: Timer 3 Overflow + "USART0_START", // 35: USART 0 Receive Start + "USART1_START", // 36: USART 1 Receive Start + "PCINT4", // 37: Pin Change Interrupt 4 + "XOSCFD", // 38: Crystal Failure Detect + "PTC_EOC", // 39: PTC End of Conversion + "PTC_WCOMP", // 40: PTC Window Comparator Mode + "SPI1_STC", // 41: SPI 1 Serial Transfer Complete + "TWI1", // 42: 2-Wire Interface 1 + "TIMER4_CAPT", // 43: Timer 4 Capture Event + "TIMER4_COMPA", // 44: Timer 4 Compare Match A + "TIMER4_COMPB", // 45: Timer 4 Compare Match B + "TIMER4_OVF", // 46: Timer 4 Overflow + "USART2_RX", // 47: USART 2 Receive Complete + "USART2_UDRE", // 48: USART 2 Data Register Empty + "USART2_TX", // 49: USART 2 Transmit Complete + "USART2_START", // 50: USART 2 Receive Start +}; + +const char * const vtab_atmega328[vts_atmega328] = { // ATmega328, ATmega168 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_READY", // 25: Store Program Memory Ready +}; + +const char * const vtab_atmega328p[vts_atmega328p] = { // ATmega328P, ATmega168PA, ATmega168P, ATmega168A, ATmega88PA, ATmega88P, ATmega88A, ATmega88, ATmega48PA, ATmega48P, ATmega48A, ATmega48, ATA6614Q, ATA6613C, ATA6612C + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_Ready", // 25: Store Program Memory Ready +}; + +const char * const vtab_atmega328pb[vts_atmega328pb] = { // ATmega328PB + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI0_STC", // 17: SPI 0 Serial Transfer Complete + "USART0_RX", // 18: USART 0 Receive Complete + "USART0_UDRE", // 19: USART 0 Data Register Empty + "USART0_TX", // 20: USART 0 Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI0", // 24: 2-Wire Interface 0 + "SPM_Ready", // 25: Store Program Memory Ready + "USART0_START", // 26: USART 0 Receive Start + "PCINT3", // 27: Pin Change Interrupt 3 + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "USART1_START", // 31: USART 1 Receive Start + "TIMER3_CAPT", // 32: Timer 3 Capture Event + "TIMER3_COMPA", // 33: Timer 3 Compare Match A + "TIMER3_COMPB", // 34: Timer 3 Compare Match B + "TIMER3_OVF", // 35: Timer 3 Overflow + "CFD", // 36: Clock Failure Detection + "PTC_EOC", // 37: PTC End of Conversion + "PTC_WCOMP", // 38: PTC Window Comparator Mode + "SPI1_STC", // 39: SPI 1 Serial Transfer Complete + "TWI1", // 40: 2-Wire Interface 1 + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_OVF", // 44: Timer 4 Overflow +}; + +const char * const vtab_atmega406[vts_atmega406] = { // ATmega406 + "RESET", // 0: Reset (various reasons) + "BPINT", // 1: Battery Protection Interrupt + "INT0", // 2: External Interrupt 0 + "INT1", // 3: External Interrupt 1 + "INT2", // 4: External Interrupt 2 + "INT3", // 5: External Interrupt 3 + "PCINT0", // 6: Pin Change Interrupt 0 + "PCINT1", // 7: Pin Change Interrupt 1 + "WDT", // 8: Watchdog Time-out + "WAKE_UP", // 9: Wake Up + "TIM1_COMP", // 10: Timer 1 Compare and Match + "TIM1_OVF", // 11: Timer 1 Overflow + "TIM0_COMPA", // 12: Timer 0 Compare Match A + "TIM0_COMPB", // 13: Timer 0 Compare Match B + "TIM0_OVF", // 14: Timer 0 Overflow + "TWI_BUS_CD", // 15: 2-Wire Interface Bus Connect/Disconnect + "TWI", // 16: 2-Wire Interface + "VADC", // 17: Voltage ADC Conversion Complete + "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator + "EE_READY", // 21: EEPROM Ready + "SPM_READY", // 22: Store Program Memory Ready +}; + +const char * const vtab_atmega644[vts_atmega644] = { // ATmega644 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready +}; + +const char * const vtab_atmega644pa[vts_atmega644pa] = { // ATmega644PA, ATmega644P, ATmega644A, ATmega324PA, ATmega324P, ATmega324A, ATmega164PA, ATmega164P, ATmega164A + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete +}; + +const char * const vtab_atmega645p[vts_atmega645p] = { // ATmega645P, ATmega645A, ATmega645, ATmega325PA, ATmega325P, ATmega325A, ATmega325, ATmega165PA, ATmega165P, ATmega165A, ATmega165 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART0_RX", // 13: USART 0 Receive Complete + "USART0_UDRE", // 14: USART 0 Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready +}; + +const char * const vtab_atmega649p[vts_atmega649p] = { // ATmega649P, ATmega649A, ATmega649, ATmega329PA, ATmega329P, ATmega329A, ATmega329, ATmega169PA, ATmega169P, ATmega169A, ATmega169 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART0_RX", // 13: USART 0 Receive Complete + "USART0_UDRE", // 14: USART 0 Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready + "LCD", // 22: LCD Start of Frame +}; + +const char * const vtab_atmega1284p[vts_atmega1284p] = { // ATmega1284P, ATmega1284 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_OVF", // 34: Timer 3 Overflow +}; + +const char * const vtab_atmega2561[vts_atmega2561] = { // ATmega2561, ATmega2560, ATmega1281, ATmega1280, ATmega640 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "PCINT2", // 11: Pin Change Interrupt 2 + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART0_RX", // 25: USART 0 Receive Complete + "USART0_UDRE", // 26: USART 0 Data Register Empty + "USART0_TX", // 27: USART 0 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "USART1_RX", // 36: USART 1 Receive Complete + "USART1_UDRE", // 37: USART 1 Data Register Empty + "USART1_TX", // 38: USART 1 Transmit Complete + "TWI", // 39: 2-Wire Interface + "SPM_READY", // 40: Store Program Memory Ready + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_COMPC", // 44: Timer 4 Compare Match C + "TIMER4_OVF", // 45: Timer 4 Overflow + "TIMER5_CAPT", // 46: Timer 5 Capture Event + "TIMER5_COMPA", // 47: Timer 5 Compare Match A + "TIMER5_COMPB", // 48: Timer 5 Compare Match B + "TIMER5_COMPC", // 49: Timer 5 Compare Match C + "TIMER5_OVF", // 50: Timer 5 Overflow + "USART2_RX", // 51: USART 2 Receive Complete + "USART2_UDRE", // 52: USART 2 Data Register Empty + "USART2_TX", // 53: USART 2 Transmit Complete + "USART3_RX", // 54: USART 3 Receive Complete + "USART3_UDRE", // 55: USART 3 Data Register Empty + "USART3_TX", // 56: USART 3 Transmit Complete +}; + +const char * const vtab_atmega2564rfr2[vts_atmega2564rfr2] = { // ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "PCINT2", // 11: Pin Change Interrupt 2 + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART0_RX", // 25: USART 0 Receive Complete + "USART0_UDRE", // 26: USART 0 Data Register Empty + "USART0_TX", // 27: USART 0 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "USART1_RX", // 36: USART 1 Receive Complete + "USART1_UDRE", // 37: USART 1 Data Register Empty + "USART1_TX", // 38: USART 1 Transmit Complete + "TWI", // 39: 2-Wire Interface + "SPM_READY", // 40: Store Program Memory Ready + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_COMPC", // 44: Timer 4 Compare Match C + "TIMER4_OVF", // 45: Timer 4 Overflow + "TIMER5_CAPT", // 46: Timer 5 Capture Event + "TIMER5_COMPA", // 47: Timer 5 Compare Match A + "TIMER5_COMPB", // 48: Timer 5 Compare Match B + "TIMER5_COMPC", // 49: Timer 5 Compare Match C + "TIMER5_OVF", // 50: Timer 5 Overflow + "RESERVED_51", // 51: Reserved 51 + "RESERVED_52", // 52: Reserved 52 + "RESERVED_53", // 53: Reserved 53 + "RESERVED_54", // 54: Reserved 54 + "RESERVED_55", // 55: Reserved 55 + "RESERVED_56", // 56: Reserved 56 + "TRX24_PLL_LOCK", // 57: TRX24 PLL Lock + "TRX24_PLL_UNLOCK", // 58: TRX24 PLL Unlock + "TRX24_RX_START", // 59: TRX24 Receive Start + "TRX24_RX_END", // 60: TRX24 Receive End + "TRX24_CCA_ED_DONE", // 61: TRX24 CCA/ED Done + "TRX24_XAH_AMI", // 62: TRX24 XAH/AMI + "TRX24_TX_END", // 63: TRX24 Transmit End + "TRX24_AWAKE", // 64: TRX24 AWAKE - Transceiver is Reaching State TRX_OFF + "SCNT_CMP1", // 65: Symbol Counter - Compare Match 1 Interrupt + "SCNT_CMP2", // 66: Symbol Counter - Compare Match 2 Interrupt + "SCNT_CMP3", // 67: Symbol Counter - Compare Match 3 Interrupt + "SCNT_OVFL", // 68: Symbol Counter - Overflow Interrupt + "SCNT_BACKOFF", // 69: Symbol Counter - Backoff Interrupt + "AES_READY", // 70: AES Engine Ready + "BAT_LOW", // 71: Battery Voltage Below Threshold + "TRX24_TX_START", // 72: TRX24 Transmit Start + "TRX24_AMI0", // 73: TRX24 Address Match 0 + "TRX24_AMI1", // 74: TRX24 Address Match 1 + "TRX24_AMI2", // 75: TRX24 Address Match 2 + "TRX24_AMI3", // 76: TRX24 Address Match 3 +}; + +const char * const vtab_atmega6450p[vts_atmega6450p] = { // ATmega6450P, ATmega6450A, ATmega6450, ATmega3250PA, ATmega3250P, ATmega3250A, ATmega3250 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART_RX", // 13: USART Receive Complete + "USART_UDRE", // 14: USART Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready + "NOT_USED", // 22: Reserved + "PCINT2", // 23: Pin Change Interrupt 2 + "PCINT3", // 24: Pin Change Interrupt 3 +}; + +const char * const vtab_atmega6490p[vts_atmega6490p] = { // ATmega6490P, ATmega6490A, ATmega6490, ATmega3290PA, ATmega3290P, ATmega3290A, ATmega3290 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART_RX", // 13: USART Receive Complete + "USART_UDRE", // 14: USART Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready + "LCD", // 22: LCD Start of Frame + "PCINT2", // 23: Pin Change Interrupt 2 + "PCINT3", // 24: Pin Change Interrupt 3 +}; + +const char * const vtab_atmega8515[vts_atmega8515] = { // ATmega8515 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_COMPB", // 5: Timer 1 Compare Match B + "TIMER1_OVF", // 6: Timer 1 Overflow + "TIMER0_OVF", // 7: Timer 0 Overflow + "SPI_STC", // 8: SPI Serial Transfer Complete + "USART_RX", // 9: USART Receive Complete + "USART_UDRE", // 10: USART Data Register Empty + "USART_TX", // 11: USART Transmit Complete + "ANA_COMP", // 12: Analog Comparator + "INT2", // 13: External Interrupt 2 + "TIMER0_COMP", // 14: Timer 0 Compare Match + "EE_RDY", // 15: EEPROM Ready + "SPM_RDY", // 16: Store Program Memory Ready +}; + +const char * const vtab_atmega8535[vts_atmega8535] = { // ATmega8535 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "USART_RX", // 11: USART Receive Complete + "USART_UDRE", // 12: USART Data Register Empty + "USART_TX", // 13: USART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface + "INT2", // 18: External Interrupt 2 + "TIMER0_COMP", // 19: Timer 0 Compare Match + "SPM_RDY", // 20: Store Program Memory Ready +}; + +const char * const vtab_at86rf401[vts_at86rf401] = { // AT86RF401 + "RESET", // 0: Reset (various reasons) + "TXDONE", // 1: Transmit Complete + "TXEMPTY", // 2: Transmit Register Empty +}; + +const char * const vtab_at90pwm2[vts_at90pwm2] = { // AT90PWM2 + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "UNUSED", // 14: not implemented on this device + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP_A", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "SPM_READY", // 31: Store Program Memory Ready +}; + +const char * const vtab_at90pwm3b[vts_at90pwm3b] = { // AT90PWM3B, AT90PWM3, AT90PWM2B + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "RESERVED15", // 14: Reserved 15 + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "RESERVED30", // 29: Reserved 30 + "RESERVED31", // 30: Reserved 31 + "SPM_READY", // 31: Store Program Memory Ready +}; + +const char * const vtab_at90scr100[vts_at90scr100] = { // AT90SCR100 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "PCINT0", // 5: Pin Change Interrupt 0 + "PCINT1", // 6: Pin Change Interrupt 1 + "PCINT2", // 7: Pin Change Interrupt 2 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "SUPPLY_MON", // 23: Supply Monitor + "RFU", // 24: Reserved for Future Use + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "KEYBOARD", // 28: Keyboard Input Change + "AES_Operation", // 29: AES Operation + "HSSPI", // 30: High-Speed SPI + "USB_Endpoint", // 31: USB Endpoint + "USB_Protocol", // 32: USB Protocol + "SCIB", // 33: Smart Card Reader Interface + "USBHost_Control", // 34: USB Host Controller + "USBHost_Pipe", // 35: USB Host Pipe + "CPRES", // 36: Card Presence Detection + "PCINT3", // 37: Pin Change Interrupt 3 +}; + +const char * const vtab_at90can128[vts_at90can128] = { // AT90CAN128, AT90CAN64, AT90CAN32 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "TIMER2_COMP", // 9: Timer 2 Compare Match + "TIMER2_OVF", // 10: Timer 2 Overflow + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_COMPC", // 14: Timer 1 Compare Match C + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP", // 16: Timer 0 Compare Match + "TIMER0_OVF", // 17: Timer 0 Overflow + "CANIT", // 18: CAN Transfer Complete or Error + "OVRIT", // 19: CAN Timer Overrun + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART0_RX", // 21: USART 0 Receive Complete + "USART0_UDRE", // 22: USART 0 Data Register Empty + "USART0_TX", // 23: USART 0 Transmit Complete + "ANALOG_COMP", // 24: Analog Comparator + "ADC", // 25: ADC Conversion Complete + "EE_READY", // 26: EEPROM Ready + "TIMER3_CAPT", // 27: Timer 3 Capture Event + "TIMER3_COMPA", // 28: Timer 3 Compare Match A + "TIMER3_COMPB", // 29: Timer 3 Compare Match B + "TIMER3_COMPC", // 30: Timer 3 Compare Match C + "TIMER3_OVF", // 31: Timer 3 Overflow + "USART1_RX", // 32: USART 1 Receive Complete + "USART1_UDRE", // 33: USART 1 Data Register Empty + "USART1_TX", // 34: USART 1 Transmit Complete + "TWI", // 35: 2-Wire Interface + "SPM_READY", // 36: Store Program Memory Ready +}; + +const char * const vtab_at90pwm161[vts_at90pwm161] = { // AT90PWM161, AT90PWM81 + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC2_EEC", // 3: PSC 2 End Of Enhanced Cycle + "PSC0_CAPT", // 4: PSC 0 Capture Event + "PSC0_EC", // 5: PSC 0 End Cycle + "PSC0_EEC", // 6: PSC 0 End Of Enhanced Cycle + "ANALOG_COMP_1", // 7: Analog Comparator 1 + "ANALOG_COMP_2", // 8: Analog Comparator 2 + "ANALOG_COMP_3", // 9: Analog Comparator 3 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_OVF", // 12: Timer 1 Overflow + "ADC", // 13: ADC Conversion Complete + "INT1", // 14: External Interrupt 1 + "SPI_STC", // 15: SPI Serial Transfer Complete + "INT2", // 16: External Interrupt 2 + "WDT", // 17: Watchdog Time-out + "EE_READY", // 18: EEPROM Ready + "SPM_READY", // 19: Store Program Memory Ready +}; + +const char * const vtab_at90pwm316[vts_at90pwm316] = { // AT90PWM316, AT90PWM216, AT90PWM1 + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "RESERVED15", // 14: Reserved 15 + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP_A", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "RESERVED30", // 29: Reserved 30 + "RESERVED31", // 30: Reserved 31 + "SPM_READY", // 31: Store Program Memory Ready +}; + +const char * const vtab_at90s1200[vts_at90s1200] = { // AT90S1200 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "TIMER0_OVF", // 2: Timer 0 Overflow + "ANA_COMP", // 3: Analog Comparator +}; + +const char * const vtab_at90s2313[vts_at90s2313] = { // AT90S2313 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT1", // 3: Timer 1 Capture Event + "TIMER1_COMP1", // 4: Timer 1 Compare + "TIMER1_OVF1", // 5: Timer 1 Overflow + "TIMER0_OVF0", // 6: Timer 0 Overflow + "UART_RX", // 7: UART Receive Complete + "UART_UDRE", // 8: UART Data Register Empty + "UART_TX", // 9: UART Transmit Complete + "ANA_COMP", // 10: Analog Comparator +}; + +const char * const vtab_at90s4433[vts_at90s4433] = { // AT90S4433, AT90S2333 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMP", // 4: Timer 1 Compare + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "SPI_STC", // 7: SPI Serial Transfer Complete + "UART_RX", // 8: UART Receive Complete + "UART_UDRE", // 9: UART Data Register Empty + "UART_TX", // 10: UART Transmit Complete + "ADC", // 11: ADC Conversion Complete + "EE_RDY", // 12: EEPROM Ready + "ANA_COMP", // 13: Analog Comparator +}; + +const char * const vtab_at90s8515[vts_at90s8515] = { // AT90S8515, AT90S4414 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_COMPB", // 5: Timer 1 Compare Match B + "TIMER1_OVF", // 6: Timer 1 Overflow + "TIMER0_OVF", // 7: Timer 0 Overflow + "SPI_STC", // 8: SPI Serial Transfer Complete + "UART_RX", // 9: UART Receive Complete + "UART_UDRE", // 10: UART Data Register Empty + "UART_TX", // 11: UART Transmit Complete + "ANA_COMP", // 12: Analog Comparator +}; + +const char * const vtab_at90s8535[vts_at90s8535] = { // AT90S8535, AT90S4434 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "UART_RX", // 11: UART Receive Complete + "UART_UDRE", // 12: UART Data Register Empty + "UART_TX", // 13: UART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator +}; + +const char * const vtab_ata5272[vts_ata5272] = { // ATA5272 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "WDT", // 5: Watchdog Time-out + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_OVF", // 11: Timer 0 Overflow + "LIN_TC", // 12: LIN Transfer Complete + "LIN_ERR", // 13: LIN Error + "SPI_STC", // 14: SPI Serial Transfer Complete + "ADC", // 15: ADC Conversion Complete + "EE_RDY", // 16: EEPROM Ready + "UNUSED", // 17: not implemented on this device + "UNUSED", // 18: not implemented on this device + "USI_OVF", // 19: USI Overflow + "UNUSED", // 20: not implemented on this device + "UNUSED", // 21: not implemented on this device + "UNUSED", // 22: not implemented on this device + "UNUSED", // 23: not implemented on this device + "UNUSED", // 24: not implemented on this device + "UNUSED", // 25: not implemented on this device + "UNUSED", // 26: not implemented on this device + "UNUSED", // 27: not implemented on this device + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "UNUSED", // 32: not implemented on this device + "UNUSED", // 33: not implemented on this device + "ANA_COMP", // 34: Analog Comparator + "UNUSED", // 35: not implemented on this device + "USI_START", // 36: USI Start Condition +}; + +const char * const vtab_ata5702m322[vts_ata5702m322] = { // ATA5702M322, ATA5700M322 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCI0", // 3: Pin Change Interrupt Request 0 + "PCI1", // 4: Pin Change Interrupt Request 1 + "VMON", // 5: Voltage Monitoring + "AVCCR", // 6: AVCC Reset + "AVCCL", // 7: AVCC Low + "T0INT", // 8: Timer 0 Interrupt + "T1COMP", // 9: Timer 1 Compare and Match + "T1OVF", // 10: Timer 1 Overflow + "T2COMP", // 11: Timer 2 Compare and Match + "T2OVF", // 12: Timer 2 Overflow + "T3CAP", // 13: Timer 3 Capture Event + "T3COMP", // 14: Timer 3 Compare and Match + "T3OVF", // 15: Timer 3 Overflow + "T4CAP", // 16: Timer 4 Capture Event + "T4COMP", // 17: Timer 4 Compare and Match + "T4OVF", // 18: Timer 4 Overflow + "T5COMP", // 19: Timer 5 Compare and Match + "T5OVF", // 20: Timer 5 Overflow + "SPI", // 21: SPI Serial Peripheral Interface + "SRX_FIFO", // 22: SPI Receive Buffer + "STX_FIFO", // 23: SPI Transmit Buffer + "SSM", // 24: Sequencer State Machine + "DFFLR", // 25: Data FIFO Fill Level Reached + "DFOUE", // 26: Data FIFO Overflow or Underflow Error + "SFFLR", // 27: RSSI/Preamble FIFO Fill Level Reached + "SFOUE", // 28: RSSI/Preamble FIFO Overflow or Underflow Error + "TMTCF", // 29: Transmit Modulator Telegram Finished + "AES", // 30: AES Crypto Unit + "TPINT", // 31: Transponder Mode Interrupt + "TPTOERR", // 32: Transponder Timeout Error + "LFID0INT", // 33: LF Receiver Identifier 0 Interrupt + "LFID1INT", // 34: LF Receiver Identifier 1 Interrupt + "LFFEINT", // 35: LF Receiver Frame End Interrupt + "LFBCR", // 36: LF Receiver Bit Count Reached + "LFPBD", // 37: LF Receiver PreBurst Detected + "LFDE", // 38: LF Receiver Decoder Error + "LFEOT", // 39: LF Receiver End of Telegram + "LFTCOR", // 40: LF Receiver Timer Compare + "LFRSCO", // 41: LF Receiver RSSI Measurement + "LDFFLR", // 42: Data FIFO Fill Level Reached + "LDFOUE", // 43: Data FIFO Overflow or Underflow Error + "EXCM", // 44: External Input Clock Break Down + "E2CINT", // 45: EEPROM Error Correction Interrupt + "ERDY", // 46: EEPROM Ready + "SPMR", // 47: Store Program Memory Ready + "TWI1", // 48: 2-Wire Interface 1 + "SPI2", // 49: SPI 2 Serial Peripheral Interface + "TWI2", // 50: 2-Wire Interface 2 +}; + +const char * const vtab_ata5790[vts_ata5790] = { // ATA5790 + "RESET", // 0: Reset (various reasons) + "TPINT", // 1: Transponder Mode Interrupt + "INT0", // 2: External Interrupt 0 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "VMINT", // 5: Voltage Monitoring Interrupt + "T0INT", // 6: Timer 0 Interrupt + "LFID0INT", // 7: LF Receiver Identifier 0 Interrupt + "LFID1INT", // 8: LF Receiver Identifier 1 Interrupt + "LFFEINT", // 9: LF Receiver Frame End Interrupt + "LFDBINT", // 10: LF Receiver Data Buffer Full Interrupt + "T3CAPINT", // 11: Timer 3 Capture Event Interrupt + "T3COMINT", // 12: Timer 3 Compare and Match Interrupt + "T3OVFINT", // 13: Timer 3 Overflow Interrupt + "T2COMINT", // 14: Timer 2 Compare and Match Interrupt + "T2OVFINT", // 15: Timer 2 Overflow Interrupt + "T1INT", // 16: Timer 1 Interrupt + "SPISTC", // 17: SPI Serial Transfer Complete + "TMRXBINT", // 18: Timer Modulator Receive Buffer Interrupt + "TMTXBINT", // 19: Timer Modulator Transmit Buffer Interrupt + "TMTXCINT", // 20: Timer Modulator Transmit Complete Interrupt + "AESINT", // 21: AES Crypto Unit Interrupt + "LFRSSINT", // 22: LF Receiver RSSI Interrupt + "LFSDINT", // 23: LF Receiver Signal Detect Interrupt + "LFMDINT", // 24: LF Receiver Manchester Decoder Error Interrupt + "EXCMINT", // 25: External Input Clock Monitoring Interrupt + "EXXMINT", // 26: External XTAL Oscillator Break Down Interrupt + "RTCINT", // 27: Real Time Clock Interrupt + "EEREADY", // 28: EEPROM Ready + "SPMREADY", // 29: Store Program Memory Ready +}; + +const char * const vtab_ata5791[vts_ata5791] = { // ATA5791, ATA5790N + "RESET", // 0: Reset (various reasons) + "TPINT", // 1: Transponder Mode Interrupt + "INT0", // 2: External Interrupt 0 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "VMINT", // 5: Voltage Monitoring Interrupt + "T0INT", // 6: Timer 0 Interrupt + "LFID0INT", // 7: LF Receiver Identifier 0 Interrupt + "LFID1INT", // 8: LF Receiver Identifier 1 Interrupt + "LFFEINT", // 9: LF Receiver Frame End Interrupt + "LFDBINT", // 10: LF Receiver Data Buffer Full Interrupt + "T3CAPINT", // 11: Timer 3 Capture Event Interrupt + "T3COMINT", // 12: Timer 3 Compare and Match Interrupt + "T3OVFINT", // 13: Timer 3 Overflow Interrupt + "T3COM2INT", // 14: Timer 3 Compare and Match 2 Interrupt + "T2COMINT", // 15: Timer 2 Compare and Match Interrupt + "T2OVFINT", // 16: Timer 2 Overflow Interrupt + "T1INT", // 17: Timer 1 Interrupt + "SPISTC", // 18: SPI Serial Transfer Complete + "TMRXBINT", // 19: Timer Modulator Receive Buffer Interrupt + "TMTXBINT", // 20: Timer Modulator Transmit Buffer Interrupt + "TMTXCINT", // 21: Timer Modulator Transmit Complete Interrupt + "AESINT", // 22: AES Crypto Unit Interrupt + "LFRSSINT", // 23: LF Receiver RSSI Interrupt + "LFSDINT", // 24: LF Receiver Signal Detect Interrupt + "LFMDINT", // 25: LF Receiver Manchester Decoder Error Interrupt + "EXCMINT", // 26: External Input Clock Monitoring Interrupt + "EXXMINT", // 27: External XTAL Oscillator Break Down Interrupt + "RTCINT", // 28: Real Time Clock Interrupt + "EEREADY", // 29: EEPROM Ready + "SPMREADY", // 30: Store Program Memory Ready +}; + +const char * const vtab_ata5795[vts_ata5795] = { // ATA5795 + "RESET", // 0: Reset (various reasons) + "TPINT", // 1: Transponder Mode Interrupt + "INT0", // 2: External Interrupt 0 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "VMINT", // 5: Voltage Monitoring Interrupt + "T0INT", // 6: Timer 0 Interrupt + "T3CAPINT", // 7: Timer 3 Capture Event Interrupt + "T3COMINT", // 8: Timer 3 Compare and Match Interrupt + "T3OVFINT", // 9: Timer 3 Overflow Interrupt + "T2COMINT", // 10: Timer 2 Compare and Match Interrupt + "T2OVFINT", // 11: Timer 2 Overflow Interrupt + "T1INT", // 12: Timer 1 Interrupt + "SPISTC", // 13: SPI Serial Transfer Complete + "TMRXBINT", // 14: Timer Modulator Receive Buffer Interrupt + "TMTXBINT", // 15: Timer Modulator Transmit Buffer Interrupt + "TMTXCINT", // 16: Timer Modulator Transmit Complete Interrupt + "AESINT", // 17: AES Crypto Unit Interrupt + "EXCMINT", // 18: External Input Clock Monitoring Interrupt + "EXXMINT", // 19: External XTAL Oscillator Break Down Interrupt + "RTCINT", // 20: Real Time Clock Interrupt + "EEREADY", // 21: EEPROM Ready + "SPMREADY", // 22: Store Program Memory Ready +}; + +const char * const vtab_ata5835[vts_ata5835] = { // ATA5835, ATA5787 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCI0", // 3: Pin Change Interrupt Request 0 + "PCI1", // 4: Pin Change Interrupt Request 1 + "VMON", // 5: Voltage Monitoring + "AVCCR", // 6: AVCC Reset + "AVCCL", // 7: AVCC Low + "T0INT", // 8: Timer 0 Interrupt + "T1COMP", // 9: Timer 1 Compare and Match + "T1OVF", // 10: Timer 1 Overflow + "T2COMP", // 11: Timer 2 Compare and Match + "T2OVF", // 12: Timer 2 Overflow + "T3CAP", // 13: Timer 3 Capture Event + "T3COMP", // 14: Timer 3 Compare and Match + "T3OVF", // 15: Timer 3 Overflow + "T4CAP", // 16: Timer 4 Capture Event + "T4COMP", // 17: Timer 4 Compare and Match + "T4OVF", // 18: Timer 4 Overflow + "T5COMP", // 19: Timer 5 Compare and Match + "T5OVF", // 20: Timer 5 Overflow + "SPI", // 21: SPI Serial Peripheral Interface + "SRX_FIFO", // 22: SPI Receive Buffer + "STX_FIFO", // 23: SPI Transmit Buffer + "LINTC", // 24: LIN Transfer Complete + "LINERR", // 25: LIN Error + "SSM", // 26: Sequencer State Machine + "DFFLR", // 27: Data FIFO Fill Level Reached + "DFOUE", // 28: Data FIFO Overflow or Underflow Error + "SFFLR", // 29: RSSI/Preamble FIFO Fill Level Reached + "SFOUE", // 30: RSSI/Preamble FIFO Overflow or Underflow Error + "TMTCF", // 31: Transmit Modulator Telegram Finished + "UHF_WCOA", // 32: UHF Receiver Wake Up OK on Receive Path A + "UHF_WCOB", // 33: UHF Receiver Wake Up OK on Receive Path B + "UHF_SOTA", // 34: UHF Receiver Start of Telegram OK on Receive Path A + "UHF_SOTB", // 35: UHF Receiver Start of Telegram OK on Receive Path B + "UHF_EOTA", // 36: UHF Receiver End of Telegram on Receive Path A + "UHF_EOTB", // 37: UHF Receiver End of Telegram on Receive Path B + "UHF_NBITA", // 38: UHF Receiver New Bit on Receive Path A + "UHF_NBITB", // 39: UHF Receiver New Bit on Receive Path B + "EXCM", // 40: External Input Clock Break Down + "ERDY", // 41: EEPROM Ready + "SPMR", // 42: Store Program Memory Ready + "IDFULL", // 43: IDSCAN Full +}; + +const char * const vtab_ata6289[vts_ata6289] = { // ATA6289, ATA6286, ATA6285 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "INTVM", // 6: Voltage Monitor Interrupt + "SENINT", // 7: Sensor Interface Interrupt + "INTT0", // 8: Timer 0 Interval Interrupt + "LFWP", // 9: LF-Receiver Wake-up + "T3CAP", // 10: Timer 3 Capture Event + "T3COMA", // 11: Timer 3 Compare Match A + "T3COMB", // 12: Timer 3 Compare Match B + "T3OVF", // 13: Timer 3 Overflow + "T2CAP", // 14: Timer 2 Capture Event + "T2COM", // 15: Timer 2 Compare Match + "T2OVF", // 16: Timer 2 Overflow + "SPISTC", // 17: SPI Serial Transfer Complete + "LFRXB", // 18: LF Receive Buffer + "INTT1", // 19: Timer 1 Interval Interrupt + "T2RXB", // 20: Timer 2 SSI Receive Buffer + "T2TXB", // 21: Timer 2 SSI Transmit Buffer + "T2TXC", // 22: Timer 2 SSI Transmit Complete + "LFREOB", // 23: LF-Receiver End of Burst + "EXCM", // 24: External Input Clock Break Down + "EEREADY", // 25: EEPROM Ready + "SPM_RDY", // 26: Store Program Memory Ready +}; + +const char * const vtab_ata8515[vts_ata8515] = { // ATA8515, ATA8510, ATA8215, ATA8210, ATA5833, ATA5832, ATA5831, ATA5783, ATA5782, ATA5781 + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCI0", // 3: Pin Change Interrupt Request 0 + "PCI1", // 4: Pin Change Interrupt Request 1 + "VMON", // 5: Voltage Monitoring + "AVCCR", // 6: AVCC Reset + "AVCCL", // 7: AVCC Low + "T0INT", // 8: Timer 0 Interrupt + "T1COMP", // 9: Timer 1 Compare and Match + "T1OVF", // 10: Timer 1 Overflow + "T2COMP", // 11: Timer 2 Compare and Match + "T2OVF", // 12: Timer 2 Overflow + "T3CAP", // 13: Timer 3 Capture Event + "T3COMP", // 14: Timer 3 Compare and Match + "T3OVF", // 15: Timer 3 Overflow + "T4CAP", // 16: Timer 4 Capture Event + "T4COMP", // 17: Timer 4 Compare and Match + "T4OVF", // 18: Timer 4 Overflow + "T5COMP", // 19: Timer 5 Compare and Match + "T5OVF", // 20: Timer 5 Overflow + "SPI", // 21: SPI Serial Peripheral Interface + "SRX_FIFO", // 22: SPI Receive Buffer + "STX_FIFO", // 23: SPI Transmit Buffer + "SSM", // 24: Sequencer State Machine + "DFFLR", // 25: Data FIFO Fill Level Reached + "DFOUE", // 26: Data FIFO Overflow or Underflow Error + "SFFLR", // 27: RSSI/Preamble FIFO Fill Level Reached + "SFOUE", // 28: RSSI/Preamble FIFO Overflow or Underflow Error + "TMTCF", // 29: Transmit Modulator Telegram Finished + "UHF_WCOB", // 30: UHF Receiver Wake Up OK on Receive Path B + "UHF_WCOA", // 31: UHF Receiver Wake Up OK on Receive Path A + "UHF_SOTB", // 32: UHF Receiver Start of Telegram OK on Receive Path B + "UHF_SOTA", // 33: UHF Receiver Start of Telegram OK on Receive Path A + "UHF_EOTB", // 34: UHF Receiver End of Telegram on Receive Path B + "UHF_EOTA", // 35: UHF Receiver End of Telegram on Receive Path A + "UHF_NBITB", // 36: UHF Receiver New Bit on Receive Path B + "UHF_NBITA", // 37: UHF Receiver New Bit on Receive Path A + "EXCM", // 38: External Input Clock Break Down + "ERDY", // 39: EEPROM Ready + "SPMR", // 40: Store Program Memory Ready + "IDFULL", // 41: IDSCAN Full +}; + +const char * const vtab_atxmega32a4[vts_atxmega32a4] = { // ATxmega32A4, ATxmega16A4 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF", // 14: TC C0 Overflow + "TCC0_ERR", // 15: TC C0 Error + "TCC0_CCA", // 16: TC C0 Compare or Capture A + "TCC0_CCB", // 17: TC C0 Compare or Capture B + "TCC0_CCC", // 18: TC C0 Compare or Capture C + "TCC0_CCD", // 19: TC C0 Compare or Capture D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "HIRESE_OVF", // 53: High-resolution Extension Overflow + "HIRESE_ERR", // 54: High-resolution Extension Error + "HIRESE_CCA", // 55: High-resolution Extension Compare and Capture A + "HIRESE_CCB", // 56: High-resolution Extension Compare and Capture B + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete +}; + +const char * const vtab_atxmega32c4[vts_atxmega32c4] = { // ATxmega32C4, ATxmega16C4 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "UNUSED", // 60: not implemented on this device + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "UNUSED", // 91: not implemented on this device + "UNUSED", // 92: not implemented on this device + "UNUSED", // 93: not implemented on this device + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "UNUSED", // 104: not implemented on this device + "UNUSED", // 105: not implemented on this device + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "UNUSED", // 108: not implemented on this device + "UNUSED", // 109: not implemented on this device + "UNUSED", // 110: not implemented on this device + "UNUSED", // 111: not implemented on this device + "UNUSED", // 112: not implemented on this device + "UNUSED", // 113: not implemented on this device + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega32d4[vts_atxmega32d4] = { // ATxmega32D4, ATxmega16D4 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "UNUSED", // 60: not implemented on this device + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete +}; + +const char * const vtab_atxmega32e5[vts_atxmega32e5] = { // ATxmega32E5, ATxmega16E5, ATxmega8E5 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTR_INT", // 2: External Interrupt PORT R + "EDMA_CH0", // 3: External DMA Channel 0 + "EDMA_CH1", // 4: External DMA Channel 1 + "EDMA_CH2", // 5: External DMA Channel 2 + "EDMA_CH3", // 6: External DMA Channel 3 + "RTC_OVF", // 7: RTC Overflow + "RTC_COMP", // 8: RTC Compare + "PORTC_INT", // 9: External Interrupt PORT C + "TWIC_TWIS", // 10: 2-Wire Interface C Periphery + "TWIC_TWIM", // 11: 2-Wire Interface C Controller + "TCC4_OVF", // 12: TC C4 Overflow + "TCC4_ERR", // 13: TC C4 Error + "TCC4_CCA", // 14: TC C4 Compare or Capture A + "TCC4_CCB", // 15: TC C4 Compare or Capture B + "TCC4_CCC", // 16: TC C4 Compare or Capture C + "TCC4_CCD", // 17: TC C4 Compare or Capture D + "TCC5_OVF", // 18: TC C5 Overflow + "TCC5_ERR", // 19: TC C5 Error + "TCC5_CCA", // 20: TC C5 Compare or Capture A + "TCC5_CCB", // 21: TC C5 Compare or Capture B + "SPIC_INT", // 22: SPI C Interrupt + "USARTC0_RXC", // 23: USARTC 0 Reception Complete + "USARTC0_DRE", // 24: USARTC 0 Data Register Empty + "USARTC0_TXC", // 25: USARTC 0 Transmission Complete + "NVM_EE", // 26: NVM EEPROM + "NVM_SPM", // 27: NVM SPM + "XCL_UNF", // 28: XMEGA Custom Logic Underflow + "XCL_CC", // 29: XMEGA Custom Logic Compare or Capture + "PORTA_INT", // 30: External Interrupt PORT A + "ACA_AC0", // 31: ACA AC 0 Interrupt + "ACA_AC1", // 32: ACA AC 1 Interrupt + "ACA_ACW", // 33: ACA AC Window Mode + "ADCA_CH0", // 34: ADCA Interrupt 0 + "PORTD_INT", // 35: External Interrupt PORT D + "TCD5_OVF", // 36: TC D5 Overflow + "TCD5_ERR", // 37: TC D5 Error + "TCD5_CCA", // 38: TC D5 Compare or Capture A + "TCD5_CCB", // 39: TC D5 Compare or Capture B + "USARTD0_RXC", // 40: USARTD 0 Reception Complete + "USARTD0_DRE", // 41: USARTD 0 Data Register Empty + "USARTD0_TXC", // 42: USARTD 0 Transmission Complete +}; + +const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxmega64A1 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF", // 14: TC C0 Overflow + "TCC0_ERR", // 15: TC C0 Error + "TCC0_CCA", // 16: TC C0 Compare or Capture A + "TCC0_CCB", // 17: TC C0 Compare or Capture B + "TCC0_CCC", // 18: TC C0 Compare or Capture C + "TCC0_CCD", // 19: TC C0 Compare or Capture D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "SPIE_INT", // 57: SPI E Interrupt + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "USARTE1_RXC", // 61: USARTE 1 Reception Complete + "USARTE1_DRE", // 62: USARTE 1 Data Register Empty + "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "TWID_TWIS", // 75: 2-Wire Interface D Periphery + "TWID_TWIM", // 76: 2-Wire Interface D Controller + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "PORTQ_INT0", // 94: External Interrupt 0 PORT Q + "PORTQ_INT1", // 95: External Interrupt 1 PORT Q + "PORTH_INT0", // 96: External Interrupt 0 PORT H + "PORTH_INT1", // 97: External Interrupt 1 PORT H + "PORTJ_INT0", // 98: External Interrupt 0 PORT J + "PORTJ_INT1", // 99: External Interrupt 1 PORT J + "PORTK_INT0", // 100: External Interrupt 0 PORT K + "PORTK_INT1", // 101: External Interrupt 1 PORT K + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "TWIF_TWIS", // 106: 2-Wire Interface F Periphery + "TWIF_TWIM", // 107: 2-Wire Interface F Controller + "TCF0_OVF", // 108: TC F0 Overflow + "TCF0_ERR", // 109: TC F0 Error + "TCF0_CCA", // 110: TC F0 Compare or Capture A + "TCF0_CCB", // 111: TC F0 Compare or Capture B + "TCF0_CCC", // 112: TC F0 Compare or Capture C + "TCF0_CCD", // 113: TC F0 Compare or Capture D + "TCF1_OVF", // 114: TC F1 Overflow + "TCF1_ERR", // 115: TC F1 Error + "TCF1_CCA", // 116: TC F1 Compare or Capture A + "TCF1_CCB", // 117: TC F1 Compare or Capture B + "SPIF_INT", // 118: SPI F Interrupt + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "USARTF1_RXC", // 122: USARTF 1 Reception Complete + "USARTF1_DRE", // 123: USARTF 1 Data Register Empty + "USARTF1_TXC", // 124: USARTF 1 Transmission Complete +}; + +const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, ATxmega64A1U + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "SPIE_INT", // 57: SPI E Interrupt + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "USARTE1_RXC", // 61: USARTE 1 Reception Complete + "USARTE1_DRE", // 62: USARTE 1 Data Register Empty + "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "TWID_TWIS", // 75: 2-Wire Interface D Periphery + "TWID_TWIM", // 76: 2-Wire Interface D Controller + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "PORTQ_INT0", // 94: External Interrupt 0 PORT Q + "PORTQ_INT1", // 95: External Interrupt 1 PORT Q + "PORTH_INT0", // 96: External Interrupt 0 PORT H + "PORTH_INT1", // 97: External Interrupt 1 PORT H + "PORTJ_INT0", // 98: External Interrupt 0 PORT J + "PORTJ_INT1", // 99: External Interrupt 1 PORT J + "PORTK_INT0", // 100: External Interrupt 0 PORT K + "PORTK_INT1", // 101: External Interrupt 1 PORT K + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "TWIF_TWIS", // 106: 2-Wire Interface F Periphery + "TWIF_TWIM", // 107: 2-Wire Interface F Controller + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "TCF1_OVF", // 114: TC F1 Overflow + "TCF1_ERR", // 115: TC F1 Error + "TCF1_CCA", // 116: TC F1 Compare or Capture A + "TCF1_CCB", // 117: TC F1 Compare or Capture B + "SPIF_INT", // 118: SPI F Interrupt + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "USARTF1_RXC", // 122: USARTF 1 Reception Complete + "USARTF1_DRE", // 123: USARTF 1 Data Register Empty + "USARTF1_TXC", // 124: USARTF 1 Transmission Complete + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega128b1[vts_atxmega128b1] = { // ATxmega128B1, ATxmega64B1 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 32: USB Transaction Complete + "UNUSED", // 33: not implemented on this device + "UNUSED", // 34: not implemented on this device + "LCD_INT", // 35: LCD Interrupt + "AES_INT", // 36: AES Interrupt + "NVM_EE", // 37: NVM EEPROM + "NVM_SPM", // 38: NVM SPM + "PORTB_INT0", // 39: External Interrupt 0 PORT B + "PORTB_INT1", // 40: External Interrupt 1 PORT B + "ACB_AC0", // 41: ACB AC 0 Interrupt + "ACB_AC1", // 42: ACB AC 1 Interrupt + "ACB_ACW", // 43: ACB AC Window Mode + "ADCB_CH0", // 44: ADCB Interrupt 0 + "UNUSED", // 45: not implemented on this device + "UNUSED", // 46: not implemented on this device + "UNUSED", // 47: not implemented on this device + "PORTD_INT0", // 48: External Interrupt 0 PORT D + "PORTD_INT1", // 49: External Interrupt 1 PORT D + "PORTG_INT0", // 50: External Interrupt 0 PORT G + "PORTG_INT1", // 51: External Interrupt 1 PORT G + "PORTM_INT0", // 52: External Interrupt 0 PORT M + "PORTM_INT1", // 53: External Interrupt 1 PORT M + "PORTE_INT0", // 54: External Interrupt 0 PORT E + "PORTE_INT1", // 55: External Interrupt 1 PORT E + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "TCE0_OVF/TCE2_LUNF", // 58: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 59: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 60: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 61: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 62: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 63: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "UNUSED", // 64: not implemented on this device + "UNUSED", // 65: not implemented on this device + "UNUSED", // 66: not implemented on this device + "UNUSED", // 67: not implemented on this device + "UNUSED", // 68: not implemented on this device + "USARTE0_RXC", // 69: USARTE 0 Reception Complete + "USARTE0_DRE", // 70: USARTE 0 Data Register Empty + "USARTE0_TXC", // 71: USARTE 0 Transmission Complete + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "PORTA_INT0", // 75: External Interrupt 0 PORT A + "PORTA_INT1", // 76: External Interrupt 1 PORT A + "ACA_AC0", // 77: ACA AC 0 Interrupt + "ACA_AC1", // 78: ACA AC 1 Interrupt + "ACA_ACW", // 79: ACA AC Window Mode + "ADCA_CH0", // 80: ADCA Interrupt 0 +}; + +const char * const vtab_atxmega128b3[vts_atxmega128b3] = { // ATxmega128B3, ATxmega64B3 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 32: USB Transaction Complete + "UNUSED", // 33: not implemented on this device + "UNUSED", // 34: not implemented on this device + "LCD_INT", // 35: LCD Interrupt + "AES_INT", // 36: AES Interrupt + "NVM_EE", // 37: NVM EEPROM + "NVM_SPM", // 38: NVM SPM + "PORTB_INT0", // 39: External Interrupt 0 PORT B + "PORTB_INT1", // 40: External Interrupt 1 PORT B + "ACB_AC0", // 41: ACB AC 0 Interrupt + "ACB_AC1", // 42: ACB AC 1 Interrupt + "ACB_ACW", // 43: ACB AC Window Mode + "ADCB_CH0", // 44: ADCB Interrupt 0 + "UNUSED", // 45: not implemented on this device + "UNUSED", // 46: not implemented on this device + "UNUSED", // 47: not implemented on this device + "PORTD_INT0", // 48: External Interrupt 0 PORT D + "PORTD_INT1", // 49: External Interrupt 1 PORT D + "PORTG_INT0", // 50: External Interrupt 0 PORT G + "PORTG_INT1", // 51: External Interrupt 1 PORT G + "PORTM_INT0", // 52: External Interrupt 0 PORT M + "PORTM_INT1", // 53: External Interrupt 1 PORT M +}; + +const char * const vtab_atxmega128a4u[vts_atxmega128a4u] = { // ATxmega128A4U, ATxmega64A4U, ATxmega32A4U, ATxmega16A4U + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "UNUSED", // 104: not implemented on this device + "UNUSED", // 105: not implemented on this device + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "UNUSED", // 108: not implemented on this device + "UNUSED", // 109: not implemented on this device + "UNUSED", // 110: not implemented on this device + "UNUSED", // 111: not implemented on this device + "UNUSED", // 112: not implemented on this device + "UNUSED", // 113: not implemented on this device + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega128d4[vts_atxmega128d4] = { // ATxmega128D4, ATxmega64D4 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete +}; + +const char * const vtab_atxmega256a3[vts_atxmega256a3] = { // ATxmega256A3, ATxmega192A3, ATxmega128A3, ATxmega64A3 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF", // 14: TC C0 Overflow + "TCC0_ERR", // 15: TC C0 Error + "TCC0_CCA", // 16: TC C0 Compare or Capture A + "TCC0_CCB", // 17: TC C0 Compare or Capture B + "TCC0_CCC", // 18: TC C0 Compare or Capture C + "TCC0_CCD", // 19: TC C0 Compare or Capture D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "SPIE_INT", // 57: SPI E Interrupt + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "USARTE1_RXC", // 61: USARTE 1 Reception Complete + "USARTE1_DRE", // 62: USARTE 1 Data Register Empty + "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF", // 108: TC F0 Overflow + "TCF0_ERR", // 109: TC F0 Error + "TCF0_CCA", // 110: TC F0 Compare or Capture A + "TCF0_CCB", // 111: TC F0 Compare or Capture B + "TCF0_CCC", // 112: TC F0 Compare or Capture C + "TCF0_CCD", // 113: TC F0 Compare or Capture D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete +}; + +const char * const vtab_atxmega256a3b[vts_atxmega256a3b] = { // ATxmega256A3B + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC32_OVF", // 10: RTC32 Overflow + "RTC32_COMP", // 11: RTC32 Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF", // 14: TC C0 Overflow + "TCC0_ERR", // 15: TC C0 Error + "TCC0_CCA", // 16: TC C0 Compare or Capture A + "TCC0_CCB", // 17: TC C0 Compare or Capture B + "TCC0_CCC", // 18: TC C0 Compare or Capture C + "TCC0_CCD", // 19: TC C0 Compare or Capture D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF", // 108: TC F0 Overflow + "TCF0_ERR", // 109: TC F0 Error + "TCF0_CCA", // 110: TC F0 Compare or Capture A + "TCF0_CCB", // 111: TC F0 Compare or Capture B + "TCF0_CCC", // 112: TC F0 Compare or Capture C + "TCF0_CCD", // 113: TC F0 Compare or Capture D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete +}; + +const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { // ATxmega256A3BU + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC32_OVF", // 10: RTC32 Overflow + "RTC32_COMP", // 11: RTC32 Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { // ATxmega256A3U, ATxmega192A3U, ATxmega128A3U, ATxmega64A3U + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "SPIE_INT", // 57: SPI E Interrupt + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "USARTE1_RXC", // 61: USARTE 1 Reception Complete + "USARTE1_DRE", // 62: USARTE 1 Data Register Empty + "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega256c3[vts_atxmega256c3] = { // ATxmega256C3, ATxmega192C3, ATxmega128C3, ATxmega64C3, ATxmega32C3 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "UNUSED", // 91: not implemented on this device + "UNUSED", // 92: not implemented on this device + "UNUSED", // 93: not implemented on this device + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega384c3[vts_atxmega384c3] = { // ATxmega384C3 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "UNUSED", // 91: not implemented on this device + "UNUSED", // 92: not implemented on this device + "UNUSED", // 93: not implemented on this device + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +const char * const vtab_atxmega384d3[vts_atxmega384d3] = { // ATxmega384D3, ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3, ATxmega32D3 + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIS", // 12: 2-Wire Interface C Periphery + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIS", // 45: 2-Wire Interface E Periphery + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "UNUSED", // 91: not implemented on this device + "UNUSED", // 92: not implemented on this device + "UNUSED", // 93: not implemented on this device + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D +}; + +const char * const vtab_attiny402[vts_attiny402] = { // ATtiny402, ATtiny202 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "UNUSED", // 4: not implemented on this device + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "UNUSED", // 14: not implemented on this device + "UNUSED", // 15: not implemented on this device + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny404[vts_attiny404] = { // ATtiny404, ATtiny204 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "UNUSED", // 14: not implemented on this device + "UNUSED", // 15: not implemented on this device + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny406[vts_attiny406] = { // ATtiny406 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "UNUSED", // 14: not implemented on this device + "UNUSED", // 15: not implemented on this device + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny412[vts_attiny412] = { // ATtiny412, ATtiny212 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "UNUSED", // 4: not implemented on this device + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny814[vts_attiny814] = { // ATtiny814, ATtiny414, ATtiny214 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny817[vts_attiny817] = { // ATtiny817, ATtiny816, ATtiny417, ATtiny416auto, ATtiny416 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIS", // 19: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +const char * const vtab_attiny1607[vts_attiny1607] = { // ATtiny1607, ATtiny1606, ATtiny1604, ATtiny807, ATtiny806, ATtiny804 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "UNUSED", // 14: not implemented on this device + "UNUSED", // 15: not implemented on this device + "UNUSED", // 16: not implemented on this device + "AC0_AC", // 17: AC0 AC Interrupt + "UNUSED", // 18: not implemented on this device + "UNUSED", // 19: not implemented on this device + "ADC0_RESRDY", // 20: ADC 0 Result Ready + "ADC0_WCOMP", // 21: ADC 0 Window Comparator + "UNUSED", // 22: not implemented on this device + "UNUSED", // 23: not implemented on this device + "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller + "SPI0_INT", // 26: SPI 0 Interrupt + "USART0_RXC", // 27: USART 0 Receive Complete + "USART0_DRE", // 28: USART 0 Data Register Empty + "USART0_TXC", // 29: USART 0 Transmit Complete + "NVMCTRL_EE", // 30: NVM EEPROM +}; + +const char * const vtab_attiny1614[vts_attiny1614] = { // ATtiny1614 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TCD0_OVF", // 15: TC D0 Overflow + "TCD0_TRIG", // 16: TC D0 Trigger + "AC0_AC", // 17: AC0 AC Interrupt + "AC1_AC", // 18: AC1 AC Interrupt + "AC2_AC", // 19: AC2 AC Interrupt + "ADC0_RESRDY", // 20: ADC 0 Result Ready + "ADC0_WCOMP", // 21: ADC 0 Window Comparator + "ADC1_RESRDY", // 22: ADC 1 Result Ready + "ADC1_WCOMP", // 23: ADC 1 Window Comparator + "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller + "SPI0_INT", // 26: SPI 0 Interrupt + "USART0_RXC", // 27: USART 0 Receive Complete + "USART0_DRE", // 28: USART 0 Data Register Empty + "USART0_TXC", // 29: USART 0 Transmit Complete + "NVMCTRL_EE", // 30: NVM EEPROM +}; + +const char * const vtab_attiny3214[vts_attiny3214] = { // ATtiny3214 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF", // 8: TC A0 Low Underflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0", // 10: TC A0 Compare 0 + "TCA0_CMP1", // 11: TC A0 Compare 1 + "TCA0_CMP2", // 12: TC A0 Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TCD0_OVF", // 15: TC D0 Overflow + "TCD0_TRIG", // 16: TC D0 Trigger + "AC0_AC", // 17: AC0 AC Interrupt + "AC1_AC", // 18: AC1 AC Interrupt + "AC2_AC", // 19: AC2 AC Interrupt + "ADC0_RESRDY", // 20: ADC 0 Result Ready + "ADC0_WCOMP", // 21: ADC 0 Window Comparator + "ADC1_RESRDY", // 22: ADC 1 Result Ready + "ADC1_WCOMP", // 23: ADC 1 Window Comparator + "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller + "SPI0_INT", // 26: SPI 0 Interrupt + "USART0_RXC", // 27: USART 0 Receive Complete + "USART0_DRE", // 28: USART 0 Data Register Empty + "USART0_TXC", // 29: USART 0 Transmit Complete + "NVMCTRL_EE", // 30: NVM EEPROM +}; + +const char * const vtab_attiny3217[vts_attiny3217] = { // ATtiny3217, ATtiny3216, ATtiny1617, ATtiny1616 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TCD0_OVF", // 15: TC D0 Overflow + "TCD0_TRIG", // 16: TC D0 Trigger + "AC0_AC", // 17: AC0 AC Interrupt + "AC1_AC", // 18: AC1 AC Interrupt + "AC2_AC", // 19: AC2 AC Interrupt + "ADC0_RESRDY", // 20: ADC 0 Result Ready + "ADC0_WCOMP", // 21: ADC 0 Window Comparator + "ADC1_RESRDY", // 22: ADC 1 Result Ready + "ADC1_WCOMP", // 23: ADC 1 Window Comparator + "TWI0_TWIS", // 24: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller + "SPI0_INT", // 26: SPI 0 Interrupt + "USART0_RXC", // 27: USART 0 Receive Complete + "USART0_DRE", // 28: USART 0 Data Register Empty + "USART0_TXC", // 29: USART 0 Transmit Complete + "NVMCTRL_EE", // 30: NVM EEPROM +}; + +const char * const vtab_attiny3227[vts_attiny3227] = { // ATtiny3227, ATtiny3226, ATtiny3224, ATtiny1627, ATtiny1626, ATtiny1624, ATtiny827, ATtiny826, ATtiny824, ATtiny427, ATtiny426, ATtiny424 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "PORTB_PORT", // 7: Interrupt PORT B + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller + "SPI0_INT", // 16: SPI 0 Interrupt + "USART0_RXC", // 17: USART 0 Receive Complete + "USART0_DRE", // 18: USART 0 Data Register Empty + "USART0_TXC", // 19: USART 0 Transmit Complete + "AC0_AC", // 20: AC0 AC Interrupt + "ADC0_ERROR", // 21: ADC 0 Error + "ADC0_RESRDY", // 22: ADC 0 Result Ready + "ADC0_SAMPRDY", // 23: ADC 0 Sample Ready + "PORTC_PORT", // 24: Interrupt PORT C + "TCB1_INT", // 25: TC B1 Interrupt + "USART1_RXC", // 26: USART 1 Receive Complete + "USART1_DRE", // 27: USART 1 Data Register Empty + "USART1_TXC", // 28: USART 1 Transmit Complete + "NVMCTRL_EE", // 29: NVM EEPROM +}; + +const char * const vtab_atmega4808[vts_atmega4808] = { // ATmega4808, ATmega3208, ATmega1608, ATmega808 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller + "SPI0_INT", // 16: SPI 0 Interrupt + "USART0_RXC", // 17: USART 0 Receive Complete + "USART0_DRE", // 18: USART 0 Data Register Empty + "USART0_TXC", // 19: USART 0 Transmit Complete + "PORTD_PORT", // 20: Interrupt PORT D + "AC0_AC", // 21: AC0 AC Interrupt + "ADC0_RESRDY", // 22: ADC 0 Result Ready + "ADC0_WCOMP", // 23: ADC 0 Window Comparator + "PORTC_PORT", // 24: Interrupt PORT C + "TCB2_INT", // 25: TC B2 Interrupt + "USART1_RXC", // 26: USART 1 Receive Complete + "USART1_DRE", // 27: USART 1 Data Register Empty + "USART1_TXC", // 28: USART 1 Transmit Complete + "PORTF_PORT", // 29: Interrupt PORT F + "NVMCTRL_EE", // 30: NVM EEPROM + "USART2_RXC", // 31: USART 2 Receive Complete + "USART2_DRE", // 32: USART 2 Data Register Empty + "USART2_TXC", // 33: USART 2 Transmit Complete + "PORTB_PORT", // 34: Interrupt PORT B + "PORTE_PORT", // 35: Interrupt PORT E +}; + +const char * const vtab_atmega4809[vts_atmega4809] = { // ATmega4809, ATmega3209, ATmega1609, ATmega809 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TWI0_TWIS", // 14: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller + "SPI0_INT", // 16: SPI 0 Interrupt + "USART0_RXC", // 17: USART 0 Receive Complete + "USART0_DRE", // 18: USART 0 Data Register Empty + "USART0_TXC", // 19: USART 0 Transmit Complete + "PORTD_PORT", // 20: Interrupt PORT D + "AC0_AC", // 21: AC0 AC Interrupt + "ADC0_RESRDY", // 22: ADC 0 Result Ready + "ADC0_WCOMP", // 23: ADC 0 Window Comparator + "PORTC_PORT", // 24: Interrupt PORT C + "TCB2_INT", // 25: TC B2 Interrupt + "USART1_RXC", // 26: USART 1 Receive Complete + "USART1_DRE", // 27: USART 1 Data Register Empty + "USART1_TXC", // 28: USART 1 Transmit Complete + "PORTF_PORT", // 29: Interrupt PORT F + "NVMCTRL_EE", // 30: NVM EEPROM + "USART2_RXC", // 31: USART 2 Receive Complete + "USART2_DRE", // 32: USART 2 Data Register Empty + "USART2_TXC", // 33: USART 2 Transmit Complete + "PORTB_PORT", // 34: Interrupt PORT B + "PORTE_PORT", // 35: Interrupt PORT E + "TCB3_INT", // 36: TC B3 Interrupt + "USART3_RXC", // 37: USART 3 Receive Complete + "USART3_DRE", // 38: USART 3 Data Register Empty + "USART3_TXC", // 39: USART 3 Transmit Complete +}; + +const char * const vtab_avr64dd32[vts_avr64dd32] = { // AVR64DD32, AVR64DD28, AVR64DD20, AVR64DD14, AVR32DD32, AVR32DD28, AVR32DD20, AVR32DD14, AVR16DD32, AVR16DD28, AVR16DD20, AVR16DD14 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD3_ZCD", // 28: Zero Cross Detect 3 + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM +}; + +const char * const vtab_avr64ea32[vts_avr64ea32] = { // AVR64EA32, AVR64EA28 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "PORTA_PORT", // 7: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TWI0_TWIS", // 15: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller + "SPI0_INT", // 17: SPI 0 Interrupt + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "AC0_AC", // 22: AC0 AC Interrupt + "ADC0_ERROR", // 23: ADC 0 Error + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready + "AC1_AC", // 26: AC1 AC Interrupt + "PORTC_PORT", // 27: Interrupt PORT C + "TCB2_INT", // 28: TC B2 Interrupt + "USART1_RXC", // 29: USART 1 Receive Complete + "USART1_DRE", // 30: USART 1 Data Register Empty + "USART1_TXC", // 31: USART 1 Transmit Complete + "PORTF_PORT", // 32: Interrupt PORT F + "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready + "USART2_RXC", // 34: USART 2 Receive Complete + "USART2_DRE", // 35: USART 2 Data Register Empty + "USART2_TXC", // 36: USART 2 Transmit Complete +}; + +const char * const vtab_avr64ea48[vts_avr64ea48] = { // AVR64EA48 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "PORTA_PORT", // 7: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TWI0_TWIS", // 15: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller + "SPI0_INT", // 17: SPI 0 Interrupt + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "AC0_AC", // 22: AC0 AC Interrupt + "ADC0_ERROR", // 23: ADC 0 Error + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready + "AC1_AC", // 26: AC1 AC Interrupt + "PORTC_PORT", // 27: Interrupt PORT C + "TCB2_INT", // 28: TC B2 Interrupt + "USART1_RXC", // 29: USART 1 Receive Complete + "USART1_DRE", // 30: USART 1 Data Register Empty + "USART1_TXC", // 31: USART 1 Transmit Complete + "PORTF_PORT", // 32: Interrupt PORT F + "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready + "USART2_RXC", // 34: USART 2 Receive Complete + "USART2_DRE", // 35: USART 2 Data Register Empty + "USART2_TXC", // 36: USART 2 Transmit Complete + "TCB3_INT", // 37: TC B3 Interrupt + "TCA1_LUNF/TCA1_OVF", // 38: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 39: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 40: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 41: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 42: TC A1 Compare 2/TC A1 Low Compare 2 + "PORTE_PORT", // 43: Interrupt PORT E + "PORTB_PORT", // 44: Interrupt PORT B +}; + +const char * const vtab_avr128da28[vts_avr128da28] = { // AVR128DA28, AVR64DA28, AVR32DA28 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt +}; + +const char * const vtab_avr128db28[vts_avr128db28] = { // AVR128DB28, AVR64DB28, AVR32DB28 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt +}; + +const char * const vtab_avr128da32[vts_avr128da32] = { // AVR128DA32, AVR64DA32, AVR32DA32 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "UNUSED", // 41: not implemented on this device + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller +}; + +const char * const vtab_avr128db32[vts_avr128db32] = { // AVR128DB32, AVR64DB32, AVR32DB32 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller +}; + +const char * const vtab_avr128da48[vts_avr128da48] = { // AVR128DA48, AVR64DA48, AVR32DA48 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "TCB3_INT", // 41: TC B3 Interrupt + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "PORTB_PORT", // 44: Interrupt PORT B + "PORTE_PORT", // 45: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 47: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 51: Zero Cross Detect 1 + "USART3_RXC", // 52: USART 3 Receive Complete + "USART3_DRE", // 53: USART 3 Data Register Empty + "USART3_TXC", // 54: USART 3 Transmit Complete + "USART4_RXC", // 55: USART 4 Receive Complete + "USART4_DRE", // 56: USART 4 Data Register Empty + "USART4_TXC", // 57: USART 4 Transmit Complete +}; + +const char * const vtab_avr128db48[vts_avr128db48] = { // AVR128DB48, AVR64DB48, AVR32DB48 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "TCB3_INT", // 44: TC B3 Interrupt + "PORTB_PORT", // 45: Interrupt PORT B + "PORTE_PORT", // 46: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 48: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 52: Zero Cross Detect 1 + "USART3_RXC", // 53: USART 3 Receive Complete + "USART3_DRE", // 54: USART 3 Data Register Empty + "USART3_TXC", // 55: USART 3 Transmit Complete + "USART4_RXC", // 56: USART 4 Receive Complete + "USART4_DRE", // 57: USART 4 Data Register Empty + "USART4_TXC", // 58: USART 4 Transmit Complete + "UNUSED", // 59: not implemented on this device + "ZCD2_ZCD", // 60: Zero Cross Detect 2 +}; + +const char * const vtab_avr128da64[vts_avr128da64] = { // AVR128DA64, AVR64DA64 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIS", // 16: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "TCB3_INT", // 41: TC B3 Interrupt + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "PORTB_PORT", // 44: Interrupt PORT B + "PORTE_PORT", // 45: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 47: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 51: Zero Cross Detect 1 + "USART3_RXC", // 52: USART 3 Receive Complete + "USART3_DRE", // 53: USART 3 Data Register Empty + "USART3_TXC", // 54: USART 3 Transmit Complete + "USART4_RXC", // 55: USART 4 Receive Complete + "USART4_DRE", // 56: USART 4 Data Register Empty + "USART4_TXC", // 57: USART 4 Transmit Complete + "PORTG_PORT", // 58: Interrupt PORT G + "ZCD2_ZCD", // 59: Zero Cross Detect 2 + "TCB4_INT", // 60: TC B4 Interrupt + "USART5_RXC", // 61: USART 5 Receive Complete + "USART5_DRE", // 62: USART 5 Data Register Empty + "USART5_TXC", // 63: USART 5 Transmit Complete +}; + +const char * const vtab_avr128db64[vts_avr128db64] = { // AVR128DB64, AVR64DB64 + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIS", // 18: 2-Wire Interface 0 Periphery + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIS", // 42: 2-Wire Interface 1 Periphery + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "TCB3_INT", // 44: TC B3 Interrupt + "PORTB_PORT", // 45: Interrupt PORT B + "PORTE_PORT", // 46: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 48: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 52: Zero Cross Detect 1 + "USART3_RXC", // 53: USART 3 Receive Complete + "USART3_DRE", // 54: USART 3 Data Register Empty + "USART3_TXC", // 55: USART 3 Transmit Complete + "USART4_RXC", // 56: USART 4 Receive Complete + "USART4_DRE", // 57: USART 4 Data Register Empty + "USART4_TXC", // 58: USART 4 Transmit Complete + "PORTG_PORT", // 59: Interrupt PORT G + "ZCD2_ZCD", // 60: Zero Cross Detect 2 + "TCB4_INT", // 61: TC B4 Interrupt + "USART5_RXC", // 62: USART 5 Receive Complete + "USART5_DRE", // 63: USART 5 Data Register Empty + "USART5_TXC", // 64: USART 5 Transmit Complete +}; + diff --git a/src/avrintel.h b/src/avrintel.h new file mode 100644 index 00000000..69f4862c --- /dev/null +++ b/src/avrintel.h @@ -0,0 +1,1477 @@ +/* + * Do not edit: automatically generated by mkavrintel.pl + * + * avrintel.h + * + * Atmel AVR8L, AVR8, XMEGA and AVR8X family description of interrupts and more + * + * published under GNU General Public License, version 3 (GPL-3.0) + * meta-author Stefan Rueger + * + * v 1.1 + * 30.08.2022 + * + */ + +#ifndef AVRINTEL_H +#define AVRINTEL_H + +#include "libavrdude.h" + +typedef struct { // Value of -1 typically means unknown + const char *name; // Name of part + uint16_t mcuid; // ID of MCU in 0..2039 + uint8_t avrarch; // F_AVR8L, F_AVR8, F_XMEGA or F_AVR8X + uint8_t sigs[3]; // Signature bytes + int32_t flashoffset; // Flash offset + int32_t flashsize; // Flash size + int16_t pagesize; // Flash page size + int8_t nboots; // Number of supported boot sectors + int16_t bootsize; // Size of (smallest) boot sector + int32_t eepromoffset; // EEPROM offset + int32_t eepromsize; // EEPROM size + int32_t eeprompagesize; // EEPROM page size + int32_t sramstart; // SRAM offset + int32_t sramsize; // SRAM size + int8_t nfuses; // Number of fuse bytes + int8_t nlocks; // Number of lock bytes + uint8_t ninterrupts; // Number of vectors in interrupt vector table + const char * const *isrtable; // Interrupt vector table vector names +} uPcore_t; + +#define F_AVR8L 1 // TPI programming, ATtiny(4|5|9|10|20|40|102|104) +#define F_AVR8 2 // ISP programming with SPI, "classic" AVRs +#define F_XMEGA 4 // PDI programming, ATxmega family +#define F_AVR8X 8 // UPDI programming, newer 8-bit MCUs + +#define UB_N_MCU 2040 // mcuid is in 0..2039 + +// MCU id: running number in arbitrary order; once assigned never change for backward compatibility +#define id_attiny4 0u +#define id_attiny5 1u +#define id_attiny9 2u +#define id_attiny10 3u +#define id_attiny20 4u +#define id_attiny40 5u +#define id_attiny102 6u +#define id_attiny104 7u +#define id_attiny11 8u +#define id_attiny12 9u +#define id_attiny13 10u +#define id_attiny13a 11u +#define id_attiny15 12u +#define id_attiny22 13u +#define id_attiny24 14u +#define id_attiny24a 15u +#define id_attiny25 16u +#define id_attiny26 17u +#define id_attiny28 18u +#define id_attiny43u 19u +#define id_attiny44 20u +#define id_attiny44a 21u +#define id_attiny45 22u +#define id_attiny48 23u +#define id_attiny84 24u +#define id_attiny84a 25u +#define id_attiny85 26u +#define id_attiny87 27u +#define id_attiny88 28u +#define id_attiny167 29u +#define id_attiny261 30u +#define id_attiny261a 31u +#define id_attiny441 32u +#define id_attiny461 33u +#define id_attiny461a 34u +#define id_attiny828 35u +#define id_attiny828r 36u +#define id_attiny841 37u +#define id_attiny861 38u +#define id_attiny861a 39u +#define id_attiny1634 40u +#define id_attiny1634r 41u +#define id_attiny2313 42u +#define id_attiny2313a 43u +#define id_attiny4313 44u +#define id_atmega8 45u +#define id_atmega8a 46u +#define id_atmega8hva 47u +#define id_atmega8u2 48u +#define id_atmega16 49u +#define id_atmega16a 50u +#define id_atmega16hva 51u +#define id_atmega16hvb 52u +#define id_atmega16hvbrevb 53u +#define id_atmega16m1 54u +#define id_atmega16hva2 55u +#define id_atmega16u2 56u +#define id_atmega16u4 57u +#define id_atmega32 58u +#define id_atmega32a 59u +#define id_atmega32hvb 60u +#define id_atmega32hvbrevb 61u +#define id_atmega32c1 62u +#define id_atmega32m1 63u +#define id_atmega32u2 64u +#define id_atmega32u4 65u +#define id_atmega32u6 66u +#define id_atmega48 67u +#define id_atmega48a 68u +#define id_atmega48p 69u +#define id_atmega48pa 70u +#define id_atmega48pb 71u +#define id_atmega64 72u +#define id_atmega64a 73u +#define id_atmega64hve 74u +#define id_atmega64c1 75u +#define id_atmega64m1 76u +#define id_atmega64hve2 77u +#define id_atmega64rfr2 78u +#define id_atmega88 79u +#define id_atmega88a 80u +#define id_atmega88p 81u +#define id_atmega88pa 82u +#define id_atmega88pb 83u +#define id_atmega103 84u +#define id_atmega128 85u +#define id_atmega128a 86u +#define id_atmega128rfa1 87u +#define id_atmega128rfr2 88u +#define id_atmega161 89u +#define id_atmega162 90u +#define id_atmega163 91u +#define id_atmega164a 92u +#define id_atmega164p 93u +#define id_atmega164pa 94u +#define id_atmega165 95u +#define id_atmega165a 96u +#define id_atmega165p 97u +#define id_atmega165pa 98u +#define id_atmega168 99u +#define id_atmega168a 100u +#define id_atmega168p 101u +#define id_atmega168pa 102u +#define id_atmega168pb 103u +#define id_atmega169 104u +#define id_atmega169a 105u +#define id_atmega169p 106u +#define id_atmega169pa 107u +#define id_atmega256rfr2 108u +#define id_atmega323 109u +#define id_atmega324a 110u +#define id_atmega324p 111u +#define id_atmega324pa 112u +#define id_atmega324pb 113u +#define id_atmega325 114u +#define id_atmega325a 115u +#define id_atmega325p 116u +#define id_atmega325pa 117u +#define id_atmega328 118u +#define id_atmega328p 119u +#define id_atmega328pb 120u +#define id_atmega329 121u +#define id_atmega329a 122u +#define id_atmega329p 123u +#define id_atmega329pa 124u +#define id_atmega406 125u +#define id_atmega640 126u +#define id_atmega644 127u +#define id_atmega644a 128u +#define id_atmega644p 129u +#define id_atmega644pa 130u +#define id_atmega644rfr2 131u +#define id_atmega645 132u +#define id_atmega645a 133u +#define id_atmega645p 134u +#define id_atmega649 135u +#define id_atmega649a 136u +#define id_atmega649p 137u +#define id_atmega1280 138u +#define id_atmega1281 139u +#define id_atmega1284 140u +#define id_atmega1284p 141u +#define id_atmega1284rfr2 142u +#define id_atmega2560 143u +#define id_atmega2561 144u +#define id_atmega2564rfr2 145u +#define id_atmega3250 146u +#define id_atmega3250a 147u +#define id_atmega3250p 148u +#define id_atmega3250pa 149u +#define id_atmega3290 150u +#define id_atmega3290a 151u +#define id_atmega3290p 152u +#define id_atmega3290pa 153u +#define id_atmega6450 154u +#define id_atmega6450a 155u +#define id_atmega6450p 156u +#define id_atmega6490 157u +#define id_atmega6490a 158u +#define id_atmega6490p 159u +#define id_atmega8515 160u +#define id_atmega8535 161u +#define id_at43usb320 162u +#define id_at43usb355 163u +#define id_at76c711 164u +#define id_at86rf401 165u +#define id_at90pwm1 166u +#define id_at90pwm2 167u +#define id_at90pwm2b 168u +#define id_at90pwm3 169u +#define id_at90pwm3b 170u +#define id_at90can32 171u +#define id_at90can64 172u +#define id_at90pwm81 173u +#define id_at90usb82 174u +#define id_at90scr100 175u +#define id_at90can128 176u +#define id_at90pwm161 177u +#define id_at90usb162 178u +#define id_at90pwm216 179u +#define id_at90pwm316 180u +#define id_at90usb646 181u +#define id_at90usb647 182u +#define id_at90s1200 183u +#define id_at90usb1286 184u +#define id_at90usb1287 185u +#define id_at90s2313 186u +#define id_at90s2323 187u +#define id_at90s2333 188u +#define id_at90s2343 189u +#define id_at90s4414 190u +#define id_at90s4433 191u +#define id_at90s4434 192u +#define id_at90s8515 193u +#define id_at90c8534 194u +#define id_at90s8535 195u +#define id_at94k 196u +#define id_ata5272 197u +#define id_ata5505 198u +#define id_ata5700m322 199u +#define id_ata5702m322 200u +#define id_ata5781 201u +#define id_ata5782 202u +#define id_ata5783 203u +#define id_ata5787 204u +#define id_ata5790 205u +#define id_ata5790n 206u +#define id_ata5791 207u +#define id_ata5795 208u +#define id_ata5831 209u +#define id_ata5832 210u +#define id_ata5833 211u +#define id_ata5835 212u +#define id_ata6285 213u +#define id_ata6286 214u +#define id_ata6289 215u +#define id_ata6612c 216u +#define id_ata6613c 217u +#define id_ata6614q 218u +#define id_ata6616c 219u +#define id_ata6617c 220u +#define id_ata8210 221u +#define id_ata8215 222u +#define id_ata8510 223u +#define id_ata8515 224u +#define id_ata664251 225u +#define id_m3000 226u +#define id_lgt8f88p 227u +#define id_lgt8f168p 228u +#define id_lgt8f328p 229u +#define id_atxmega8e5 230u +#define id_atxmega16a4 231u +#define id_atxmega16a4u 232u +#define id_atxmega16c4 233u +#define id_atxmega16d4 234u +#define id_atxmega16e5 235u +#define id_atxmega32c3 236u +#define id_atxmega32d3 237u +#define id_atxmega32a4 238u +#define id_atxmega32a4u 239u +#define id_atxmega32c4 240u +#define id_atxmega32d4 241u +#define id_atxmega32e5 242u +#define id_atxmega64a1 243u +#define id_atxmega64a1u 244u +#define id_atxmega64b1 245u +#define id_atxmega64a3 246u +#define id_atxmega64a3u 247u +#define id_atxmega64b3 248u +#define id_atxmega64c3 249u +#define id_atxmega64d3 250u +#define id_atxmega64a4 251u +#define id_atxmega64a4u 252u +#define id_atxmega64d4 253u +#define id_atxmega128a1 254u +#define id_atxmega128a1revd 255u +#define id_atxmega128a1u 256u +#define id_atxmega128b1 257u +#define id_atxmega128a3 258u +#define id_atxmega128a3u 259u +#define id_atxmega128b3 260u +#define id_atxmega128c3 261u +#define id_atxmega128d3 262u +#define id_atxmega128a4 263u +#define id_atxmega128a4u 264u +#define id_atxmega128d4 265u +#define id_atxmega192a1 266u +#define id_atxmega192a3 267u +#define id_atxmega192a3u 268u +#define id_atxmega192c3 269u +#define id_atxmega192d3 270u +#define id_atxmega256a1 271u +#define id_atxmega256a3 272u +#define id_atxmega256a3b 273u +#define id_atxmega256a3bu 274u +#define id_atxmega256a3u 275u +#define id_atxmega256c3 276u +#define id_atxmega256d3 277u +#define id_atxmega384c3 278u +#define id_atxmega384d3 279u +#define id_attiny202 280u +#define id_attiny204 281u +#define id_attiny212 282u +#define id_attiny214 283u +#define id_attiny402 284u +#define id_attiny404 285u +#define id_attiny406 286u +#define id_attiny412 287u +#define id_attiny414 288u +#define id_attiny416 289u +#define id_attiny416auto 290u +#define id_attiny417 291u +#define id_attiny424 292u +#define id_attiny426 293u +#define id_attiny427 294u +#define id_attiny804 295u +#define id_attiny806 296u +#define id_attiny807 297u +#define id_attiny814 298u +#define id_attiny816 299u +#define id_attiny817 300u +#define id_attiny824 301u +#define id_attiny826 302u +#define id_attiny827 303u +#define id_attiny1604 304u +#define id_attiny1606 305u +#define id_attiny1607 306u +#define id_attiny1614 307u +#define id_attiny1616 308u +#define id_attiny1617 309u +#define id_attiny1624 310u +#define id_attiny1626 311u +#define id_attiny1627 312u +#define id_attiny3214 313u +#define id_attiny3216 314u +#define id_attiny3217 315u +#define id_attiny3224 316u +#define id_attiny3226 317u +#define id_attiny3227 318u +#define id_atmega808 319u +#define id_atmega809 320u +#define id_atmega1608 321u +#define id_atmega1609 322u +#define id_atmega3208 323u +#define id_atmega3209 324u +#define id_atmega4808 325u +#define id_atmega4809 326u +#define id_avr8ea28 327u +#define id_avr8ea32 328u +#define id_avr16dd14 329u +#define id_avr16dd20 330u +#define id_avr16dd28 331u +#define id_avr16ea28 332u +#define id_avr16dd32 333u +#define id_avr16ea32 334u +#define id_avr16ea48 335u +#define id_avr32dd14 336u +#define id_avr32dd20 337u +#define id_avr32da28 338u +#define id_avr32db28 339u +#define id_avr32dd28 340u +#define id_avr32ea28 341u +#define id_avr32da32 342u +#define id_avr32db32 343u +#define id_avr32dd32 344u +#define id_avr32ea32 345u +#define id_avr32da48 346u +#define id_avr32db48 347u +#define id_avr32ea48 348u +#define id_avr64dd14 349u +#define id_avr64dd20 350u +#define id_avr64da28 351u +#define id_avr64db28 352u +#define id_avr64dd28 353u +#define id_avr64ea28 354u +#define id_avr64da32 355u +#define id_avr64db32 356u +#define id_avr64dd32 357u +#define id_avr64ea32 358u +#define id_avr64da48 359u +#define id_avr64db48 360u +#define id_avr64ea48 361u +#define id_avr64da64 362u +#define id_avr64db64 363u +#define id_avr128da28 364u +#define id_avr128db28 365u +#define id_avr128da32 366u +#define id_avr128db32 367u +#define id_avr128da48 368u +#define id_avr128db48 369u +#define id_avr128da64 370u +#define id_avr128db64 371u + +// Interrupt vector table sizes (number of vectors) +#define vts_attiny4 10 +#define vts_attiny5 11 +#define vts_attiny9 10 +#define vts_attiny10 11 +#define vts_attiny20 17 +#define vts_attiny40 18 +#define vts_attiny102 16 +#define vts_attiny104 16 +#define vts_attiny11 5 +#define vts_attiny12 6 +#define vts_attiny13 10 +#define vts_attiny13a 10 +#define vts_attiny15 9 +#define vts_attiny22 3 +#define vts_attiny24 17 +#define vts_attiny24a 17 +#define vts_attiny25 15 +#define vts_attiny26 12 +#define vts_attiny28 6 +#define vts_attiny43u 16 +#define vts_attiny44 17 +#define vts_attiny44a 17 +#define vts_attiny45 15 +#define vts_attiny48 20 +#define vts_attiny84 17 +#define vts_attiny84a 17 +#define vts_attiny85 15 +#define vts_attiny87 20 +#define vts_attiny88 20 +#define vts_attiny167 20 +#define vts_attiny261 19 +#define vts_attiny261a 19 +#define vts_attiny441 30 +#define vts_attiny461 19 +#define vts_attiny461a 19 +#define vts_attiny828 26 +#define vts_attiny841 30 +#define vts_attiny861 19 +#define vts_attiny861a 19 +#define vts_attiny1634 28 +#define vts_attiny2313 19 +#define vts_attiny2313a 21 +#define vts_attiny4313 21 +#define vts_atmega8 19 +#define vts_atmega8a 19 +#define vts_atmega8hva 21 +#define vts_atmega8u2 29 +#define vts_atmega16 21 +#define vts_atmega16a 21 +#define vts_atmega16hva 21 +#define vts_atmega16hvb 29 +#define vts_atmega16hvbrevb 29 +#define vts_atmega16m1 31 +#define vts_atmega16hva2 22 +#define vts_atmega16u2 29 +#define vts_atmega16u4 43 +#define vts_atmega32 21 +#define vts_atmega32a 21 +#define vts_atmega32hvb 29 +#define vts_atmega32hvbrevb 29 +#define vts_atmega32c1 31 +#define vts_atmega32m1 31 +#define vts_atmega32u2 29 +#define vts_atmega32u4 43 +#define vts_atmega32u6 38 +#define vts_atmega48 26 +#define vts_atmega48a 26 +#define vts_atmega48p 26 +#define vts_atmega48pa 26 +#define vts_atmega48pb 27 +#define vts_atmega64 35 +#define vts_atmega64a 35 +#define vts_atmega64hve 25 +#define vts_atmega64c1 31 +#define vts_atmega64m1 31 +#define vts_atmega64hve2 25 +#define vts_atmega64rfr2 77 +#define vts_atmega88 26 +#define vts_atmega88a 26 +#define vts_atmega88p 26 +#define vts_atmega88pa 26 +#define vts_atmega88pb 27 +#define vts_atmega103 24 +#define vts_atmega128 35 +#define vts_atmega128a 35 +#define vts_atmega128rfa1 72 +#define vts_atmega128rfr2 77 +#define vts_atmega161 21 +#define vts_atmega162 28 +#define vts_atmega163 18 +#define vts_atmega164a 31 +#define vts_atmega164p 31 +#define vts_atmega164pa 31 +#define vts_atmega165 22 +#define vts_atmega165a 22 +#define vts_atmega165p 22 +#define vts_atmega165pa 22 +#define vts_atmega168 26 +#define vts_atmega168a 26 +#define vts_atmega168p 26 +#define vts_atmega168pa 26 +#define vts_atmega168pb 27 +#define vts_atmega169 23 +#define vts_atmega169a 23 +#define vts_atmega169p 23 +#define vts_atmega169pa 23 +#define vts_atmega256rfr2 77 +#define vts_atmega323 21 +#define vts_atmega324a 31 +#define vts_atmega324p 31 +#define vts_atmega324pa 31 +#define vts_atmega324pb 51 +#define vts_atmega325 22 +#define vts_atmega325a 22 +#define vts_atmega325p 22 +#define vts_atmega325pa 22 +#define vts_atmega328 26 +#define vts_atmega328p 26 +#define vts_atmega328pb 45 +#define vts_atmega329 23 +#define vts_atmega329a 23 +#define vts_atmega329p 23 +#define vts_atmega329pa 23 +#define vts_atmega406 23 +#define vts_atmega640 57 +#define vts_atmega644 28 +#define vts_atmega644a 31 +#define vts_atmega644p 31 +#define vts_atmega644pa 31 +#define vts_atmega644rfr2 77 +#define vts_atmega645 22 +#define vts_atmega645a 22 +#define vts_atmega645p 22 +#define vts_atmega649 23 +#define vts_atmega649a 23 +#define vts_atmega649p 23 +#define vts_atmega1280 57 +#define vts_atmega1281 57 +#define vts_atmega1284 35 +#define vts_atmega1284p 35 +#define vts_atmega1284rfr2 77 +#define vts_atmega2560 57 +#define vts_atmega2561 57 +#define vts_atmega2564rfr2 77 +#define vts_atmega3250 25 +#define vts_atmega3250a 25 +#define vts_atmega3250p 25 +#define vts_atmega3250pa 25 +#define vts_atmega3290 25 +#define vts_atmega3290a 25 +#define vts_atmega3290p 25 +#define vts_atmega3290pa 25 +#define vts_atmega6450 25 +#define vts_atmega6450a 25 +#define vts_atmega6450p 25 +#define vts_atmega6490 25 +#define vts_atmega6490a 25 +#define vts_atmega6490p 25 +#define vts_atmega8515 17 +#define vts_atmega8535 21 +#define vts_at86rf401 3 +#define vts_at90pwm1 32 +#define vts_at90pwm2 32 +#define vts_at90pwm2b 32 +#define vts_at90pwm3 32 +#define vts_at90pwm3b 32 +#define vts_at90can32 37 +#define vts_at90can64 37 +#define vts_at90pwm81 20 +#define vts_at90usb82 29 +#define vts_at90scr100 38 +#define vts_at90can128 37 +#define vts_at90pwm161 20 +#define vts_at90usb162 29 +#define vts_at90pwm216 32 +#define vts_at90pwm316 32 +#define vts_at90usb646 38 +#define vts_at90usb647 38 +#define vts_at90s1200 4 +#define vts_at90usb1286 38 +#define vts_at90usb1287 38 +#define vts_at90s2313 11 +#define vts_at90s2323 3 +#define vts_at90s2333 14 +#define vts_at90s2343 3 +#define vts_at90s4414 13 +#define vts_at90s4433 14 +#define vts_at90s4434 17 +#define vts_at90s8515 13 +#define vts_at90s8535 17 +#define vts_ata5272 37 +#define vts_ata5505 20 +#define vts_ata5700m322 51 +#define vts_ata5702m322 51 +#define vts_ata5781 42 +#define vts_ata5782 42 +#define vts_ata5783 42 +#define vts_ata5787 44 +#define vts_ata5790 30 +#define vts_ata5790n 31 +#define vts_ata5791 31 +#define vts_ata5795 23 +#define vts_ata5831 42 +#define vts_ata5832 42 +#define vts_ata5833 42 +#define vts_ata5835 44 +#define vts_ata6285 27 +#define vts_ata6286 27 +#define vts_ata6289 27 +#define vts_ata6612c 26 +#define vts_ata6613c 26 +#define vts_ata6614q 26 +#define vts_ata6616c 20 +#define vts_ata6617c 20 +#define vts_ata8210 42 +#define vts_ata8215 42 +#define vts_ata8510 42 +#define vts_ata8515 42 +#define vts_ata664251 20 +#define vts_atxmega8e5 43 +#define vts_atxmega16a4 94 +#define vts_atxmega16a4u 127 +#define vts_atxmega16c4 127 +#define vts_atxmega16d4 91 +#define vts_atxmega16e5 43 +#define vts_atxmega32c3 127 +#define vts_atxmega32d3 114 +#define vts_atxmega32a4 94 +#define vts_atxmega32a4u 127 +#define vts_atxmega32c4 127 +#define vts_atxmega32d4 91 +#define vts_atxmega32e5 43 +#define vts_atxmega64a1 125 +#define vts_atxmega64a1u 127 +#define vts_atxmega64b1 81 +#define vts_atxmega64a3 122 +#define vts_atxmega64a3u 127 +#define vts_atxmega64b3 54 +#define vts_atxmega64c3 127 +#define vts_atxmega64d3 114 +#define vts_atxmega64a4u 127 +#define vts_atxmega64d4 91 +#define vts_atxmega128a1 125 +#define vts_atxmega128a1u 127 +#define vts_atxmega128b1 81 +#define vts_atxmega128a3 122 +#define vts_atxmega128a3u 127 +#define vts_atxmega128b3 54 +#define vts_atxmega128c3 127 +#define vts_atxmega128d3 114 +#define vts_atxmega128a4u 127 +#define vts_atxmega128d4 91 +#define vts_atxmega192a3 122 +#define vts_atxmega192a3u 127 +#define vts_atxmega192c3 127 +#define vts_atxmega192d3 114 +#define vts_atxmega256a3 122 +#define vts_atxmega256a3b 122 +#define vts_atxmega256a3bu 127 +#define vts_atxmega256a3u 127 +#define vts_atxmega256c3 127 +#define vts_atxmega256d3 114 +#define vts_atxmega384c3 127 +#define vts_atxmega384d3 114 +#define vts_attiny202 26 +#define vts_attiny204 26 +#define vts_attiny212 26 +#define vts_attiny214 26 +#define vts_attiny402 26 +#define vts_attiny404 26 +#define vts_attiny406 26 +#define vts_attiny412 26 +#define vts_attiny414 26 +#define vts_attiny416 26 +#define vts_attiny416auto 26 +#define vts_attiny417 26 +#define vts_attiny424 30 +#define vts_attiny426 30 +#define vts_attiny427 30 +#define vts_attiny804 31 +#define vts_attiny806 31 +#define vts_attiny807 31 +#define vts_attiny814 26 +#define vts_attiny816 26 +#define vts_attiny817 26 +#define vts_attiny824 30 +#define vts_attiny826 30 +#define vts_attiny827 30 +#define vts_attiny1604 31 +#define vts_attiny1606 31 +#define vts_attiny1607 31 +#define vts_attiny1614 31 +#define vts_attiny1616 31 +#define vts_attiny1617 31 +#define vts_attiny1624 30 +#define vts_attiny1626 30 +#define vts_attiny1627 30 +#define vts_attiny3214 31 +#define vts_attiny3216 31 +#define vts_attiny3217 31 +#define vts_attiny3224 30 +#define vts_attiny3226 30 +#define vts_attiny3227 30 +#define vts_atmega808 36 +#define vts_atmega809 40 +#define vts_atmega1608 36 +#define vts_atmega1609 40 +#define vts_atmega3208 36 +#define vts_atmega3209 40 +#define vts_atmega4808 36 +#define vts_atmega4809 40 +#define vts_avr16dd14 36 +#define vts_avr16dd20 36 +#define vts_avr16dd28 36 +#define vts_avr16dd32 36 +#define vts_avr32dd14 36 +#define vts_avr32dd20 36 +#define vts_avr32da28 41 +#define vts_avr32db28 42 +#define vts_avr32dd28 36 +#define vts_avr32da32 44 +#define vts_avr32db32 44 +#define vts_avr32dd32 36 +#define vts_avr32da48 58 +#define vts_avr32db48 61 +#define vts_avr64dd14 36 +#define vts_avr64dd20 36 +#define vts_avr64da28 41 +#define vts_avr64db28 42 +#define vts_avr64dd28 36 +#define vts_avr64ea28 37 +#define vts_avr64da32 44 +#define vts_avr64db32 44 +#define vts_avr64dd32 36 +#define vts_avr64ea32 37 +#define vts_avr64da48 58 +#define vts_avr64db48 61 +#define vts_avr64ea48 45 +#define vts_avr64da64 64 +#define vts_avr64db64 65 +#define vts_avr128da28 41 +#define vts_avr128db28 42 +#define vts_avr128da32 44 +#define vts_avr128db32 44 +#define vts_avr128da48 58 +#define vts_avr128db48 61 +#define vts_avr128da64 64 +#define vts_avr128db64 65 + +// Suggested vector bootloader interrupt number (first unused vector or, failing that, slot just above vector table) +#define vbu_attiny4 10 +#define vbu_attiny5 11 +#define vbu_attiny9 10 +#define vbu_attiny10 11 +#define vbu_attiny20 17 +#define vbu_attiny40 18 +#define vbu_attiny102 16 +#define vbu_attiny104 16 +#define vbu_attiny11 5 +#define vbu_attiny12 6 +#define vbu_attiny13 10 +#define vbu_attiny13a 10 +#define vbu_attiny15 9 +#define vbu_attiny22 3 +#define vbu_attiny24 17 +#define vbu_attiny24a 17 +#define vbu_attiny25 15 +#define vbu_attiny26 12 +#define vbu_attiny28 6 +#define vbu_attiny43u 16 +#define vbu_attiny44 17 +#define vbu_attiny44a 17 +#define vbu_attiny45 15 +#define vbu_attiny48 20 +#define vbu_attiny84 17 +#define vbu_attiny84a 17 +#define vbu_attiny85 15 +#define vbu_attiny87 20 +#define vbu_attiny88 20 +#define vbu_attiny167 20 +#define vbu_attiny261 19 +#define vbu_attiny261a 19 +#define vbu_attiny441 30 +#define vbu_attiny461 19 +#define vbu_attiny461a 19 +#define vbu_attiny828 26 +#define vbu_attiny841 30 +#define vbu_attiny861 19 +#define vbu_attiny861a 19 +#define vbu_attiny1634 28 +#define vbu_attiny2313 19 +#define vbu_attiny2313a 21 +#define vbu_attiny4313 21 +#define vbu_atmega8 19 +#define vbu_atmega8a 19 +#define vbu_atmega8hva 21 +#define vbu_atmega8u2 29 +#define vbu_atmega16 21 +#define vbu_atmega16a 21 +#define vbu_atmega16hva 21 +#define vbu_atmega16hvb 29 +#define vbu_atmega16hvbrevb 29 +#define vbu_atmega16m1 31 +#define vbu_atmega16hva2 22 +#define vbu_atmega16u2 29 +#define vbu_atmega16u4 43 +#define vbu_atmega32 21 +#define vbu_atmega32a 21 +#define vbu_atmega32hvb 29 +#define vbu_atmega32hvbrevb 29 +#define vbu_atmega32c1 31 +#define vbu_atmega32m1 31 +#define vbu_atmega32u2 29 +#define vbu_atmega32u4 43 +#define vbu_atmega32u6 38 +#define vbu_atmega48 26 +#define vbu_atmega48a 26 +#define vbu_atmega48p 26 +#define vbu_atmega48pa 26 +#define vbu_atmega48pb 27 +#define vbu_atmega64 35 +#define vbu_atmega64a 35 +#define vbu_atmega64hve 25 +#define vbu_atmega64c1 31 +#define vbu_atmega64m1 31 +#define vbu_atmega64hve2 25 +#define vbu_atmega64rfr2 77 +#define vbu_atmega88 26 +#define vbu_atmega88a 26 +#define vbu_atmega88p 26 +#define vbu_atmega88pa 26 +#define vbu_atmega88pb 27 +#define vbu_atmega103 24 +#define vbu_atmega128 35 +#define vbu_atmega128a 35 +#define vbu_atmega128rfa1 72 +#define vbu_atmega128rfr2 77 +#define vbu_atmega161 21 +#define vbu_atmega162 28 +#define vbu_atmega163 18 +#define vbu_atmega164a 31 +#define vbu_atmega164p 31 +#define vbu_atmega164pa 31 +#define vbu_atmega165 22 +#define vbu_atmega165a 22 +#define vbu_atmega165p 22 +#define vbu_atmega165pa 22 +#define vbu_atmega168 26 +#define vbu_atmega168a 26 +#define vbu_atmega168p 26 +#define vbu_atmega168pa 26 +#define vbu_atmega168pb 27 +#define vbu_atmega169 23 +#define vbu_atmega169a 23 +#define vbu_atmega169p 23 +#define vbu_atmega169pa 23 +#define vbu_atmega256rfr2 77 +#define vbu_atmega323 21 +#define vbu_atmega324a 31 +#define vbu_atmega324p 31 +#define vbu_atmega324pa 31 +#define vbu_atmega324pb 51 +#define vbu_atmega325 22 +#define vbu_atmega325a 22 +#define vbu_atmega325p 22 +#define vbu_atmega325pa 22 +#define vbu_atmega328 26 +#define vbu_atmega328p 26 +#define vbu_atmega328pb 45 +#define vbu_atmega329 23 +#define vbu_atmega329a 23 +#define vbu_atmega329p 23 +#define vbu_atmega329pa 23 +#define vbu_atmega406 23 +#define vbu_atmega640 57 +#define vbu_atmega644 28 +#define vbu_atmega644a 31 +#define vbu_atmega644p 31 +#define vbu_atmega644pa 31 +#define vbu_atmega644rfr2 77 +#define vbu_atmega645 22 +#define vbu_atmega645a 22 +#define vbu_atmega645p 22 +#define vbu_atmega649 23 +#define vbu_atmega649a 23 +#define vbu_atmega649p 23 +#define vbu_atmega1280 57 +#define vbu_atmega1281 57 +#define vbu_atmega1284 35 +#define vbu_atmega1284p 35 +#define vbu_atmega1284rfr2 77 +#define vbu_atmega2560 57 +#define vbu_atmega2561 57 +#define vbu_atmega2564rfr2 77 +#define vbu_atmega3250 25 +#define vbu_atmega3250a 25 +#define vbu_atmega3250p 25 +#define vbu_atmega3250pa 25 +#define vbu_atmega3290 25 +#define vbu_atmega3290a 25 +#define vbu_atmega3290p 25 +#define vbu_atmega3290pa 25 +#define vbu_atmega6450 25 +#define vbu_atmega6450a 25 +#define vbu_atmega6450p 25 +#define vbu_atmega6490 25 +#define vbu_atmega6490a 25 +#define vbu_atmega6490p 25 +#define vbu_atmega8515 17 +#define vbu_atmega8535 21 +#define vbu_at86rf401 3 +#define vbu_at90pwm1 32 +#define vbu_at90pwm2 14 +#define vbu_at90pwm2b 32 +#define vbu_at90pwm3 32 +#define vbu_at90pwm3b 32 +#define vbu_at90can32 37 +#define vbu_at90can64 37 +#define vbu_at90pwm81 20 +#define vbu_at90usb82 29 +#define vbu_at90scr100 38 +#define vbu_at90can128 37 +#define vbu_at90pwm161 20 +#define vbu_at90usb162 29 +#define vbu_at90pwm216 32 +#define vbu_at90pwm316 32 +#define vbu_at90usb646 38 +#define vbu_at90usb647 38 +#define vbu_at90s1200 4 +#define vbu_at90usb1286 38 +#define vbu_at90usb1287 38 +#define vbu_at90s2313 11 +#define vbu_at90s2323 3 +#define vbu_at90s2333 14 +#define vbu_at90s2343 3 +#define vbu_at90s4414 13 +#define vbu_at90s4433 14 +#define vbu_at90s4434 17 +#define vbu_at90s8515 13 +#define vbu_at90s8535 17 +#define vbu_ata5272 17 +#define vbu_ata5505 20 +#define vbu_ata5700m322 51 +#define vbu_ata5702m322 51 +#define vbu_ata5781 42 +#define vbu_ata5782 42 +#define vbu_ata5783 42 +#define vbu_ata5787 44 +#define vbu_ata5790 30 +#define vbu_ata5790n 31 +#define vbu_ata5791 31 +#define vbu_ata5795 23 +#define vbu_ata5831 42 +#define vbu_ata5832 42 +#define vbu_ata5833 42 +#define vbu_ata5835 44 +#define vbu_ata6285 27 +#define vbu_ata6286 27 +#define vbu_ata6289 27 +#define vbu_ata6612c 26 +#define vbu_ata6613c 26 +#define vbu_ata6614q 26 +#define vbu_ata6616c 20 +#define vbu_ata6617c 20 +#define vbu_ata8210 42 +#define vbu_ata8215 42 +#define vbu_ata8510 42 +#define vbu_ata8515 42 +#define vbu_ata664251 20 +#define vbu_atxmega8e5 43 +#define vbu_atxmega16a4 36 +#define vbu_atxmega16a4u 36 +#define vbu_atxmega16c4 6 +#define vbu_atxmega16d4 6 +#define vbu_atxmega16e5 43 +#define vbu_atxmega32c3 6 +#define vbu_atxmega32d3 6 +#define vbu_atxmega32a4 36 +#define vbu_atxmega32a4u 36 +#define vbu_atxmega32c4 6 +#define vbu_atxmega32d4 6 +#define vbu_atxmega32e5 43 +#define vbu_atxmega64a1 102 +#define vbu_atxmega64a1u 102 +#define vbu_atxmega64b1 8 +#define vbu_atxmega64a3 75 +#define vbu_atxmega64a3u 75 +#define vbu_atxmega64b3 8 +#define vbu_atxmega64c3 6 +#define vbu_atxmega64d3 6 +#define vbu_atxmega64a4u 36 +#define vbu_atxmega64d4 6 +#define vbu_atxmega128a1 102 +#define vbu_atxmega128a1u 102 +#define vbu_atxmega128b1 8 +#define vbu_atxmega128a3 75 +#define vbu_atxmega128a3u 75 +#define vbu_atxmega128b3 8 +#define vbu_atxmega128c3 6 +#define vbu_atxmega128d3 6 +#define vbu_atxmega128a4u 36 +#define vbu_atxmega128d4 6 +#define vbu_atxmega192a3 75 +#define vbu_atxmega192a3u 75 +#define vbu_atxmega192c3 6 +#define vbu_atxmega192d3 6 +#define vbu_atxmega256a3 75 +#define vbu_atxmega256a3b 57 +#define vbu_atxmega256a3bu 57 +#define vbu_atxmega256a3u 75 +#define vbu_atxmega256c3 6 +#define vbu_atxmega256d3 6 +#define vbu_atxmega384c3 8 +#define vbu_atxmega384d3 6 +#define vbu_attiny202 4 +#define vbu_attiny204 5 +#define vbu_attiny212 4 +#define vbu_attiny214 5 +#define vbu_attiny402 4 +#define vbu_attiny404 5 +#define vbu_attiny406 14 +#define vbu_attiny412 4 +#define vbu_attiny414 5 +#define vbu_attiny416 26 +#define vbu_attiny416auto 26 +#define vbu_attiny417 26 +#define vbu_attiny424 30 +#define vbu_attiny426 30 +#define vbu_attiny427 30 +#define vbu_attiny804 14 +#define vbu_attiny806 14 +#define vbu_attiny807 14 +#define vbu_attiny814 5 +#define vbu_attiny816 26 +#define vbu_attiny817 26 +#define vbu_attiny824 30 +#define vbu_attiny826 30 +#define vbu_attiny827 30 +#define vbu_attiny1604 14 +#define vbu_attiny1606 14 +#define vbu_attiny1607 14 +#define vbu_attiny1614 5 +#define vbu_attiny1616 31 +#define vbu_attiny1617 31 +#define vbu_attiny1624 30 +#define vbu_attiny1626 30 +#define vbu_attiny1627 30 +#define vbu_attiny3214 31 +#define vbu_attiny3216 31 +#define vbu_attiny3217 31 +#define vbu_attiny3224 30 +#define vbu_attiny3226 30 +#define vbu_attiny3227 30 +#define vbu_atmega808 36 +#define vbu_atmega809 40 +#define vbu_atmega1608 36 +#define vbu_atmega1609 40 +#define vbu_atmega3208 36 +#define vbu_atmega3209 40 +#define vbu_atmega4808 36 +#define vbu_atmega4809 40 +#define vbu_avr16dd14 36 +#define vbu_avr16dd20 36 +#define vbu_avr16dd28 36 +#define vbu_avr16dd32 36 +#define vbu_avr32dd14 36 +#define vbu_avr32dd20 36 +#define vbu_avr32da28 41 +#define vbu_avr32db28 42 +#define vbu_avr32dd28 36 +#define vbu_avr32da32 41 +#define vbu_avr32db32 44 +#define vbu_avr32dd32 36 +#define vbu_avr32da48 58 +#define vbu_avr32db48 59 +#define vbu_avr64dd14 36 +#define vbu_avr64dd20 36 +#define vbu_avr64da28 41 +#define vbu_avr64db28 42 +#define vbu_avr64dd28 36 +#define vbu_avr64ea28 37 +#define vbu_avr64da32 41 +#define vbu_avr64db32 44 +#define vbu_avr64dd32 36 +#define vbu_avr64ea32 37 +#define vbu_avr64da48 58 +#define vbu_avr64db48 59 +#define vbu_avr64ea48 45 +#define vbu_avr64da64 64 +#define vbu_avr64db64 65 +#define vbu_avr128da28 41 +#define vbu_avr128db28 42 +#define vbu_avr128da32 41 +#define vbu_avr128db32 44 +#define vbu_avr128da48 58 +#define vbu_avr128db48 59 +#define vbu_avr128da64 64 +#define vbu_avr128db64 65 + +// Aliases for parts with the same vector table +#define vtab_attiny4 vtab_attiny9 +#define vtab_attiny5 vtab_attiny10 +#define vtab_attiny102 vtab_attiny104 +#define vtab_attiny13 vtab_attiny13a +#define vtab_attiny24 vtab_attiny84a +#define vtab_attiny24a vtab_attiny84a +#define vtab_attiny25 vtab_attiny85 +#define vtab_attiny44 vtab_attiny84a +#define vtab_attiny44a vtab_attiny84a +#define vtab_attiny45 vtab_attiny85 +#define vtab_attiny48 vtab_attiny88 +#define vtab_attiny84 vtab_attiny84a +#define vtab_attiny87 vtab_attiny167 +#define vtab_attiny261 vtab_attiny861a +#define vtab_attiny261a vtab_attiny861a +#define vtab_attiny441 vtab_attiny841 +#define vtab_attiny461 vtab_attiny861a +#define vtab_attiny461a vtab_attiny861a +#define vtab_attiny861 vtab_attiny861a +#define vtab_attiny2313a vtab_attiny4313 +#define vtab_atmega8 vtab_atmega8a +#define vtab_atmega8hva vtab_atmega16hva +#define vtab_atmega8u2 vtab_atmega32u2 +#define vtab_atmega16 vtab_atmega16a +#define vtab_atmega16hvb vtab_atmega32hvbrevb +#define vtab_atmega16hvbrevb vtab_atmega32hvbrevb +#define vtab_atmega16m1 vtab_atmega64m1 +#define vtab_atmega16u2 vtab_atmega32u2 +#define vtab_atmega16u4 vtab_atmega32u4 +#define vtab_atmega32 vtab_atmega323 +#define vtab_atmega32a vtab_atmega323 +#define vtab_atmega32hvb vtab_atmega32hvbrevb +#define vtab_atmega32c1 vtab_atmega64m1 +#define vtab_atmega32m1 vtab_atmega64m1 +#define vtab_atmega48 vtab_atmega328p +#define vtab_atmega48a vtab_atmega328p +#define vtab_atmega48p vtab_atmega328p +#define vtab_atmega48pa vtab_atmega328p +#define vtab_atmega48pb vtab_atmega168pb +#define vtab_atmega64 vtab_atmega128a +#define vtab_atmega64a vtab_atmega128a +#define vtab_atmega64hve vtab_atmega64hve2 +#define vtab_atmega64c1 vtab_atmega64m1 +#define vtab_atmega64rfr2 vtab_atmega2564rfr2 +#define vtab_atmega88 vtab_atmega328p +#define vtab_atmega88a vtab_atmega328p +#define vtab_atmega88p vtab_atmega328p +#define vtab_atmega88pa vtab_atmega328p +#define vtab_atmega88pb vtab_atmega168pb +#define vtab_atmega128 vtab_atmega128a +#define vtab_atmega128rfr2 vtab_atmega2564rfr2 +#define vtab_atmega164a vtab_atmega644pa +#define vtab_atmega164p vtab_atmega644pa +#define vtab_atmega164pa vtab_atmega644pa +#define vtab_atmega165 vtab_atmega645p +#define vtab_atmega165a vtab_atmega645p +#define vtab_atmega165p vtab_atmega645p +#define vtab_atmega165pa vtab_atmega645p +#define vtab_atmega168 vtab_atmega328 +#define vtab_atmega168a vtab_atmega328p +#define vtab_atmega168p vtab_atmega328p +#define vtab_atmega168pa vtab_atmega328p +#define vtab_atmega169 vtab_atmega649p +#define vtab_atmega169a vtab_atmega649p +#define vtab_atmega169p vtab_atmega649p +#define vtab_atmega169pa vtab_atmega649p +#define vtab_atmega256rfr2 vtab_atmega2564rfr2 +#define vtab_atmega324a vtab_atmega644pa +#define vtab_atmega324p vtab_atmega644pa +#define vtab_atmega324pa vtab_atmega644pa +#define vtab_atmega325 vtab_atmega645p +#define vtab_atmega325a vtab_atmega645p +#define vtab_atmega325p vtab_atmega645p +#define vtab_atmega325pa vtab_atmega645p +#define vtab_atmega329 vtab_atmega649p +#define vtab_atmega329a vtab_atmega649p +#define vtab_atmega329p vtab_atmega649p +#define vtab_atmega329pa vtab_atmega649p +#define vtab_atmega640 vtab_atmega2561 +#define vtab_atmega644a vtab_atmega644pa +#define vtab_atmega644p vtab_atmega644pa +#define vtab_atmega644rfr2 vtab_atmega2564rfr2 +#define vtab_atmega645 vtab_atmega645p +#define vtab_atmega645a vtab_atmega645p +#define vtab_atmega649 vtab_atmega649p +#define vtab_atmega649a vtab_atmega649p +#define vtab_atmega1280 vtab_atmega2561 +#define vtab_atmega1281 vtab_atmega2561 +#define vtab_atmega1284 vtab_atmega1284p +#define vtab_atmega1284rfr2 vtab_atmega2564rfr2 +#define vtab_atmega2560 vtab_atmega2561 +#define vtab_atmega3250 vtab_atmega6450p +#define vtab_atmega3250a vtab_atmega6450p +#define vtab_atmega3250p vtab_atmega6450p +#define vtab_atmega3250pa vtab_atmega6450p +#define vtab_atmega3290 vtab_atmega6490p +#define vtab_atmega3290a vtab_atmega6490p +#define vtab_atmega3290p vtab_atmega6490p +#define vtab_atmega3290pa vtab_atmega6490p +#define vtab_atmega6450 vtab_atmega6450p +#define vtab_atmega6450a vtab_atmega6450p +#define vtab_atmega6490 vtab_atmega6490p +#define vtab_atmega6490a vtab_atmega6490p +#define vtab_at90pwm1 vtab_at90pwm316 +#define vtab_at90pwm2b vtab_at90pwm3b +#define vtab_at90pwm3 vtab_at90pwm3b +#define vtab_at90can32 vtab_at90can128 +#define vtab_at90can64 vtab_at90can128 +#define vtab_at90pwm81 vtab_at90pwm161 +#define vtab_at90usb82 vtab_atmega32u2 +#define vtab_at90usb162 vtab_atmega32u2 +#define vtab_at90pwm216 vtab_at90pwm316 +#define vtab_at90usb646 vtab_atmega32u6 +#define vtab_at90usb647 vtab_atmega32u6 +#define vtab_at90usb1286 vtab_atmega32u6 +#define vtab_at90usb1287 vtab_atmega32u6 +#define vtab_at90s2323 vtab_attiny22 +#define vtab_at90s2333 vtab_at90s4433 +#define vtab_at90s2343 vtab_attiny22 +#define vtab_at90s4414 vtab_at90s8515 +#define vtab_at90s4434 vtab_at90s8535 +#define vtab_ata5505 vtab_attiny167 +#define vtab_ata5700m322 vtab_ata5702m322 +#define vtab_ata5781 vtab_ata8515 +#define vtab_ata5782 vtab_ata8515 +#define vtab_ata5783 vtab_ata8515 +#define vtab_ata5787 vtab_ata5835 +#define vtab_ata5790n vtab_ata5791 +#define vtab_ata5831 vtab_ata8515 +#define vtab_ata5832 vtab_ata8515 +#define vtab_ata5833 vtab_ata8515 +#define vtab_ata6285 vtab_ata6289 +#define vtab_ata6286 vtab_ata6289 +#define vtab_ata6612c vtab_atmega328p +#define vtab_ata6613c vtab_atmega328p +#define vtab_ata6614q vtab_atmega328p +#define vtab_ata6616c vtab_attiny167 +#define vtab_ata6617c vtab_attiny167 +#define vtab_ata8210 vtab_ata8515 +#define vtab_ata8215 vtab_ata8515 +#define vtab_ata8510 vtab_ata8515 +#define vtab_ata664251 vtab_attiny167 +#define vtab_atxmega8e5 vtab_atxmega32e5 +#define vtab_atxmega16a4 vtab_atxmega32a4 +#define vtab_atxmega16a4u vtab_atxmega128a4u +#define vtab_atxmega16c4 vtab_atxmega32c4 +#define vtab_atxmega16d4 vtab_atxmega32d4 +#define vtab_atxmega16e5 vtab_atxmega32e5 +#define vtab_atxmega32c3 vtab_atxmega256c3 +#define vtab_atxmega32d3 vtab_atxmega384d3 +#define vtab_atxmega32a4u vtab_atxmega128a4u +#define vtab_atxmega64a1 vtab_atxmega128a1 +#define vtab_atxmega64a1u vtab_atxmega128a1u +#define vtab_atxmega64b1 vtab_atxmega128b1 +#define vtab_atxmega64a3 vtab_atxmega256a3 +#define vtab_atxmega64a3u vtab_atxmega256a3u +#define vtab_atxmega64b3 vtab_atxmega128b3 +#define vtab_atxmega64c3 vtab_atxmega256c3 +#define vtab_atxmega64d3 vtab_atxmega384d3 +#define vtab_atxmega64a4u vtab_atxmega128a4u +#define vtab_atxmega64d4 vtab_atxmega128d4 +#define vtab_atxmega128a3 vtab_atxmega256a3 +#define vtab_atxmega128a3u vtab_atxmega256a3u +#define vtab_atxmega128c3 vtab_atxmega256c3 +#define vtab_atxmega128d3 vtab_atxmega384d3 +#define vtab_atxmega192a3 vtab_atxmega256a3 +#define vtab_atxmega192a3u vtab_atxmega256a3u +#define vtab_atxmega192c3 vtab_atxmega256c3 +#define vtab_atxmega192d3 vtab_atxmega384d3 +#define vtab_atxmega256d3 vtab_atxmega384d3 +#define vtab_attiny202 vtab_attiny402 +#define vtab_attiny204 vtab_attiny404 +#define vtab_attiny212 vtab_attiny412 +#define vtab_attiny214 vtab_attiny814 +#define vtab_attiny414 vtab_attiny814 +#define vtab_attiny416 vtab_attiny817 +#define vtab_attiny416auto vtab_attiny817 +#define vtab_attiny417 vtab_attiny817 +#define vtab_attiny424 vtab_attiny3227 +#define vtab_attiny426 vtab_attiny3227 +#define vtab_attiny427 vtab_attiny3227 +#define vtab_attiny804 vtab_attiny1607 +#define vtab_attiny806 vtab_attiny1607 +#define vtab_attiny807 vtab_attiny1607 +#define vtab_attiny816 vtab_attiny817 +#define vtab_attiny824 vtab_attiny3227 +#define vtab_attiny826 vtab_attiny3227 +#define vtab_attiny827 vtab_attiny3227 +#define vtab_attiny1604 vtab_attiny1607 +#define vtab_attiny1606 vtab_attiny1607 +#define vtab_attiny1616 vtab_attiny3217 +#define vtab_attiny1617 vtab_attiny3217 +#define vtab_attiny1624 vtab_attiny3227 +#define vtab_attiny1626 vtab_attiny3227 +#define vtab_attiny1627 vtab_attiny3227 +#define vtab_attiny3216 vtab_attiny3217 +#define vtab_attiny3224 vtab_attiny3227 +#define vtab_attiny3226 vtab_attiny3227 +#define vtab_atmega808 vtab_atmega4808 +#define vtab_atmega809 vtab_atmega4809 +#define vtab_atmega1608 vtab_atmega4808 +#define vtab_atmega1609 vtab_atmega4809 +#define vtab_atmega3208 vtab_atmega4808 +#define vtab_atmega3209 vtab_atmega4809 +#define vtab_avr16dd14 vtab_avr64dd32 +#define vtab_avr16dd20 vtab_avr64dd32 +#define vtab_avr16dd28 vtab_avr64dd32 +#define vtab_avr16dd32 vtab_avr64dd32 +#define vtab_avr32dd14 vtab_avr64dd32 +#define vtab_avr32dd20 vtab_avr64dd32 +#define vtab_avr32da28 vtab_avr128da28 +#define vtab_avr32db28 vtab_avr128db28 +#define vtab_avr32dd28 vtab_avr64dd32 +#define vtab_avr32da32 vtab_avr128da32 +#define vtab_avr32db32 vtab_avr128db32 +#define vtab_avr32dd32 vtab_avr64dd32 +#define vtab_avr32da48 vtab_avr128da48 +#define vtab_avr32db48 vtab_avr128db48 +#define vtab_avr64dd14 vtab_avr64dd32 +#define vtab_avr64dd20 vtab_avr64dd32 +#define vtab_avr64da28 vtab_avr128da28 +#define vtab_avr64db28 vtab_avr128db28 +#define vtab_avr64dd28 vtab_avr64dd32 +#define vtab_avr64ea28 vtab_avr64ea32 +#define vtab_avr64da32 vtab_avr128da32 +#define vtab_avr64db32 vtab_avr128db32 +#define vtab_avr64da48 vtab_avr128da48 +#define vtab_avr64db48 vtab_avr128db48 +#define vtab_avr64da64 vtab_avr128da64 +#define vtab_avr64db64 vtab_avr128db64 + +// Interrupt vector table interrupt names +extern const char * const vtab_attiny9[10]; // ATtiny9, ATtiny4 +extern const char * const vtab_attiny10[11]; // ATtiny10, ATtiny5 +extern const char * const vtab_attiny20[17]; // ATtiny20 +extern const char * const vtab_attiny40[18]; // ATtiny40 +extern const char * const vtab_attiny104[16]; // ATtiny104, ATtiny102 +extern const char * const vtab_attiny11[5]; // ATtiny11 +extern const char * const vtab_attiny12[6]; // ATtiny12 +extern const char * const vtab_attiny13a[10]; // ATtiny13A, ATtiny13 +extern const char * const vtab_attiny15[9]; // ATtiny15 +extern const char * const vtab_attiny22[3]; // ATtiny22, AT90S2343, AT90S2323 +extern const char * const vtab_attiny26[12]; // ATtiny26 +extern const char * const vtab_attiny28[6]; // ATtiny28 +extern const char * const vtab_attiny43u[16]; // ATtiny43U +extern const char * const vtab_attiny84a[17]; // ATtiny84A, ATtiny84, ATtiny44A, ATtiny44, ATtiny24A, ATtiny24 +extern const char * const vtab_attiny85[15]; // ATtiny85, ATtiny45, ATtiny25 +extern const char * const vtab_attiny88[20]; // ATtiny88, ATtiny48 +extern const char * const vtab_attiny167[20]; // ATtiny167, ATtiny87, ATA664251, ATA6617C, ATA6616C, ATA5505 +extern const char * const vtab_attiny828[26]; // ATtiny828 +extern const char * const vtab_attiny841[30]; // ATtiny841, ATtiny441 +extern const char * const vtab_attiny861a[19]; // ATtiny861A, ATtiny861, ATtiny461A, ATtiny461, ATtiny261A, ATtiny261 +extern const char * const vtab_attiny1634[28]; // ATtiny1634 +extern const char * const vtab_attiny2313[19]; // ATtiny2313 +extern const char * const vtab_attiny4313[21]; // ATtiny4313, ATtiny2313A +extern const char * const vtab_atmega8a[19]; // ATmega8A, ATmega8 +extern const char * const vtab_atmega16a[21]; // ATmega16A, ATmega16 +extern const char * const vtab_atmega16hva[21]; // ATmega16HVA, ATmega8HVA +extern const char * const vtab_atmega16hva2[22]; // ATmega16HVA2 +extern const char * const vtab_atmega32hvbrevb[29]; // ATmega32HVBrevB, ATmega32HVB, ATmega16HVBrevB, ATmega16HVB +extern const char * const vtab_atmega32u2[29]; // ATmega32U2, ATmega16U2, ATmega8U2, AT90USB162, AT90USB82 +extern const char * const vtab_atmega32u4[43]; // ATmega32U4, ATmega16U4 +extern const char * const vtab_atmega32u6[38]; // ATmega32U6, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646 +extern const char * const vtab_atmega64m1[31]; // ATmega64M1, ATmega64C1, ATmega32M1, ATmega32C1, ATmega16M1 +extern const char * const vtab_atmega64hve2[25]; // ATmega64HVE2, ATmega64HVE +extern const char * const vtab_atmega103[24]; // ATmega103 +extern const char * const vtab_atmega128a[35]; // ATmega128A, ATmega128, ATmega64A, ATmega64 +extern const char * const vtab_atmega128rfa1[72]; // ATmega128RFA1 +extern const char * const vtab_atmega161[21]; // ATmega161 +extern const char * const vtab_atmega162[28]; // ATmega162 +extern const char * const vtab_atmega163[18]; // ATmega163 +extern const char * const vtab_atmega168pb[27]; // ATmega168PB, ATmega88PB, ATmega48PB +extern const char * const vtab_atmega323[21]; // ATmega323, ATmega32A, ATmega32 +extern const char * const vtab_atmega324pb[51]; // ATmega324PB +extern const char * const vtab_atmega328[26]; // ATmega328, ATmega168 +extern const char * const vtab_atmega328p[26]; // ATmega328P, ATmega168PA, ATmega168P, ATmega168A, ATmega88PA, ATmega88P, ATmega88A, ATmega88, ATmega48PA, ATmega48P, ATmega48A, ATmega48, ATA6614Q, ATA6613C, ATA6612C +extern const char * const vtab_atmega328pb[45]; // ATmega328PB +extern const char * const vtab_atmega406[23]; // ATmega406 +extern const char * const vtab_atmega644[28]; // ATmega644 +extern const char * const vtab_atmega644pa[31]; // ATmega644PA, ATmega644P, ATmega644A, ATmega324PA, ATmega324P, ATmega324A, ATmega164PA, ATmega164P, ATmega164A +extern const char * const vtab_atmega645p[22]; // ATmega645P, ATmega645A, ATmega645, ATmega325PA, ATmega325P, ATmega325A, ATmega325, ATmega165PA, ATmega165P, ATmega165A, ATmega165 +extern const char * const vtab_atmega649p[23]; // ATmega649P, ATmega649A, ATmega649, ATmega329PA, ATmega329P, ATmega329A, ATmega329, ATmega169PA, ATmega169P, ATmega169A, ATmega169 +extern const char * const vtab_atmega1284p[35]; // ATmega1284P, ATmega1284 +extern const char * const vtab_atmega2561[57]; // ATmega2561, ATmega2560, ATmega1281, ATmega1280, ATmega640 +extern const char * const vtab_atmega2564rfr2[77]; // ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2 +extern const char * const vtab_atmega6450p[25]; // ATmega6450P, ATmega6450A, ATmega6450, ATmega3250PA, ATmega3250P, ATmega3250A, ATmega3250 +extern const char * const vtab_atmega6490p[25]; // ATmega6490P, ATmega6490A, ATmega6490, ATmega3290PA, ATmega3290P, ATmega3290A, ATmega3290 +extern const char * const vtab_atmega8515[17]; // ATmega8515 +extern const char * const vtab_atmega8535[21]; // ATmega8535 +extern const char * const vtab_at86rf401[3]; // AT86RF401 +extern const char * const vtab_at90pwm2[32]; // AT90PWM2 +extern const char * const vtab_at90pwm3b[32]; // AT90PWM3B, AT90PWM3, AT90PWM2B +extern const char * const vtab_at90scr100[38]; // AT90SCR100 +extern const char * const vtab_at90can128[37]; // AT90CAN128, AT90CAN64, AT90CAN32 +extern const char * const vtab_at90pwm161[20]; // AT90PWM161, AT90PWM81 +extern const char * const vtab_at90pwm316[32]; // AT90PWM316, AT90PWM216, AT90PWM1 +extern const char * const vtab_at90s1200[4]; // AT90S1200 +extern const char * const vtab_at90s2313[11]; // AT90S2313 +extern const char * const vtab_at90s4433[14]; // AT90S4433, AT90S2333 +extern const char * const vtab_at90s8515[13]; // AT90S8515, AT90S4414 +extern const char * const vtab_at90s8535[17]; // AT90S8535, AT90S4434 +extern const char * const vtab_ata5272[37]; // ATA5272 +extern const char * const vtab_ata5702m322[51]; // ATA5702M322, ATA5700M322 +extern const char * const vtab_ata5790[30]; // ATA5790 +extern const char * const vtab_ata5791[31]; // ATA5791, ATA5790N +extern const char * const vtab_ata5795[23]; // ATA5795 +extern const char * const vtab_ata5835[44]; // ATA5835, ATA5787 +extern const char * const vtab_ata6289[27]; // ATA6289, ATA6286, ATA6285 +extern const char * const vtab_ata8515[42]; // ATA8515, ATA8510, ATA8215, ATA8210, ATA5833, ATA5832, ATA5831, ATA5783, ATA5782, ATA5781 +extern const char * const vtab_atxmega32a4[94]; // ATxmega32A4, ATxmega16A4 +extern const char * const vtab_atxmega32c4[127]; // ATxmega32C4, ATxmega16C4 +extern const char * const vtab_atxmega32d4[91]; // ATxmega32D4, ATxmega16D4 +extern const char * const vtab_atxmega32e5[43]; // ATxmega32E5, ATxmega16E5, ATxmega8E5 +extern const char * const vtab_atxmega128a1[125]; // ATxmega128A1, ATxmega64A1 +extern const char * const vtab_atxmega128a1u[127]; // ATxmega128A1U, ATxmega64A1U +extern const char * const vtab_atxmega128b1[81]; // ATxmega128B1, ATxmega64B1 +extern const char * const vtab_atxmega128b3[54]; // ATxmega128B3, ATxmega64B3 +extern const char * const vtab_atxmega128a4u[127]; // ATxmega128A4U, ATxmega64A4U, ATxmega32A4U, ATxmega16A4U +extern const char * const vtab_atxmega128d4[91]; // ATxmega128D4, ATxmega64D4 +extern const char * const vtab_atxmega256a3[122]; // ATxmega256A3, ATxmega192A3, ATxmega128A3, ATxmega64A3 +extern const char * const vtab_atxmega256a3b[122]; // ATxmega256A3B +extern const char * const vtab_atxmega256a3bu[127]; // ATxmega256A3BU +extern const char * const vtab_atxmega256a3u[127]; // ATxmega256A3U, ATxmega192A3U, ATxmega128A3U, ATxmega64A3U +extern const char * const vtab_atxmega256c3[127]; // ATxmega256C3, ATxmega192C3, ATxmega128C3, ATxmega64C3, ATxmega32C3 +extern const char * const vtab_atxmega384c3[127]; // ATxmega384C3 +extern const char * const vtab_atxmega384d3[114]; // ATxmega384D3, ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3, ATxmega32D3 +extern const char * const vtab_attiny402[26]; // ATtiny402, ATtiny202 +extern const char * const vtab_attiny404[26]; // ATtiny404, ATtiny204 +extern const char * const vtab_attiny406[26]; // ATtiny406 +extern const char * const vtab_attiny412[26]; // ATtiny412, ATtiny212 +extern const char * const vtab_attiny814[26]; // ATtiny814, ATtiny414, ATtiny214 +extern const char * const vtab_attiny817[26]; // ATtiny817, ATtiny816, ATtiny417, ATtiny416auto, ATtiny416 +extern const char * const vtab_attiny1607[31]; // ATtiny1607, ATtiny1606, ATtiny1604, ATtiny807, ATtiny806, ATtiny804 +extern const char * const vtab_attiny1614[31]; // ATtiny1614 +extern const char * const vtab_attiny3214[31]; // ATtiny3214 +extern const char * const vtab_attiny3217[31]; // ATtiny3217, ATtiny3216, ATtiny1617, ATtiny1616 +extern const char * const vtab_attiny3227[30]; // ATtiny3227, ATtiny3226, ATtiny3224, ATtiny1627, ATtiny1626, ATtiny1624, ATtiny827, ATtiny826, ATtiny824, ATtiny427, ATtiny426, ATtiny424 +extern const char * const vtab_atmega4808[36]; // ATmega4808, ATmega3208, ATmega1608, ATmega808 +extern const char * const vtab_atmega4809[40]; // ATmega4809, ATmega3209, ATmega1609, ATmega809 +extern const char * const vtab_avr64dd32[36]; // AVR64DD32, AVR64DD28, AVR64DD20, AVR64DD14, AVR32DD32, AVR32DD28, AVR32DD20, AVR32DD14, AVR16DD32, AVR16DD28, AVR16DD20, AVR16DD14 +extern const char * const vtab_avr64ea32[37]; // AVR64EA32, AVR64EA28 +extern const char * const vtab_avr64ea48[45]; // AVR64EA48 +extern const char * const vtab_avr128da28[41]; // AVR128DA28, AVR64DA28, AVR32DA28 +extern const char * const vtab_avr128db28[42]; // AVR128DB28, AVR64DB28, AVR32DB28 +extern const char * const vtab_avr128da32[44]; // AVR128DA32, AVR64DA32, AVR32DA32 +extern const char * const vtab_avr128db32[44]; // AVR128DB32, AVR64DB32, AVR32DB32 +extern const char * const vtab_avr128da48[58]; // AVR128DA48, AVR64DA48, AVR32DA48 +extern const char * const vtab_avr128db48[61]; // AVR128DB48, AVR64DB48, AVR32DB48 +extern const char * const vtab_avr128da64[64]; // AVR128DA64, AVR64DA64 +extern const char * const vtab_avr128db64[65]; // AVR128DB64, AVR64DB64 + +extern const uPcore_t uP_table[372]; + +#endif diff --git a/src/avrpart.c b/src/avrpart.c index fb04a157..1e4fefee 100644 --- a/src/avrpart.c +++ b/src/avrpart.c @@ -583,6 +583,7 @@ AVRPART *avr_new_part(void) { p->mem_alias = lcreat(NULL, 0); // Default values + p->mcuid = -1; p->hvupdi_variant = -1; memset(p->signature, 0xFF, 3); p->reset_disposition = RESET_DEDICATED; diff --git a/src/bitbang.c b/src/bitbang.c index c043d740..af468926 100644 --- a/src/bitbang.c +++ b/src/bitbang.c @@ -422,7 +422,7 @@ int bitbang_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char res[4]; AVRMEM *mem; - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { pgm->pgm_led(pgm, ON); while (avr_tpi_poll_nvmbsy(pgm)); @@ -482,7 +482,7 @@ int bitbang_program_enable(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char res[4]; int i; - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { /* enable NVM programming */ bitbang_tpi_tx(pgm, TPI_CMD_SKEY); for (i = sizeof(tpi_skey) - 1; i >= 0; i--) @@ -524,7 +524,7 @@ int bitbang_initialize(const PROGRAMMER *pgm, const AVRPART *p) { usleep(20000); /* TPIDATA is a single line, so MISO & MOSI should be connected */ - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { /* make sure cmd_tpi() is defined */ if (pgm->cmd_tpi == NULL) { avrdude_message(MSG_INFO, "%s: Error: %s programmer does not support TPI\n", @@ -559,7 +559,7 @@ int bitbang_initialize(const PROGRAMMER *pgm, const AVRPART *p) { pgm->setpin(pgm, PIN_AVR_RESET, 0); usleep(20000); - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { /* keep TPIDATA high for 16 clock cycles */ pgm->setpin(pgm, PIN_AVR_MOSI, 1); for (i = 0; i < 16; i++) diff --git a/src/config.c b/src/config.c index d36e0814..a0351833 100644 --- a/src/config.c +++ b/src/config.c @@ -24,12 +24,14 @@ #include #include #include +#include #include #include #include "avrdude.h" #include "libavrdude.h" #include "config.h" +#include "avrintel.h" #include "config_gram.h" @@ -44,6 +46,7 @@ LISTID number_list; PROGRAMMER * current_prog; AVRPART * current_part; AVRMEM * current_mem; +int current_strct; LISTID part_list; LISTID programmers; bool is_alias; @@ -53,6 +56,22 @@ char * cfg_infile; extern char * yytext; +#define pgm_comp_desc(x, type) { #x, COMP_PROGRAMMER, offsetof(PROGRAMMER, x), sizeof(((PROGRAMMER *) NULL)->x), type } +#define part_comp_desc(x, type) { #x, COMP_AVRPART, offsetof(AVRPART, x), sizeof(((AVRPART *) NULL)->x), type } +#define mem_comp_desc(x, type) { #x, COMP_AVRMEM, offsetof(AVRMEM, x), sizeof(((AVRMEM *) NULL)->x), type } + +// Component description for config_gram.y, will be sorted appropriately on first use +Component_t avr_comp[] = { + // PROGRAMMER + pgm_comp_desc(prog_modes, COMP_INT), + + // AVRPART + part_comp_desc(prog_modes, COMP_INT), + part_comp_desc(mcuid, COMP_INT), + part_comp_desc(n_interrupts, COMP_INT), + part_comp_desc(n_page_erase, COMP_INT), +}; + #define DEBUG 0 void cleanup_config(void) @@ -190,7 +209,7 @@ void free_tokens(int n, ...) -TOKEN *number(const char *text) { +TOKEN *new_number(const char *text) { struct token_t *tkn = new_token(TKN_NUMBER); tkn->value.type = V_NUM; tkn->value.number = atoi(text); @@ -202,7 +221,7 @@ TOKEN *number(const char *text) { return tkn; } -TOKEN *number_real(const char *text) { +TOKEN *new_number_real(const char *text) { struct token_t * tkn = new_token(TKN_NUMBER); tkn->value.type = V_NUM_REAL; tkn->value.number_real = atof(text); @@ -214,7 +233,7 @@ TOKEN *number_real(const char *text) { return tkn; } -TOKEN *hexnumber(const char *text) { +TOKEN *new_hexnumber(const char *text) { struct token_t *tkn = new_token(TKN_NUMBER); char * e; @@ -233,11 +252,41 @@ TOKEN *hexnumber(const char *text) { return tkn; } +TOKEN *new_constant(const char *con) { + struct token_t *tkn = new_token(TKN_NUMBER); + int assigned = 1; -TOKEN *string(const char *text) { + tkn->value.type = V_NUM; + tkn->value.number = + !strcmp("PM_SPM", con)? PM_SPM: + !strcmp("PM_TPI", con)? PM_TPI: + !strcmp("PM_ISP", con)? PM_ISP: + !strcmp("PM_PDI", con)? PM_PDI: + !strcmp("PM_UPDI", con)? PM_UPDI: + !strcmp("PM_HVSP", con)? PM_HVSP: + !strcmp("PM_HVPP", con)? PM_HVPP: + !strcmp("PM_debugWIRE", con)? PM_debugWIRE: + !strcmp("PM_JTAG", con)? PM_JTAG: + !strcmp("PM_aWire", con)? PM_aWire: + (assigned = 0); + + if(!assigned) { + yyerror("can't identify constant %s", con); + free_token(tkn); + return NULL; + } + +#if DEBUG + avrdude_message(MSG_INFO, "CONSTANT(%s=%d)\n", con, tkn->value.number); +#endif + + return tkn; +} + +TOKEN *new_string(const char *text) { struct token_t *tkn = new_token(TKN_STRING); tkn->value.type = V_STR; - tkn->value.string = cfg_strdup("string()", text); + tkn->value.string = cfg_strdup("new_string()", text); #if DEBUG avrdude_message(MSG_INFO, "STRING(%s)\n", tkn->value.string); @@ -247,7 +296,7 @@ TOKEN *string(const char *text) { } -TOKEN * keyword(int primary) { +TOKEN *new_keyword(int primary) { return new_token(primary); } @@ -692,3 +741,145 @@ char *cfg_escape(const char *s) { return cfg_strdup("cfg_escape()", buf); } + + +static int cmp_comp(const void *v1, const void *v2) { + const Component_t *c1 = v1, *c2 = v2; + int ret = strcmp(c1->name, c2->name); + + return ret? ret: c1->strct - c2->strct; +} + +Component_t *cfg_comp_search(const char *name, int strct) { + static int init; + Component_t key; + + if(!init++) + qsort(avr_comp, sizeof avr_comp/sizeof*avr_comp, sizeof(Component_t), cmp_comp); + + + key.name = name; + key.strct = strct; + return bsearch(&key, avr_comp, sizeof avr_comp/sizeof*avr_comp, sizeof(Component_t), cmp_comp); +} + + +const char *cfg_strct_name(int strct) { + switch(strct) { + case COMP_CONFIG_MAIN: return "avrdude.conf main"; + case COMP_AVRPART: return "AVRPART"; + case COMP_AVRMEM: return "AVRMEM"; + case COMP_PROGRAMMER: return "PROGRAMMER"; + } + return "unknown struct"; +} + +const char *cfg_v_type(int type) { + switch(type) { + case V_NONE: return "void"; + case V_NUM: return "number"; + case V_NUM_REAL: return "real"; + case V_STR: return "string"; + case V_COMPONENT: return "component"; + } + return "unknown v type"; +} + +const char *cfg_comp_type(int type) { + switch(type) { + case COMP_INT: return "number"; + case COMP_SHORT: return "short"; + case COMP_CHAR: return "char"; + case COMP_STRING: return "string"; + case COMP_CHAR_ARRAY: return "byte array"; + case COMP_INT_LISTID: return "number list"; + case COMP_STRING_LISTID: return "string list"; + case COMP_OPCODE: return "opcode"; + case COMP_PIN: return "pin"; + case COMP_PIN_LIST: return "pin list"; + } + return "unknown comp type"; +} + + +// Used by config_gram.y to assign a component in one of the relevant structures with a value +void cfg_assign(char *sp, int strct, Component_t *cp, VALUE *v) { + const char *str; + int num; + + switch(cp->type) { + case COMP_CHAR: + case COMP_SHORT: + case COMP_INT: + if(v->type != V_NUM) { + yywarning("%s in %s expects a %s but is assigned a %s", + cp->name, cfg_strct_name(strct), cfg_comp_type(cp->type), cfg_v_type(v->type)); + return; + } + // TODO: consider endianess (code currently assumes little endian) + num = v->number; + memcpy(sp+cp->offset, &num, cp->size); + break; + case COMP_STRING: + if(v->type != V_STR) { + yywarning("%s in %s expects a string but is assigned a %s", + cp->name, cfg_strct_name(strct), cfg_v_type(v->type)); + return; + } + str = cache_string(v->string); + memcpy(sp+cp->offset, &str, cp->size); + break; + // TODO: implement COMP_CHAR_ARRAY, COMP_INT_LISTID, COMP_STRING_LISTID, ... + default: + yywarning("%s in %s expects a %s but that is not implemented", + cp->name, cfg_strct_name(strct), cfg_comp_type(cp->type)); + } +} + +// Automatically assign an mcuid if known from avrintel.c table +void cfg_update_mcuid(AVRPART *part) { + // Don't assign an mcuid for template parts that has a space in desc + if(!part->desc || *part->desc == 0 || strchr(part->desc, ' ')) + return; + + // Don't assign an mcuid for template parts where id starts with "." + if(!part->id || !*part->id || *part->id == '.') + return; + + // Don't assign an mcuid for 32-bit AVR parts + if(part->prog_modes & PM_aWire) + return; + + // Find an entry that shares the same name + for(int i=0; i < sizeof uP_table/sizeof *uP_table; i++) { + if(strcasecmp(part->desc, uP_table[i].name) == 0) { + if(part->mcuid != (int) uP_table[i].mcuid) { + part->mcuid = uP_table[i].mcuid; + yywarning("assigned mcuid = %d to part %s", part->mcuid, part->desc); + } + return; + } + } + + // None have the same name: an entry with part->mcuid might be an error + for(int i=0; i < sizeof uP_table/sizeof *uP_table; i++) + if(part->mcuid == (int) uP_table[i].mcuid) { + // Complain unless it can be considered a variant, eg, ATmega32L and ATmega32 + AVRMEM *flash = avr_locate_mem(part, "flash"); + if(flash) { + size_t l1 = strlen(part->desc), l2 = strlen(uP_table[i].name); + if(strncasecmp(part->desc, uP_table[i].name, l1 < l2? l1: l2) || + flash->size != uP_table[i].flashsize || + flash->page_size != uP_table[i].pagesize || + part->n_interrupts != uP_table[i].ninterrupts) + yywarning("mcuid %d is reserved for %s, use a free number >= %d", + part->mcuid, uP_table[i].name, sizeof uP_table/sizeof *uP_table); + } + return; + } + + // Range check + if(part->mcuid < 0 || part->mcuid >= UB_N_MCU) + yywarning("mcuid %d for %s is out of range [0..%d], use a free number >= %d", + part->mcuid, part->desc, UB_N_MCU-1, sizeof uP_table/sizeof *uP_table); +} diff --git a/src/config.h b/src/config.h index b8bd2031..8bacda42 100644 --- a/src/config.h +++ b/src/config.h @@ -37,13 +37,48 @@ typedef struct { } COMMENT; -enum { V_NONE, V_NUM, V_NUM_REAL, V_STR }; +enum { // Which structures a component can occur in + COMP_CONFIG_MAIN, + COMP_PROGRAMMER, + COMP_AVRPART, + COMP_AVRMEM, +}; + +enum { // Component types in structure + COMP_INT, + COMP_SHORT, + COMP_CHAR, + COMP_STRING, + COMP_CHAR_ARRAY, // This and below are not yet implemented + COMP_INT_LISTID, + COMP_STRING_LISTID, + COMP_OPCODE, + COMP_PIN, // Pins may never be implemented + COMP_PIN_LIST +}; + +typedef struct { // Description of a component in a structure + const char *name; // Component name + int strct; // Structure, eg, COMP_AVRPART + int offset, size, type; // Location, size and type within structure +} Component_t; + + +enum { // Value types for VALUE struct + V_NONE, + V_NUM, + V_NUM_REAL, + V_STR, + V_COMPONENT, +}; + typedef struct value_t { int type; union { int number; double number_real; char * string; + Component_t *comp; }; } VALUE; @@ -59,6 +94,7 @@ extern FILE * yyin; extern PROGRAMMER * current_prog; extern AVRPART * current_part; extern AVRMEM * current_mem; +extern int current_strct; extern int cfg_lineno; extern char * cfg_infile; extern LISTID string_list; @@ -87,15 +123,17 @@ void free_token(TOKEN *tkn); void free_tokens(int n, ...); -TOKEN *number(const char *text); +TOKEN *new_number(const char *text); -TOKEN *number_real(const char *text); +TOKEN *new_number_real(const char *text); -TOKEN *hexnumber(const char *text); +TOKEN *new_hexnumber(const char *text); -TOKEN *string(const char *text); +TOKEN *new_constant(const char *text); -TOKEN *keyword(int primary); +TOKEN *new_string(const char *text); + +TOKEN *new_keyword(int primary); void print_token(TOKEN *tkn); @@ -115,6 +153,16 @@ LISTID cfg_move_comments(void); void cfg_pop_comms(void); +Component_t *cfg_comp_search(const char *name, int strct); + +const char *cfg_v_type(int type); + +const char *cfg_strct_name(int strct); + +void cfg_assign(char *sp, int strct, Component_t *cp, VALUE *v); + +void cfg_update_mcuid(AVRPART *part); + #ifdef __cplusplus } #endif diff --git a/src/config_gram.y b/src/config_gram.y index dfdf50b5..ca47dab5 100644 --- a/src/config_gram.y +++ b/src/config_gram.y @@ -208,19 +208,26 @@ static int pin_name; %token TKN_COMMA %token TKN_EQUAL %token TKN_SEMI -%token TKN_TILDE %token TKN_LEFT_PAREN %token TKN_RIGHT_PAREN %token TKN_NUMBER %token TKN_NUMBER_REAL %token TKN_STRING +%token TKN_COMPONENT + +%left OP_OR /* calculator operations */ +%left OP_XOR +%left OP_AND +%left OP_PLUS OP_MINUS +%left OP_TIMES OP_DIVIDE OP_MODULO +%right OP_TILDE UNARY %start configuration %% number_real : - TKN_NUMBER { + numexpr { $$ = $1; /* convert value to real */ $$->value.number_real = $$->value.number; @@ -229,6 +236,27 @@ number_real : TKN_NUMBER_REAL { $$ = $1; } +; + + +expr: numexpr | TKN_STRING; + +numexpr: + TKN_NUMBER | + numexpr OP_OR numexpr { $$ = $1; $$->value.number |= $3->value.number; } | + numexpr OP_XOR numexpr { $$ = $1; $$->value.number ^= $3->value.number; } | + numexpr OP_AND numexpr { $$ = $1; $$->value.number &= $3->value.number; } | + numexpr OP_PLUS numexpr { $$ = $1; $$->value.number += $3->value.number; } | + numexpr OP_MINUS numexpr { $$ = $1; $$->value.number -= $3->value.number; } | + numexpr OP_TIMES numexpr { $$ = $1; $$->value.number *= $3->value.number; } | + numexpr OP_DIVIDE numexpr { $$ = $1; $$->value.number /= $3->value.number; } | + numexpr OP_MODULO numexpr { $$ = $1; $$->value.number %= $3->value.number; } | + OP_PLUS numexpr %prec UNARY { $$ = $2; } | + OP_MINUS numexpr %prec UNARY { $$ = $2; $$->value.number = -$$->value.number; } | + OP_TILDE numexpr %prec UNARY { $$ = $2; $$->value.number = ~$$->value.number; } | + TKN_LEFT_PAREN numexpr TKN_RIGHT_PAREN { $$ = $2; } +; + configuration : /* empty */ | config @@ -302,6 +330,7 @@ prog_def : // pgm_fill_old_pins(current_prog); // TODO to be removed if old pin data no longer needed // pgm_display_generic(current_prog, id); current_prog = NULL; + current_strct = COMP_CONFIG_MAIN; } ; @@ -309,6 +338,7 @@ prog_def : prog_decl : K_PROGRAMMER { current_prog = pgm_new(); + current_strct = COMP_PROGRAMMER; current_prog->config_file = cache_string(cfg_infile); current_prog->lineno = cfg_lineno; } @@ -322,6 +352,7 @@ prog_decl : YYABORT; } current_prog = pgm_dup(pgm); + current_strct = COMP_PROGRAMMER; current_prog->parent_id = cache_string($3->value.string); current_prog->comments = NULL; current_prog->config_file = cache_string(cfg_infile); @@ -343,6 +374,8 @@ part_def : YYABORT; } + cfg_update_mcuid(current_part); + // Sanity checks for memory sizes and compute/override num_pages entry for (ln=lfirst(current_part->mem); ln; ln=lnext(ln)) { m = ldata(ln); @@ -389,6 +422,7 @@ part_def : current_part->comments = cfg_move_comments(); LISTADD(part_list, current_part); current_part = NULL; + current_strct = COMP_CONFIG_MAIN; } ; @@ -396,6 +430,7 @@ part_decl : K_PART { current_part = avr_new_part(); + current_strct = COMP_AVRPART; current_part->config_file = cache_string(cfg_infile); current_part->lineno = cfg_lineno; } | @@ -409,6 +444,7 @@ part_decl : } current_part = avr_dup_part(parent_part); + current_strct = COMP_AVRPART; current_part->parent_id = cache_string($3->value.string); current_part->comments = NULL; current_part->config_file = cache_string(cfg_infile); @@ -425,8 +461,8 @@ string_list : num_list : - TKN_NUMBER { ladd(number_list, $1); } | - num_list TKN_COMMA TKN_NUMBER { ladd(number_list, $3); } + numexpr { ladd(number_list, $1); } | + num_list TKN_COMMA numexpr { ladd(number_list, $3); } ; prog_parms : @@ -435,6 +471,10 @@ prog_parms : ; prog_parm : + TKN_COMPONENT TKN_EQUAL expr { + cfg_assign((char *) current_prog, COMP_PROGRAMMER, $1->value.comp, &$3->value); + free_token($1); + } | K_ID TKN_EQUAL string_list { { while (lsize(string_list)) { @@ -456,7 +496,7 @@ prog_parm : current_prog->desc = cache_string($3->value.string); free_token($3); } | - K_BAUDRATE TKN_EQUAL TKN_NUMBER { + K_BAUDRATE TKN_EQUAL numexpr { { current_prog->baudrate = $3->value.number; free_token($3); @@ -505,7 +545,7 @@ prog_parm_usb: free_token($3); } } | - K_USBVID TKN_EQUAL TKN_NUMBER { + K_USBVID TKN_EQUAL numexpr { { current_prog->usbvid = $3->value.number; free_token($3); @@ -533,7 +573,7 @@ prog_parm_usb: ; usb_pid_list: - TKN_NUMBER { + numexpr { { /* overwrite pids, so clear the existing entries */ if(current_prog->usbpid) @@ -547,7 +587,7 @@ usb_pid_list: free_token($1); } } | - usb_pid_list TKN_COMMA TKN_NUMBER { + usb_pid_list TKN_COMMA numexpr { { int *ip = cfg_malloc("usb_pid_list", sizeof(int)); *ip = $3->value.number; @@ -562,7 +602,7 @@ prog_parm_updi: ; hvupdi_support_list: - TKN_NUMBER { + numexpr { { /* overwrite list entries, so clear the existing entries */ if(current_prog->hvupdi_support) @@ -576,7 +616,7 @@ hvupdi_support_list: free_token($1); } } | - hvupdi_support_list TKN_COMMA TKN_NUMBER { + hvupdi_support_list TKN_COMMA numexpr { { int *ip = cfg_malloc("hvupdi_support_list", sizeof(int)); *ip = $3->value.number; @@ -589,7 +629,7 @@ hvupdi_support_list: pin_number_non_empty: TKN_NUMBER { if(0 != assign_pin(pin_name, $1, 0)) YYABORT; } | - TKN_TILDE TKN_NUMBER { if(0 != assign_pin(pin_name, $2, 1)) YYABORT; } + OP_TILDE TKN_NUMBER { if(0 != assign_pin(pin_name, $2, 1)) YYABORT; } ; pin_number: @@ -601,7 +641,7 @@ pin_number: pin_list_element: pin_number_non_empty | - TKN_TILDE TKN_LEFT_PAREN num_list TKN_RIGHT_PAREN { if(0 != assign_pin_list(1)) YYABORT; } + OP_TILDE TKN_LEFT_PAREN num_list TKN_RIGHT_PAREN { if(0 != assign_pin_list(1)) YYABORT; } ; pin_list_non_empty: @@ -665,6 +705,10 @@ retry_lines : ; part_parm : + TKN_COMPONENT TKN_EQUAL expr { + cfg_assign((char *) current_part, COMP_AVRPART, $1->value.comp, &$3->value); + free_token($1); + } | K_ID TKN_EQUAL TKN_STRING { current_part->id = cache_string($3->value.string); @@ -683,13 +727,13 @@ part_parm : free_token($3); } | - K_HVUPDI_VARIANT TKN_EQUAL TKN_NUMBER + K_HVUPDI_VARIANT TKN_EQUAL numexpr { current_part->hvupdi_variant = $3->value.number; free_token($3); } | - K_DEVICECODE TKN_EQUAL TKN_NUMBER { + K_DEVICECODE TKN_EQUAL numexpr { { yyerror("devicecode is deprecated, use " "stk500_devcode instead"); @@ -697,14 +741,14 @@ part_parm : } } | - K_STK500_DEVCODE TKN_EQUAL TKN_NUMBER { + K_STK500_DEVCODE TKN_EQUAL numexpr { { current_part->stk500_devcode = $3->value.number; free_token($3); } } | - K_AVR910_DEVCODE TKN_EQUAL TKN_NUMBER { + K_AVR910_DEVCODE TKN_EQUAL numexpr { { current_part->avr910_devcode = $3->value.number; free_token($3); @@ -722,7 +766,7 @@ part_parm : } } | - K_USBPID TKN_EQUAL TKN_NUMBER { + K_USBPID TKN_EQUAL numexpr { { current_part->usbpid = $3->value.number; free_token($3); @@ -877,19 +921,19 @@ part_parm : } } | - K_CHIP_ERASE_DELAY TKN_EQUAL TKN_NUMBER + K_CHIP_ERASE_DELAY TKN_EQUAL numexpr { current_part->chip_erase_delay = $3->value.number; free_token($3); } | - K_PAGEL TKN_EQUAL TKN_NUMBER + K_PAGEL TKN_EQUAL numexpr { current_part->pagel = $3->value.number; free_token($3); } | - K_BS2 TKN_EQUAL TKN_NUMBER + K_BS2 TKN_EQUAL numexpr { current_part->bs2 = $3->value.number; free_token($3); @@ -905,169 +949,169 @@ part_parm : free_tokens(2, $1, $3); } | - K_TIMEOUT TKN_EQUAL TKN_NUMBER + K_TIMEOUT TKN_EQUAL numexpr { current_part->timeout = $3->value.number; free_token($3); } | - K_STABDELAY TKN_EQUAL TKN_NUMBER + K_STABDELAY TKN_EQUAL numexpr { current_part->stabdelay = $3->value.number; free_token($3); } | - K_CMDEXEDELAY TKN_EQUAL TKN_NUMBER + K_CMDEXEDELAY TKN_EQUAL numexpr { current_part->cmdexedelay = $3->value.number; free_token($3); } | - K_HVSPCMDEXEDELAY TKN_EQUAL TKN_NUMBER + K_HVSPCMDEXEDELAY TKN_EQUAL numexpr { current_part->hvspcmdexedelay = $3->value.number; free_token($3); } | - K_SYNCHLOOPS TKN_EQUAL TKN_NUMBER + K_SYNCHLOOPS TKN_EQUAL numexpr { current_part->synchloops = $3->value.number; free_token($3); } | - K_BYTEDELAY TKN_EQUAL TKN_NUMBER + K_BYTEDELAY TKN_EQUAL numexpr { current_part->bytedelay = $3->value.number; free_token($3); } | - K_POLLVALUE TKN_EQUAL TKN_NUMBER + K_POLLVALUE TKN_EQUAL numexpr { current_part->pollvalue = $3->value.number; free_token($3); } | - K_POLLINDEX TKN_EQUAL TKN_NUMBER + K_POLLINDEX TKN_EQUAL numexpr { current_part->pollindex = $3->value.number; free_token($3); } | - K_PREDELAY TKN_EQUAL TKN_NUMBER + K_PREDELAY TKN_EQUAL numexpr { current_part->predelay = $3->value.number; free_token($3); } | - K_POSTDELAY TKN_EQUAL TKN_NUMBER + K_POSTDELAY TKN_EQUAL numexpr { current_part->postdelay = $3->value.number; free_token($3); } | - K_POLLMETHOD TKN_EQUAL TKN_NUMBER + K_POLLMETHOD TKN_EQUAL numexpr { current_part->pollmethod = $3->value.number; free_token($3); } | - K_HVENTERSTABDELAY TKN_EQUAL TKN_NUMBER + K_HVENTERSTABDELAY TKN_EQUAL numexpr { current_part->hventerstabdelay = $3->value.number; free_token($3); } | - K_PROGMODEDELAY TKN_EQUAL TKN_NUMBER + K_PROGMODEDELAY TKN_EQUAL numexpr { current_part->progmodedelay = $3->value.number; free_token($3); } | - K_LATCHCYCLES TKN_EQUAL TKN_NUMBER + K_LATCHCYCLES TKN_EQUAL numexpr { current_part->latchcycles = $3->value.number; free_token($3); } | - K_TOGGLEVTG TKN_EQUAL TKN_NUMBER + K_TOGGLEVTG TKN_EQUAL numexpr { current_part->togglevtg = $3->value.number; free_token($3); } | - K_POWEROFFDELAY TKN_EQUAL TKN_NUMBER + K_POWEROFFDELAY TKN_EQUAL numexpr { current_part->poweroffdelay = $3->value.number; free_token($3); } | - K_RESETDELAYMS TKN_EQUAL TKN_NUMBER + K_RESETDELAYMS TKN_EQUAL numexpr { current_part->resetdelayms = $3->value.number; free_token($3); } | - K_RESETDELAYUS TKN_EQUAL TKN_NUMBER + K_RESETDELAYUS TKN_EQUAL numexpr { current_part->resetdelayus = $3->value.number; free_token($3); } | - K_HVLEAVESTABDELAY TKN_EQUAL TKN_NUMBER + K_HVLEAVESTABDELAY TKN_EQUAL numexpr { current_part->hvleavestabdelay = $3->value.number; free_token($3); } | - K_RESETDELAY TKN_EQUAL TKN_NUMBER + K_RESETDELAY TKN_EQUAL numexpr { current_part->resetdelay = $3->value.number; free_token($3); } | - K_CHIPERASEPULSEWIDTH TKN_EQUAL TKN_NUMBER + K_CHIPERASEPULSEWIDTH TKN_EQUAL numexpr { current_part->chiperasepulsewidth = $3->value.number; free_token($3); } | - K_CHIPERASEPOLLTIMEOUT TKN_EQUAL TKN_NUMBER + K_CHIPERASEPOLLTIMEOUT TKN_EQUAL numexpr { current_part->chiperasepolltimeout = $3->value.number; free_token($3); } | - K_CHIPERASETIME TKN_EQUAL TKN_NUMBER + K_CHIPERASETIME TKN_EQUAL numexpr { current_part->chiperasetime = $3->value.number; free_token($3); } | - K_PROGRAMFUSEPULSEWIDTH TKN_EQUAL TKN_NUMBER + K_PROGRAMFUSEPULSEWIDTH TKN_EQUAL numexpr { current_part->programfusepulsewidth = $3->value.number; free_token($3); } | - K_PROGRAMFUSEPOLLTIMEOUT TKN_EQUAL TKN_NUMBER + K_PROGRAMFUSEPOLLTIMEOUT TKN_EQUAL numexpr { current_part->programfusepolltimeout = $3->value.number; free_token($3); } | - K_PROGRAMLOCKPULSEWIDTH TKN_EQUAL TKN_NUMBER + K_PROGRAMLOCKPULSEWIDTH TKN_EQUAL numexpr { current_part->programlockpulsewidth = $3->value.number; free_token($3); } | - K_PROGRAMLOCKPOLLTIMEOUT TKN_EQUAL TKN_NUMBER + K_PROGRAMLOCKPOLLTIMEOUT TKN_EQUAL numexpr { current_part->programlockpolltimeout = $3->value.number; free_token($3); } | - K_SYNCHCYCLES TKN_EQUAL TKN_NUMBER + K_SYNCHCYCLES TKN_EQUAL numexpr { current_part->synchcycles = $3->value.number; free_token($3); @@ -1076,50 +1120,45 @@ part_parm : K_HAS_JTAG TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_HAS_JTAG; + current_part->prog_modes |= PM_JTAG; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_HAS_JTAG; - + current_part->prog_modes &= ~PM_JTAG; free_token($3); } | K_HAS_DW TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_HAS_DW; + current_part->prog_modes |= PM_debugWIRE; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_HAS_DW; - + current_part->prog_modes &= ~PM_debugWIRE; free_token($3); } | K_HAS_PDI TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_HAS_PDI; + current_part->prog_modes |= PM_PDI; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_HAS_PDI; - + current_part->prog_modes &= ~PM_PDI; free_token($3); } | K_HAS_UPDI TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_HAS_UPDI; + current_part->prog_modes |= PM_UPDI; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_HAS_UPDI; - + current_part->prog_modes &= ~PM_UPDI; free_token($3); } | K_HAS_TPI TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_HAS_TPI; + current_part->prog_modes |= PM_TPI; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_HAS_TPI; - + current_part->prog_modes &= ~PM_TPI; free_token($3); } | @@ -1136,10 +1175,9 @@ part_parm : K_IS_AVR32 TKN_EQUAL yesno { if ($3->primary == K_YES) - current_part->flags |= AVRPART_AVR32; + current_part->prog_modes |= PM_aWire; else if ($3->primary == K_NO) - current_part->flags &= ~AVRPART_AVR32; - + current_part->prog_modes &= ~PM_aWire; free_token($3); } | @@ -1163,49 +1201,49 @@ part_parm : free_token($3); } | - K_IDR TKN_EQUAL TKN_NUMBER + K_IDR TKN_EQUAL numexpr { current_part->idr = $3->value.number; free_token($3); } | - K_RAMPZ TKN_EQUAL TKN_NUMBER + K_RAMPZ TKN_EQUAL numexpr { current_part->rampz = $3->value.number; free_token($3); } | - K_SPMCR TKN_EQUAL TKN_NUMBER + K_SPMCR TKN_EQUAL numexpr { current_part->spmcr = $3->value.number; free_token($3); } | - K_EECR TKN_EQUAL TKN_NUMBER + K_EECR TKN_EQUAL numexpr { current_part->eecr = $3->value.number; free_token($3); } | - K_MCU_BASE TKN_EQUAL TKN_NUMBER + K_MCU_BASE TKN_EQUAL numexpr { current_part->mcu_base = $3->value.number; free_token($3); } | - K_NVM_BASE TKN_EQUAL TKN_NUMBER + K_NVM_BASE TKN_EQUAL numexpr { current_part->nvm_base = $3->value.number; free_token($3); } | - K_OCD_BASE TKN_EQUAL TKN_NUMBER + K_OCD_BASE TKN_EQUAL numexpr { current_part->ocd_base = $3->value.number; free_token($3); } | - K_OCDREV TKN_EQUAL TKN_NUMBER + K_OCDREV TKN_EQUAL numexpr { current_part->ocdrev = $3->value.number; free_token($3); @@ -1255,14 +1293,6 @@ part_parm : } | -/* - K_EEPROM { current_mem = AVR_M_EEPROM; } - mem_specs | - - K_FLASH { current_mem = AVR_M_FLASH; } - mem_specs | -*/ - K_MEMORY TKN_STRING { /* select memory for extension or create if not there */ AVRMEM *mem = avr_locate_mem_noalias(current_part, $2->value.string); @@ -1273,6 +1303,7 @@ part_parm : } avr_add_mem_order($2->value.string); current_mem = mem; + current_strct = COMP_AVRMEM; free_token($2); } mem_specs @@ -1295,6 +1326,7 @@ part_parm : } cfg_pop_comms(); current_mem = NULL; + current_strct = COMP_AVRPART; } | K_MEMORY TKN_STRING TKN_EQUAL K_NULL { @@ -1306,6 +1338,7 @@ part_parm : free_token($2); cfg_pop_comms(); current_mem = NULL; + current_strct = COMP_AVRPART; } | opcode TKN_EQUAL string_list { { @@ -1355,20 +1388,25 @@ mem_specs : mem_spec : + TKN_COMPONENT TKN_EQUAL expr { + cfg_assign((char *) current_mem, COMP_AVRMEM, $1->value.comp, &$3->value); + free_token($1); + } | + K_PAGED TKN_EQUAL yesno { current_mem->paged = $3->primary == K_YES ? 1 : 0; free_token($3); } | - K_SIZE TKN_EQUAL TKN_NUMBER + K_SIZE TKN_EQUAL numexpr { current_mem->size = $3->value.number; free_token($3); } | - K_PAGE_SIZE TKN_EQUAL TKN_NUMBER + K_PAGE_SIZE TKN_EQUAL numexpr { int ps = $3->value.number; if (ps <= 0) @@ -1380,25 +1418,25 @@ mem_spec : free_token($3); } | - K_NUM_PAGES TKN_EQUAL TKN_NUMBER + K_NUM_PAGES TKN_EQUAL numexpr { current_mem->num_pages = $3->value.number; free_token($3); } | - K_OFFSET TKN_EQUAL TKN_NUMBER + K_OFFSET TKN_EQUAL numexpr { current_mem->offset = $3->value.number; free_token($3); } | - K_MIN_WRITE_DELAY TKN_EQUAL TKN_NUMBER + K_MIN_WRITE_DELAY TKN_EQUAL numexpr { current_mem->min_write_delay = $3->value.number; free_token($3); } | - K_MAX_WRITE_DELAY TKN_EQUAL TKN_NUMBER + K_MAX_WRITE_DELAY TKN_EQUAL numexpr { current_mem->max_write_delay = $3->value.number; free_token($3); @@ -1418,44 +1456,44 @@ mem_spec : free_token($4); } | - K_READBACK_P1 TKN_EQUAL TKN_NUMBER + K_READBACK_P1 TKN_EQUAL numexpr { current_mem->readback[0] = $3->value.number; free_token($3); } | - K_READBACK_P2 TKN_EQUAL TKN_NUMBER + K_READBACK_P2 TKN_EQUAL numexpr { current_mem->readback[1] = $3->value.number; free_token($3); } | - K_MODE TKN_EQUAL TKN_NUMBER + K_MODE TKN_EQUAL numexpr { current_mem->mode = $3->value.number; free_token($3); } | - K_DELAY TKN_EQUAL TKN_NUMBER + K_DELAY TKN_EQUAL numexpr { current_mem->delay = $3->value.number; free_token($3); } | - K_BLOCKSIZE TKN_EQUAL TKN_NUMBER + K_BLOCKSIZE TKN_EQUAL numexpr { current_mem->blocksize = $3->value.number; free_token($3); } | - K_READSIZE TKN_EQUAL TKN_NUMBER + K_READSIZE TKN_EQUAL numexpr { current_mem->readsize = $3->value.number; free_token($3); } | - K_POLLINDEX TKN_EQUAL TKN_NUMBER + K_POLLINDEX TKN_EQUAL numexpr { current_mem->pollindex = $3->value.number; free_token($3); diff --git a/src/developer_opts.c b/src/developer_opts.c index c8aa903c..c9efc7cf 100644 --- a/src/developer_opts.c +++ b/src/developer_opts.c @@ -63,7 +63,7 @@ static struct { const char *mcu, *var, *value; } ptinj[] = { // Add triples here, eg, {"ATmega328P", "mcuid", "999"}, - {NULL, NULL, NULL}, + {NULL, NULL, NULL}, }; static struct { @@ -74,8 +74,6 @@ static struct { }; - - // Return 0 if op code would encode (essentially) the same SPI command static int opcodecmp(const OPCODE *op1, const OPCODE *op2, int opnum) { char *opstr1, *opstr2, *p; @@ -134,7 +132,14 @@ static void printallopcodes(const AVRPART *p, const char *d, OPCODE * const *opa // Programming modes -static char *prog_modes(const AVRPART *p) { + +/* + * p->flags no longer used for programming modes, use p->prog_modes + * + + remove this comment in 2023 + +static char *prog_modes_str_flags(const AVRPART *p) { static char type[1024]; *type = 0; @@ -194,6 +199,38 @@ static char *prog_modes(const AVRPART *p) { return type + (*type == '|'); } + * + */ + + +static char *prog_modes_str(int pm) { + static char type[1024]; + + strcpy(type, "0"); + if(pm & PM_SPM) + strcat(type, " | PM_SPM"); + if(pm & PM_TPI) + strcat(type, " | PM_TPI"); + if(pm & PM_ISP) + strcat(type, " | PM_ISP"); + if(pm & PM_PDI) + strcat(type, " | PM_PDI"); + if(pm & PM_UPDI) + strcat(type, " | PM_UPDI"); + if(pm & PM_HVSP) + strcat(type, " | PM_HVSP"); + if(pm & PM_HVPP) + strcat(type, " | PM_HVPP"); + if(pm & PM_debugWIRE) + strcat(type, " | PM_debugWIRE"); + if(pm & PM_JTAG) + strcat(type, " | PM_JTAG"); + if(pm & PM_aWire) + strcat(type, " | PM_aWire"); + + return type + (type[1] == 0? 0: 4); +} + // Check whether address bits are where they should be in ISP commands static void checkaddr(int memsize, int pagesize, int opnum, const OPCODE *op, const AVRPART *p, const AVRMEM *m) { @@ -573,6 +610,10 @@ static void dev_part_strct(const AVRPART *p, bool tsv, const AVRPART *base, bool _if_partout_str(strcmp, descstr, desc); _if_partout_str(strcmp, cfg_escape(p->id), id); _if_partout_str(strcmp, cfg_escape(p->family_id), family_id); + _if_partout_str(intcmp, cfg_strdup("dev_part_strct()", prog_modes_str(p->prog_modes)), prog_modes); + _if_partout(intcmp, "%d", mcuid); + _if_partout(intcmp, "%d", n_interrupts); + _if_partout(intcmp, "%d", n_page_erase); _if_partout(intcmp, "%d", hvupdi_variant); _if_partout(intcmp, "0x%02x", stk500_devcode); _if_partout(intcmp, "0x%02x", avr910_devcode); @@ -595,13 +636,7 @@ static void dev_part_strct(const AVRPART *p, bool tsv, const AVRPART *base, bool if(tsv) { _partout("0x%04x", flags); } else { - _if_flagout(AVRPART_HAS_JTAG, has_jtag); - _if_flagout(AVRPART_HAS_DW, has_debugwire); - _if_flagout(AVRPART_HAS_PDI, has_pdi); - _if_flagout(AVRPART_HAS_UPDI, has_updi); - _if_flagout(AVRPART_HAS_TPI, has_tpi); _if_flagout(AVRPART_IS_AT90S1200, is_at90s1200); - _if_flagout(AVRPART_AVR32, is_avr32); _if_flagout(AVRPART_ALLOWFULLPAGEBITSTREAM, allowfullpagebitstream); _if_flagout(AVRPART_ENABLEPAGEPROGRAMMING, enablepageprogramming); _if_flagout(AVRPART_SERIALOK, serial); @@ -1032,7 +1067,7 @@ void dev_output_part_defs(char *partdesc) { nfuses, ok, p->flags, - prog_modes(p), + prog_modes_str(p->prog_modes), p->config_file, p->lineno ); } @@ -1051,14 +1086,14 @@ void dev_output_part_defs(char *partdesc) { // Print wait delays for AVR family parts if(waits) { - if(!(p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI | AVRPART_HAS_TPI | AVRPART_AVR32))) + if(p->prog_modes & PM_ISP) dev_info(".wd_chip_erase %.3f ms %s\n", p->chip_erase_delay/1000.0, p->desc); if(p->mem) { for(LNODEID lnm=lfirst(p->mem); lnm; lnm=lnext(lnm)) { AVRMEM *m = ldata(lnm); // Write delays not needed for read-only calibration and signature memories if(strcmp(m->desc, "calibration") && strcmp(m->desc, "signature")) { - if(!(p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI | AVRPART_HAS_TPI | AVRPART_AVR32))) { + if(p->prog_modes & PM_ISP) { if(m->min_write_delay == m->max_write_delay) dev_info(".wd_%s %.3f ms %s\n", m->desc, m->min_write_delay/1000.0, p->desc); else { @@ -1189,6 +1224,7 @@ static void dev_pgm_strct(const PROGRAMMER *pgm, bool tsv, const PROGRAMMER *bas _if_pgmout_str(strcmp, cfg_escape(pgm->desc), desc); if(!base || base->initpgm != pgm->initpgm) _pgmout_fmt("type", "\"%s\"", locate_programmer_type_id(pgm->initpgm)); + _if_pgmout_str(intcmp, cfg_strdup("dev_pgm_strct()", prog_modes_str(pgm->prog_modes)), prog_modes); if(!base || base->conntype != pgm->conntype) _pgmout_fmt("connection_type", "%s", connstr(pgm->conntype)); _if_pgmout(intcmp, "%d", baudrate); diff --git a/src/doc/avrdude.texi b/src/doc/avrdude.texi index cdc7602b..3bcade32 100644 --- a/src/doc/avrdude.texi +++ b/src/doc/avrdude.texi @@ -1694,28 +1694,32 @@ The format of the programmer definition is as follows: @smallexample programmer - parent # is a quoted string - id = [, [, ] ...] ; # are quoted strings - desc = ; # quoted string - type = "par" | "stk500" | ... ; # programmer type (see below for a list) - baudrate = ; # baudrate for serial ports - vcc = [, ... ] ; # pin number(s) - buff = [, ... ] ; # pin number(s) - reset = ; # pin number - sck = ; # pin number - mosi = ; # pin number - miso = ; # pin number - errled = ; # pin number - rdyled = ; # pin number - pgmled = ; # pin number - vfyled = ; # pin number - usbvid = ; # USB VID (Vendor ID) - usbpid = [, ...]; # USB PID (Product ID) - usbdev = ; # USB interface or other device info - usbvendor = ; # USB Vendor Name - usbproduct = ; # USB Product Name - usbsn = ; # USB Serial Number - ; + parent # optional parent + id = [, ... ] ; # are quoted strings + desc = ; # quoted string + type = ; # programmer type, quoted string + # supported types can be listed by "-c ?type" + prog_modes = PM_ @{ | PM_ @} # interfaces, eg, PM_SPM|PM_PDI + connection_type = parallel | serial | usb | spi + baudrate = ; # baudrate for avr910-programmer + vcc = [, ... ] ; # pin number(s) + buff = [, ... ] ; # pin number(s) + reset = ; # pin number + sck = ; # pin number + mosi = ; # pin number + miso = ; # pin number + errled = ; # pin number + rdyled = ; # pin number + pgmled = ; # pin number + vfyled = ; # pin number + usbvid = ; # USB VID (Vendor ID) + usbpid = [, ...] ; # USB PID (Product ID) + usbdev = ; # USB interface or other device info + usbvendor = ; # USB Vendor Name + usbproduct = ; # USB Product Name + usbsn = ; # USB Serial Number + hvupdi_support = [, , ... ] ; # UPDI HV Variants Support +; @end smallexample @noindent @@ -1723,13 +1727,29 @@ If a parent is specified, all settings of it (except its ids) are used for the n programmer. These values can be changed by new setting them for the new programmer. @noindent -To invert a bit in the pin definitions, use @code{= ~ }. +Known programming modes are +@itemize @bullet +@item @code{PM_SPM}: Bootloaders, self-programming with SPM opcodes or NVM Controllers +@item @code{PM_TPI}: Tiny Programming Interface (t4, t5, t9, t10, t20, t40, t102, t104) +@item @code{PM_ISP}: SPI programming for In-System Programming (almost all classic parts) +@item @code{PM_PDI}: Program and Debug Interface (xmega parts) +@item @code{PM_UPDI}: Unified Program and Debug Interface +@item @code{PM_HVSP}: High Voltage Serial Programming (some classic parts) +@item @code{PM_HVPP}: High Voltage Parallel Programming (most non-HVSP classic parts) +@item @code{PM_debugWIRE}: Simpler alternative to JTAG (a subset of HVPP/HVSP parts) +@item @code{PM_JTAG}: Joint Test Action Group standard (some classic parts, some xmega) +@item @code{PM_aWire}: AVR32 parts +@end itemize + +@noindent +To invert a bit in the pin definitions, use @code{= ~ }. To invert a pin list +(all pins get inverted) use @code{~ ( [, ... ] )}. @noindent Not all programmer types can handle a list of USB PIDs. @noindent -Following programmer types are currently implemented: +The following programmer types are currently implemented: @multitable @columnfractions .25 .6 @include programmer_types.texi @@ -1743,30 +1763,36 @@ Following programmer types are currently implemented: @smallexample part - id = ; # quoted string desc = ; # quoted string - family_id = ; # quoted string - has_jtag = ; # part has JTAG i/f - has_debugwire = ; # part has debugWire i/f - has_pdi = ; # part has PDI i/f - has_updi = ; # part has UPDI i/f - has_tpi = ; # part has TPI i/f - devicecode = ; # numeric + id = ; # quoted string + family_id = ; # quoted string, eg, "megaAVR" or "tinyAVR" + prog_modes = PM_ @{| PM_@} # interfaces, eg, PM_SPM|PM_ISP|PM_HVPP|PM_debugWIRE + mcuid = ; # unique id in 0..2039 for 8-bit AVRs + n_interrupts = ; # number of interrupts, used for vector bootloaders + n_page_erase = ; # if set, number of pages erased during NVM erase + hvupdi_variant = ; # numeric -1 (n/a) or 0..2 + devicecode = ; # deprecated, use stk500_devcode stk500_devcode = ; # numeric avr910_devcode = ; # numeric + has_jtag = ; # part has JTAG i/f (deprecated, use prog_modes) + has_debugwire = ; # part has debugWire i/f (deprecated, use prog_modes) + has_pdi = ; # part has PDI i/f (deprecated, use prog_modes) + has_updi = ; # part has UPDI i/f (deprecated, use prog_modes) + has_tpi = ; # part has TPI i/f (deprecated, use prog_modes) + is_avr32 = ; # AVR32 part (deprecated, use prog_modes) + is_at90s1200 = ; # AT90S1200 part signature = ; # signature bytes usbpid = ; # DFU USB PID - reset = dedicated | io; - retry_pulse = reset | sck; - pgm_enable = ; - chip_erase = ; chip_erase_delay = ; # micro-seconds + reset = dedicated | io ; + retry_pulse = reset | sck ; + chip_erase_delay = ; # chip erase delay (us) # STK500 parameters (parallel programming IO lines) pagel = ; # pin name in hex, i.e., 0xD7 bs2 = ; # pin name in hex, i.e., 0xA0 serial = ; # can use serial downloading - parallel = ; # can use par. programming - # STK500v2 parameters, to be taken from Atmel's XML files + parallel = ; # can use par. programming + # STK500v2 parameters, to be taken from Atmel's ATDF files timeout = ; stabdelay = ; cmdexedelay = ; @@ -1777,52 +1803,59 @@ part predelay = ; postdelay = ; pollmethod = ; - mode = ; - delay = ; - blocksize = ; - readsize = ; hvspcmdexedelay = ; - # STK500v2 HV programming parameters, from XML - pp_controlstack = , , ...; # PP only - hvsp_controlstack = , , ...; # HVSP only - hventerstabdelay = ; - progmodedelay = ; # PP only - latchcycles = ; - togglevtg = ; - poweroffdelay = ; - resetdelayms = ; - resetdelayus = ; - hvleavestabdelay = ; - resetdelay = ; - synchcycles = ; # HVSP only - chiperasepulsewidth = ; # PP only - chiperasepolltimeout = ; - chiperasetime = ; # HVSP only - programfusepulsewidth = ; # PP only - programfusepolltimeout = ; - programlockpulsewidth = ; # PP only - programlockpolltimeout = ; - # JTAG ICE mkII parameters, also from XML files + # STK500v2 HV programming parameters, from ATDFs + pp_controlstack = , , ... ; # PP only + hvsp_controlstack = , , ... ; # HVSP only + flash_instr = , , ; + eeprom_instr = , , ... ; + hventerstabdelay = ; + progmodedelay = ; # PP only + latchcycles = ; + togglevtg = ; + poweroffdelay = ; + resetdelayms = ; + resetdelayus = ; + hvleavestabdelay = ; + resetdelay = ; + synchcycles = ; # HVSP only + chiperasepulsewidth = ; # PP only + chiperasepolltimeout = ; + chiperasetime = ; # HVSP only + programfusepulsewidth = ; # PP only + programfusepolltimeout = ; + programlockpulsewidth = ; # PP only + programlockpolltimeout = ; + # JTAG ICE mkII parameters, also from ATDF files allowfullpagebitstream = ; enablepageprogramming = ; - idr = ; # IO addr of IDR (OCD) reg. - rampz = ; # IO addr of RAMPZ reg. - spmcr = ; # mem addr of SPMC[S]R reg. - eecr = ; # mem addr of EECR reg. - # (only when != 0x3F) - is_at90s1200 = ; # AT90S1200 part - is_avr32 = ; # AVR32 part + idr = ; # IO addr of IDR (OCD) reg + rampz = ; # IO addr of RAMPZ reg + spmcr = ; # mem addr of SPMC[S]R reg + eecr = ; # mem addr of EECR reg only when != 0x3f + mcu_base = ; + nvm_base = ; + ocd_base = ; + ocdrev = ; + pgm_enable = ; + chip_erase = ; memory - paged = ; # yes / no + paged = ; # yes/no (flash only, do not use for EEPROM) + offset = ; # memory offset size = ; # bytes page_size = ; # bytes num_pages = ; # numeric min_write_delay = ; # micro-seconds max_write_delay = ; # micro-seconds - readback_p1 = ; # byte value - readback_p2 = ; # byte value - pwroff_after_write = ; # yes / no + readback = ; # pair of byte values + readback_p1 = ; # byte value (first component) + readback_p2 = ; # byte value (second component) + pwroff_after_write = ; # yes/no + mode = ; # STK500 v2 file parameter from ATDF files + delay = ; # " + blocksize = ; # " + readsize = ; # " read = ; write = ; read_lo = ; @@ -1832,10 +1865,20 @@ part loadpage_lo = ; loadpage_hi = ; writepage = ; - ; - ; + ; +; @end smallexample +@noindent +If any of the above parameters are not specified, the default value +of 0 is used for numerics (except for @code{mcuid}, @code{hvupdi_variant} and @code{ocdrev}, +where the default value is -1) or the empty string @code{""} for string +values. If a required parameter is left empty, AVRDUDE will complain. +Almost all occurrences of numbers (with the exception of pin numbers +and where they are separated by space, eg, in signature and readback) +can also be given as simple expressions involving arithemtic and +bitwise operators. + @menu * Parent Part:: * Instruction Format:: @@ -1848,11 +1891,19 @@ part @subsection Parent Part @noindent -Parts can also inherit parameters from previously defined parts -using the following syntax. In this case specified integer and -string values override parameter values from the parent part. New -memory definitions are added to the definitions inherited from the -parent. +Parts can also inherit parameters from previously defined parts using +the following syntax. In this case specified integer and string values +override parameter values from the parent part. New memory definitions +are added to the definitions inherited from the parent. If, however, a +new memory definition refers to an existing one of the same name for +that part then, from v7.1, the existing memory definition is extended, +and components overwritten with new values. Assigning @code{NULL} +removes an inherited SPI instruction format, memory definition, control +stack, eeprom or flash instruction, eg, as in @code{memory "efuse" = +NULL;} + +@noindent +Example format for part inheritance: @smallexample part parent # quoted string @@ -1914,7 +1965,22 @@ write = "1 1 0 0 0 0 0 0 x x x x x x x x", @end smallexample +As the address bit numbers in the SPI opcodes are highly systematic, they +don't really need to be specified. A compact version of the format +specification neither uses bit-numbers for address lines nor spaces. If such +a string is longer than 7 characters, then the characters @code{0}, @code{1}, +@code{x}, @code{a}, @code{i} and @code{o} will be recognised as the +corresponding bit, whilst any of the characters @code{.}, @code{-}, @code{_} +or @code{/} can act as arbitrary visual separators, which are ignored. +Examples: +@smallexample + + loadpage_lo = "0100.0000--000x.xxxx--xxaa.aaaa--iiii.iiii"; + + loadpage_lo = "0100.0000", "000x.xxxx", "xxaa.aaaa", "iiii.iiii"; + +@end smallexample @c @c Node diff --git a/src/fileio.c b/src/fileio.c index 52e9afef..d28a4bfd 100644 --- a/src/fileio.c +++ b/src/fileio.c @@ -778,7 +778,7 @@ static int elf_mem_limits(AVRMEM *mem, struct avrpart * p, { int rv = 0; - if (p->flags & AVRPART_AVR32) { + if (p->prog_modes & PM_aWire) { // AVR32 if (strcmp(mem->desc, "flash") == 0) { *lowbound = 0x80000000; *highbound = 0xffffffff; @@ -850,7 +850,7 @@ static int elf2b(char * infile, FILE * inf, * sections out of an ELF file that contains section data for more * than one sub-segment. */ - if ((p->flags & AVRPART_HAS_PDI) != 0 && + if ((p->prog_modes & PM_PDI) != 0 && (strcmp(mem->desc, "boot") == 0 || strcmp(mem->desc, "application") == 0 || strcmp(mem->desc, "apptable") == 0)) { @@ -893,7 +893,7 @@ static int elf2b(char * infile, FILE * inf, const char *endianname; unsigned char endianess; - if (p->flags & AVRPART_AVR32) { + if (p->prog_modes & PM_aWire) { // AVR32 endianess = ELFDATA2MSB; endianname = "little"; } else { @@ -923,7 +923,7 @@ static int elf2b(char * infile, FILE * inf, const char *mname; uint16_t machine; - if (p->flags & AVRPART_AVR32) { + if (p->prog_modes & PM_aWire) { machine = EM_AVR32; mname = "AVR32"; } else { @@ -1383,14 +1383,7 @@ int fileio_setparms(int op, struct fioparms * fp, * AVR32 devices maintain their load offset within the file itself, * but AVRDUDE maintains all memory images 0-based. */ - if ((p->flags & AVRPART_AVR32) != 0) - { - fp->fileoffset = m->offset; - } - else - { - fp->fileoffset = 0; - } + fp->fileoffset = p->prog_modes & PM_aWire? m->offset: 0; return 0; } diff --git a/src/flip1.c b/src/flip1.c index dbddfaf0..a57f7259 100644 --- a/src/flip1.c +++ b/src/flip1.c @@ -239,7 +239,7 @@ int flip1_initialize(const PROGRAMMER *pgm, const AVRPART *part) { } else { pid = part->usbpid; } - if (!ovsigck && (part->flags & AVRPART_HAS_PDI)) { + if (!ovsigck && (part->prog_modes & PM_PDI)) { avrdude_message(MSG_INFO, "%s: \"flip1\" (FLIP protocol version 1) is for AT90USB* and ATmega*U* devices.\n" "%s For Xmega devices, use \"flip2\".\n" "%s (Use -F to bypass this check.)\n", diff --git a/src/flip2.c b/src/flip2.c index a26da242..2925030c 100644 --- a/src/flip2.c +++ b/src/flip2.c @@ -234,7 +234,7 @@ int flip2_initialize(const PROGRAMMER *pgm, const AVRPART *part) { pid = part->usbpid; } - if (!ovsigck && !(part->flags & AVRPART_HAS_PDI)) { + if (!ovsigck && !(part->prog_modes & PM_PDI)) { avrdude_message(MSG_INFO, "%s: \"flip2\" (FLIP protocol version 2) is for Xmega devices.\n" "%s For AT90USB* or ATmega*U* devices, use \"flip1\".\n" "%s (Use -F to bypass this check.)\n", diff --git a/src/ft245r.c b/src/ft245r.c index 9048cc2f..a44e19b8 100644 --- a/src/ft245r.c +++ b/src/ft245r.c @@ -343,7 +343,7 @@ static int ft245r_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char cmd[4] = {0,0,0,0}; unsigned char res[4]; - if (p->flags & AVRPART_HAS_TPI) + if (p->prog_modes & PM_TPI) return avr_tpi_chip_erase(pgm, p); if (p->op[AVR_OP_CHIP_ERASE] == NULL) { @@ -502,7 +502,7 @@ static int ft245r_program_enable(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char res[4]; int i; - if (p->flags & AVRPART_HAS_TPI) + if (p->prog_modes & PM_TPI) return avr_tpi_program_enable(pgm, p, TPIPCR_GT_0b); if (p->op[AVR_OP_PGM_ENABLE] == NULL) { @@ -565,7 +565,7 @@ static int ft245r_initialize(const PROGRAMMER *pgm, const AVRPART *p) { */ ft245r_usleep(pgm, 20000); // 20ms - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { bool io_link_ok = true; uint8_t byte; int i; diff --git a/src/jtag3.c b/src/jtag3.c index 94b2b695..52cbac40 100644 --- a/src/jtag3.c +++ b/src/jtag3.c @@ -1064,19 +1064,19 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { if (pgm->flag & PGM_FL_IS_DW) { ifname = "debugWire"; - if (p->flags & AVRPART_HAS_DW) + if (p->prog_modes & PM_debugWIRE) conn = PARM3_CONN_DW; } else if (pgm->flag & PGM_FL_IS_PDI) { ifname = "PDI"; - if (p->flags & AVRPART_HAS_PDI) + if (p->prog_modes & PM_PDI) conn = PARM3_CONN_PDI; } else if (pgm->flag & PGM_FL_IS_UPDI) { ifname = "UPDI"; - if (p->flags & AVRPART_HAS_UPDI) + if (p->prog_modes & PM_UPDI) conn = PARM3_CONN_UPDI; } else { ifname = "JTAG"; - if (p->flags & AVRPART_HAS_JTAG) + if (p->prog_modes & PM_JTAG) conn = PARM3_CONN_JTAG; } @@ -1086,11 +1086,11 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { return -1; } - if (p->flags & AVRPART_HAS_PDI) + if (p->prog_modes & PM_PDI) parm[0] = PARM3_ARCH_XMEGA; - else if (p->flags & AVRPART_HAS_UPDI) + else if (p->prog_modes & PM_UPDI) parm[0] = PARM3_ARCH_UPDI; - else if (p->flags & AVRPART_HAS_DW) + else if (p->prog_modes & PM_debugWIRE) parm[0] = PARM3_ARCH_TINY; else parm[0] = PARM3_ARCH_MEGA; @@ -1108,7 +1108,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { if (conn == PARM3_CONN_PDI || conn == PARM3_CONN_UPDI) PDATA(pgm)->set_sck = jtag3_set_sck_xmega_pdi; else if (conn == PARM3_CONN_JTAG) { - if (p->flags & AVRPART_HAS_PDI) + if (p->prog_modes & PM_PDI) PDATA(pgm)->set_sck = jtag3_set_sck_xmega_jtag; else PDATA(pgm)->set_sck = jtag3_set_sck_mega_jtag; @@ -1137,7 +1137,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { } /* set device descriptor data */ - if ((p->flags & AVRPART_HAS_PDI)) + if ((p->prog_modes & PM_PDI)) { struct xmega_device_desc xd; LNODEID ln; @@ -1182,7 +1182,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { if (jtag3_setparm(pgm, SCOPE_AVR, 2, PARM3_DEVICEDESC, (unsigned char *)&xd, sizeof xd) < 0) return -1; } - else if ((p->flags & AVRPART_HAS_UPDI)) + else if ((p->prog_modes & PM_UPDI)) { struct updi_device_desc xd; LNODEID ln; @@ -1247,7 +1247,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { // Generate UPDI high-voltage pulse if user asks for it and hardware supports it LNODEID support; - if (p->flags & AVRPART_HAS_UPDI && + if (p->prog_modes & PM_UPDI && PDATA(pgm)->use_hvupdi == true && p->hvupdi_variant != HV_UPDI_VARIANT_1) { parm[0] = PARM3_UPDI_HV_NONE; @@ -1332,7 +1332,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { int ocdrev; /* lacking a proper definition, guess the OCD revision */ - if (p->flags & AVRPART_HAS_DW) + if (p->prog_modes & PM_debugWIRE) ocdrev = 1; /* exception: ATtiny13, 2313, 4313 */ else if (flashsize > 128 * 1024) ocdrev = 4; @@ -1376,7 +1376,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { } if (use_ext_reset > 1) { - if(strcmp(pgm->type, "JTAGICE3") == 0 && p->flags & AVRPART_HAS_JTAG) + if(strcmp(pgm->type, "JTAGICE3") == 0 && (p->prog_modes & PM_JTAG)) avrdude_message(MSG_INFO, "%s: JTAGEN fuse disabled?\n", progname); return -1; } @@ -1394,7 +1394,7 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { * doesn't apply here anyway), the response is just RSP_OK. */ if (resp[1] == RSP3_DATA && status >= 7) { - if (p->flags & AVRPART_HAS_UPDI) { + if (p->prog_modes & PM_UPDI) { /* Partial Family_ID has been returned */ avrdude_message(MSG_NOTICE, "%s: Partial Family_ID returned: \"%c%c%c%c\"\n", progname, resp[3], resp[4], resp[5], resp[6]); @@ -1408,11 +1408,8 @@ static int jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { free(resp); PDATA(pgm)->boot_start = ULONG_MAX; - if ((p->flags & AVRPART_HAS_PDI)) { - /* - * Find out where the border between application and boot area - * is. - */ + if (p->prog_modes & PM_PDI) { + // Find the border between application and boot area AVRMEM *bootmem = avr_locate_mem(p, "boot"); AVRMEM *flashmem = avr_locate_mem(p, "flash"); if (bootmem == NULL || flashmem == NULL) { @@ -1690,7 +1687,7 @@ static int jtag3_page_erase(const PROGRAMMER *pgm, const AVRPART *p, const AVRME avrdude_message(MSG_NOTICE2, "%s: jtag3_page_erase(.., %s, 0x%x)\n", progname, m->desc, addr); - if (!(p->flags & AVRPART_HAS_PDI)) { + if (!(p->prog_modes & PM_PDI)) { avrdude_message(MSG_INFO, "%s: jtag3_page_erase: not an Xmega device\n", progname); return -1; @@ -1764,7 +1761,7 @@ static int jtag3_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const AVRM if (strcmp(m->desc, "flash") == 0) { PDATA(pgm)->flash_pageaddr = (unsigned long)-1L; cmd[3] = jtag3_memtype(pgm, p, addr); - if (p->flags & AVRPART_HAS_PDI) + if (p->prog_modes & PM_PDI) /* dynamically decide between flash/boot memtype */ dynamic_memtype = 1; } else if (strcmp(m->desc, "eeprom") == 0) { @@ -1783,14 +1780,14 @@ static int jtag3_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const AVRM free(cmd); return n_bytes; } - cmd[3] = ( p->flags & AVRPART_HAS_PDI || p->flags & AVRPART_HAS_UPDI ) ? MTYPE_EEPROM_XMEGA : MTYPE_EEPROM_PAGE; + cmd[3] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM_XMEGA: MTYPE_EEPROM_PAGE; PDATA(pgm)->eeprom_pageaddr = (unsigned long)-1L; } else if (strcmp(m->desc, "usersig") == 0 || strcmp(m->desc, "userrow") == 0) { cmd[3] = MTYPE_USERSIG; } else if (strcmp(m->desc, "boot") == 0) { cmd[3] = MTYPE_BOOT_FLASH; - } else if ( p->flags & AVRPART_HAS_PDI || p->flags & AVRPART_HAS_UPDI ) { + } else if (p->prog_modes & (PM_PDI | PM_UPDI)) { cmd[3] = MTYPE_FLASH; } else { cmd[3] = MTYPE_SPM; @@ -1868,11 +1865,11 @@ static int jtag3_paged_load(const PROGRAMMER *pgm, const AVRPART *p, const AVRME if (strcmp(m->desc, "flash") == 0) { cmd[3] = jtag3_memtype(pgm, p, addr); - if (p->flags & AVRPART_HAS_PDI) + if (p->prog_modes & PM_PDI) /* dynamically decide between flash/boot memtype */ dynamic_memtype = 1; } else if (strcmp(m->desc, "eeprom") == 0) { - cmd[3] = ( p->flags & AVRPART_HAS_PDI || p->flags & AVRPART_HAS_UPDI ) ? MTYPE_EEPROM : MTYPE_EEPROM_PAGE; + cmd[3] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM: MTYPE_EEPROM_PAGE; if (pgm->flag & PGM_FL_IS_DW) return -1; } else if (strcmp(m->desc, "prodsig") == 0) { @@ -1882,9 +1879,9 @@ static int jtag3_paged_load(const PROGRAMMER *pgm, const AVRPART *p, const AVRME cmd[3] = MTYPE_USERSIG; } else if (strcmp(m->desc, "boot") == 0) { cmd[3] = MTYPE_BOOT_FLASH; - } else if ( p->flags & AVRPART_HAS_PDI ) { + } else if (p->prog_modes & PM_PDI) { cmd[3] = MTYPE_FLASH; - } else if ( p->flags & AVRPART_HAS_UPDI ) { + } else if (p->prog_modes & PM_UPDI) { cmd[3] = MTYPE_SRAM; } else { cmd[3] = MTYPE_SPM; @@ -1949,7 +1946,7 @@ static int jtag3_read_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM cmd[1] = CMD3_READ_MEMORY; cmd[2] = 0; - cmd[3] = ( p->flags & AVRPART_HAS_PDI || p->flags & AVRPART_HAS_UPDI ) ? MTYPE_FLASH : MTYPE_FLASH_PAGE; + cmd[3] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_FLASH: MTYPE_FLASH_PAGE; if (avr_mem_is_flash_type(mem)) { addr += mem->offset & (512 * 1024 - 1); /* max 512 KiB flash */ pagesize = PDATA(pgm)->flash_pagesize; @@ -1957,7 +1954,7 @@ static int jtag3_read_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM paddr_ptr = &PDATA(pgm)->flash_pageaddr; cache_ptr = PDATA(pgm)->flash_pagecache; } else if (avr_mem_is_eeprom_type(mem)) { - if ( (pgm->flag & PGM_FL_IS_DW) || ( p->flags & AVRPART_HAS_PDI ) || ( p->flags & AVRPART_HAS_UPDI ) ) { + if ( (pgm->flag & PGM_FL_IS_DW) || (p->prog_modes & PM_PDI) || (p->prog_modes & PM_UPDI) ) { cmd[3] = MTYPE_EEPROM; } else { cmd[3] = MTYPE_EEPROM_PAGE; @@ -1987,7 +1984,7 @@ static int jtag3_read_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM unsupp = 1; } else if (matches(mem->desc, "fuse")) { cmd[3] = MTYPE_FUSE_BITS; - if (!(p->flags & AVRPART_HAS_UPDI)) + if (!(p->prog_modes & PM_UPDI)) addr = mem->offset & 7; } else if (strcmp(mem->desc, "usersig") == 0 || strcmp(mem->desc, "userrow") == 0) { @@ -2117,7 +2114,7 @@ static int jtag3_write_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRME cmd[0] = SCOPE_AVR; cmd[1] = CMD3_WRITE_MEMORY; cmd[2] = 0; - cmd[3] = ( p->flags & AVRPART_HAS_PDI || p->flags & AVRPART_HAS_UPDI ) ? MTYPE_FLASH : MTYPE_SPM; + cmd[3] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_FLASH: MTYPE_SPM; if (strcmp(mem->desc, "flash") == 0) { cache_ptr = PDATA(pgm)->flash_pagecache; pagesize = PDATA(pgm)->flash_pagesize; @@ -2149,7 +2146,7 @@ static int jtag3_write_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVRME unsupp = 1; } else if (matches(mem->desc, "fuse")) { cmd[3] = MTYPE_FUSE_BITS; - if (!(p->flags & AVRPART_HAS_UPDI)) + if (!(p->prog_modes & PM_UPDI)) addr = mem->offset & 7; } else if (strcmp(mem->desc, "usersig") == 0 || strcmp(mem->desc, "userrow") == 0) { @@ -2457,7 +2454,7 @@ static void jtag3_print_parms(const PROGRAMMER *pgm) { } static unsigned char jtag3_memtype(const PROGRAMMER *pgm, const AVRPART *p, unsigned long addr) { - if ( p->flags & AVRPART_HAS_PDI ) { + if (p->prog_modes & PM_PDI) { if (addr >= PDATA(pgm)->boot_start) return MTYPE_BOOT_FLASH; else @@ -2468,7 +2465,7 @@ static unsigned char jtag3_memtype(const PROGRAMMER *pgm, const AVRPART *p, unsi } static unsigned int jtag3_memaddr(const PROGRAMMER *pgm, const AVRPART *p, const AVRMEM *m, unsigned long addr) { - if ((p->flags & AVRPART_HAS_PDI) != 0) { + if (p->prog_modes & PM_PDI) { if (addr >= PDATA(pgm)->boot_start) /* * all memories but "flash" are smaller than boot_start anyway, so @@ -2479,10 +2476,9 @@ static unsigned int jtag3_memaddr(const PROGRAMMER *pgm, const AVRPART *p, const /* normal flash, or anything else */ return addr; } - /* - * Non-Xmega device. - */ - if (p->flags & AVRPART_HAS_UPDI) { + + // Non-Xmega device + if (p->prog_modes & PM_UPDI) { if (strcmp(m->desc, "flash") == 0) { return addr; } diff --git a/src/jtagmkI.c b/src/jtagmkI.c index a9b2dda8..73c58086 100644 --- a/src/jtagmkI.c +++ b/src/jtagmkI.c @@ -523,7 +523,7 @@ static int jtagmkI_initialize(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char cmd[1], resp[5]; unsigned char b; - if (!(p->flags & AVRPART_HAS_JTAG)) { + if (!(p->prog_modes & PM_JTAG)) { avrdude_message(MSG_INFO, "%s: jtagmkI_initialize(): part %s has no JTAG interface\n", progname, p->desc); return -1; diff --git a/src/jtagmkII.c b/src/jtagmkII.c index f4323799..e3f7d3d7 100644 --- a/src/jtagmkII.c +++ b/src/jtagmkII.c @@ -882,7 +882,7 @@ static int jtagmkII_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { int status, len; unsigned char buf[6], *resp, c; - if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) { + if (p->prog_modes & (PM_PDI | PM_UPDI)) { buf[0] = CMND_XMEGA_ERASE; buf[1] = XMEGA_ERASE_CHIP; memset(buf + 2, 0, 4); /* address of area to be erased */ @@ -893,7 +893,7 @@ static int jtagmkII_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { } avrdude_message(MSG_NOTICE2, "%s: jtagmkII_chip_erase(): Sending %schip erase command: ", progname, - (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))? "Xmega ": ""); + p->prog_modes & (PM_PDI | PM_UPDI)? "Xmega ": ""); jtagmkII_send(pgm, buf, len); status = jtagmkII_recv(pgm, &resp); @@ -919,7 +919,7 @@ static int jtagmkII_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { return -1; } - if (!(p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) + if (!(p->prog_modes & (PM_PDI | PM_UPDI))) pgm->initialize(pgm, p); return 0; @@ -966,7 +966,7 @@ static void jtagmkII_set_devdescr(const PROGRAMMER *pgm, const AVRPART *p) { u32_to_b4(sendbuf.dd.ulFlashSize, m->size); u16_to_b2(sendbuf.dd.uiFlashPageSize, m->page_size); u16_to_b2(sendbuf.dd.uiFlashpages, m->size / m->page_size); - if (p->flags & AVRPART_HAS_DW) { + if (p->prog_modes & PM_debugWIRE) { memcpy(sendbuf.dd.ucFlashInst, p->flash_instr, FLASH_INSTR_SIZE); memcpy(sendbuf.dd.ucEepromInst, p->eeprom_instr, EEPROM_INSTR_SIZE); } @@ -975,7 +975,7 @@ static void jtagmkII_set_devdescr(const PROGRAMMER *pgm, const AVRPART *p) { } } sendbuf.dd.ucCacheType = - (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))? 0x02 /* ATxmega */: 0x00; + p->prog_modes & (PM_PDI | PM_UPDI)? 0x02 /* ATxmega */: 0x00; avrdude_message(MSG_NOTICE2, "%s: jtagmkII_set_devdescr(): " "Sending set device descriptor command: ", @@ -1290,8 +1290,8 @@ static int jtagmkII_initialize(const PROGRAMMER *pgm, const AVRPART *p) { const char *ifname; /* Abort and print error if programmer does not support the target microcontroller */ - if ((strncmp(pgm->type, "JTAGMKII_UPDI", strlen("JTAGMKII_UPDI")) == 0 && !(p->flags & AVRPART_HAS_UPDI)) || - (strncmp(ldata(lfirst(pgm->id)), "jtagmkII", strlen("jtagmkII")) == 0 && p->flags & AVRPART_HAS_UPDI)) { + if ((strncmp(pgm->type, "JTAGMKII_UPDI", strlen("JTAGMKII_UPDI")) == 0 && !(p->prog_modes & PM_UPDI)) || + (strncmp(ldata(lfirst(pgm->id)), "jtagmkII", strlen("jtagmkII")) == 0 && (p->prog_modes & PM_UPDI))) { avrdude_message(MSG_INFO, "ERROR: programmer %s does not support target %s\n\n", ldata(lfirst(pgm->id)), p->desc); return -1; @@ -1300,15 +1300,15 @@ static int jtagmkII_initialize(const PROGRAMMER *pgm, const AVRPART *p) { ok = 0; if (pgm->flag & PGM_FL_IS_DW) { ifname = "debugWire"; - if (p->flags & AVRPART_HAS_DW) + if (p->prog_modes & PM_debugWIRE) ok = 1; } else if (pgm->flag & PGM_FL_IS_PDI) { ifname = "PDI"; - if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) + if (p->prog_modes & (PM_PDI | PM_UPDI)) ok = 1; } else { ifname = "JTAG"; - if (p->flags & AVRPART_HAS_JTAG) + if (p->prog_modes & PM_JTAG) ok = 1; } @@ -1350,24 +1350,21 @@ static int jtagmkII_initialize(const PROGRAMMER *pgm, const AVRPART *p) { * mode from JTAG to JTAG_XMEGA. */ if ((pgm->flag & PGM_FL_IS_JTAG) && - (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) { + (p->prog_modes & (PM_PDI | PM_UPDI))) { if (jtagmkII_getsync(pgm, EMULATOR_MODE_JTAG_XMEGA) < 0) return -1; } /* * Must set the device descriptor before entering programming mode. */ - if (PDATA(pgm)->fwver >= 0x700 && (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) != 0) + if (PDATA(pgm)->fwver >= 0x700 && (p->prog_modes & (PM_PDI | PM_UPDI)) != 0) jtagmkII_set_xmega_params(pgm, p); else jtagmkII_set_devdescr(pgm, p); PDATA(pgm)->boot_start = ULONG_MAX; - if ((p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) { - /* - * Find out where the border between application and boot area - * is. - */ + if ((p->prog_modes & (PM_PDI | PM_UPDI))) { + // Find the border between application and boot area AVRMEM *bootmem = avr_locate_mem(p, "boot"); AVRMEM *flashmem = avr_locate_mem(p, "flash"); if (bootmem == NULL || flashmem == NULL) { @@ -1405,7 +1402,7 @@ static int jtagmkII_initialize(const PROGRAMMER *pgm, const AVRPART *p) { } PDATA(pgm)->flash_pageaddr = PDATA(pgm)->eeprom_pageaddr = (unsigned long)-1L; - if (PDATA(pgm)->fwver >= 0x700 && (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) { + if (PDATA(pgm)->fwver >= 0x700 && (p->prog_modes & (PM_PDI | PM_UPDI))) { /* * Work around for * https://savannah.nongnu.org/bugs/index.php?37942 @@ -1422,7 +1419,7 @@ static int jtagmkII_initialize(const PROGRAMMER *pgm, const AVRPART *p) { return -1; } - if ((pgm->flag & PGM_FL_IS_JTAG) && !(p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) { + if ((pgm->flag & PGM_FL_IS_JTAG) && !(p->prog_modes & (PM_PDI | PM_UPDI))) { hfuse.desc = cache_string("hfuse"); if (jtagmkII_read_byte(pgm, p, &hfuse, 1, &b) < 0) return -1; @@ -1887,7 +1884,7 @@ static int jtagmkII_page_erase(const PROGRAMMER *pgm, const AVRPART *p, const AV avrdude_message(MSG_NOTICE2, "%s: jtagmkII_page_erase(.., %s, 0x%x)\n", progname, m->desc, addr); - if (!(p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI))) { + if (!(p->prog_modes & (PM_PDI | PM_UPDI))) { avrdude_message(MSG_INFO, "%s: jtagmkII_page_erase: not an Xmega device\n", progname); return -1; @@ -2002,7 +1999,7 @@ static int jtagmkII_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const A if (strcmp(m->desc, "flash") == 0) { PDATA(pgm)->flash_pageaddr = (unsigned long)-1L; cmd[1] = jtagmkII_memtype(pgm, p, addr); - if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) + if (p->prog_modes & (PM_PDI | PM_UPDI)) /* dynamically decide between flash/boot memtype */ dynamic_memtype = 1; } else if (strcmp(m->desc, "eeprom") == 0) { @@ -2021,14 +2018,14 @@ static int jtagmkII_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const A free(cmd); return n_bytes; } - cmd[1] = (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) ? MTYPE_EEPROM : MTYPE_EEPROM_PAGE; + cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM: MTYPE_EEPROM_PAGE; PDATA(pgm)->eeprom_pageaddr = (unsigned long)-1L; } else if (strcmp(m->desc, "usersig") == 0 || strcmp(m->desc, "userrow") == 0) { cmd[1] = MTYPE_USERSIG; } else if (strcmp(m->desc, "boot") == 0) { cmd[1] = MTYPE_BOOT_FLASH; - } else if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) { + } else if (p->prog_modes & (PM_PDI | PM_UPDI)) { cmd[1] = MTYPE_FLASH; } else { cmd[1] = MTYPE_SPM; @@ -2130,11 +2127,11 @@ static int jtagmkII_paged_load(const PROGRAMMER *pgm, const AVRPART *p, const AV cmd[0] = CMND_READ_MEMORY; if (strcmp(m->desc, "flash") == 0) { cmd[1] = jtagmkII_memtype(pgm, p, addr); - if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) + if (p->prog_modes & (PM_PDI | PM_UPDI)) /* dynamically decide between flash/boot memtype */ dynamic_memtype = 1; } else if (strcmp(m->desc, "eeprom") == 0) { - cmd[1] = (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) ? MTYPE_EEPROM : MTYPE_EEPROM_PAGE; + cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM: MTYPE_EEPROM_PAGE; if (pgm->flag & PGM_FL_IS_DW) return -1; } else if (strcmp(m->desc, "prodsig") == 0) { @@ -2144,7 +2141,7 @@ static int jtagmkII_paged_load(const PROGRAMMER *pgm, const AVRPART *p, const AV cmd[1] = MTYPE_USERSIG; } else if (strcmp(m->desc, "boot") == 0) { cmd[1] = MTYPE_BOOT_FLASH; - } else if (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) { + } else if (p->prog_modes & (PM_PDI | PM_UPDI)) { cmd[1] = MTYPE_FLASH; } else { cmd[1] = MTYPE_SPM; @@ -2230,14 +2227,14 @@ static int jtagmkII_read_byte(const PROGRAMMER *pgm, const AVRPART *p, const AVR unsupp = 0; addr += mem->offset; - cmd[1] = ( p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI) ) ? MTYPE_FLASH : MTYPE_FLASH_PAGE; + cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_FLASH: MTYPE_FLASH_PAGE; if (avr_mem_is_flash_type(mem)) { pagesize = PDATA(pgm)->flash_pagesize; paddr = addr & ~(pagesize - 1); paddr_ptr = &PDATA(pgm)->flash_pageaddr; cache_ptr = PDATA(pgm)->flash_pagecache; } else if (avr_mem_is_eeprom_type(mem)) { - if ( (pgm->flag & PGM_FL_IS_DW) || ( p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI) ) ) { + if ( (pgm->flag & PGM_FL_IS_DW) || (p->prog_modes & (PM_PDI | PM_UPDI)) ) { /* debugWire cannot use page access for EEPROM */ cmd[1] = MTYPE_EEPROM; } else { @@ -2404,7 +2401,7 @@ static int jtagmkII_write_byte(const PROGRAMMER *pgm, const AVRPART *p, const AV writedata = data; cmd[0] = CMND_WRITE_MEMORY; - cmd[1] = ( p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI) ) ? MTYPE_FLASH : MTYPE_SPM; + cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_FLASH: MTYPE_SPM; if (strcmp(mem->desc, "flash") == 0) { if ((addr & 1) == 1) { /* odd address = high byte */ @@ -2418,7 +2415,7 @@ static int jtagmkII_write_byte(const PROGRAMMER *pgm, const AVRPART *p, const AV if (pgm->flag & PGM_FL_IS_DW) unsupp = 1; } else if (strcmp(mem->desc, "eeprom") == 0) { - cmd[1] = ( p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI) ) ? MTYPE_EEPROM_XMEGA: MTYPE_EEPROM; + cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM_XMEGA: MTYPE_EEPROM; need_progmode = 0; PDATA(pgm)->eeprom_pageaddr = (unsigned long)-1L; } else if (strcmp(mem->desc, "lfuse") == 0) { @@ -2719,7 +2716,7 @@ static void jtagmkII_print_parms(const PROGRAMMER *pgm) { } static unsigned char jtagmkII_memtype(const PROGRAMMER *pgm, const AVRPART *p, unsigned long addr) { - if ( p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI) ) { + if (p->prog_modes & (PM_PDI | PM_UPDI)) { if (addr >= PDATA(pgm)->boot_start) return MTYPE_BOOT_FLASH; else @@ -2734,7 +2731,7 @@ static unsigned int jtagmkII_memaddr(const PROGRAMMER *pgm, const AVRPART *p, co * Xmega devices handled by V7+ firmware don't want to be told their * m->offset within the write memory command. */ - if (PDATA(pgm)->fwver >= 0x700 && (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_UPDI)) != 0) { + if (PDATA(pgm)->fwver >= 0x700 && (p->prog_modes & (PM_PDI | PM_UPDI))) { if (addr >= PDATA(pgm)->boot_start) /* * all memories but "flash" are smaller than boot_start anyway, so @@ -3572,7 +3569,7 @@ static int jtagmkII_paged_write32(const PROGRAMMER *pgm, const AVRPART *p, const } // Init SMC and set clocks - if(!(p->flags & FLAGS32_INIT_SMC)) { + if(!(PDATA(pgm)->flags32 & FLAGS32_INIT_SMC)) { status = jtagmkII_smc_init32(pgm); if(status != 0) {lineno = __LINE__; goto eRR;} // PLL 0 PDATA(pgm)->flags32 |= FLAGS32_INIT_SMC; diff --git a/src/lexer.l b/src/lexer.l index a69130d3..02fa6008 100644 --- a/src/lexer.l +++ b/src/lexer.l @@ -63,9 +63,9 @@ SIGN [+-] %% -{SIGN}?{DIGIT}+ { yylval = number(yytext); return TKN_NUMBER; } -{SIGN}?{DIGIT}+"."{DIGIT}* { yylval = number_real(yytext); return TKN_NUMBER_REAL; } -{SIGN}?"."{DIGIT}+ { yylval = number_real(yytext); return TKN_NUMBER_REAL; } +{DIGIT}+ { yylval = new_number(yytext); return TKN_NUMBER; /* sign is treated in grammar */ } +{SIGN}?{DIGIT}+"."{DIGIT}* { yylval = new_number_real(yytext); return TKN_NUMBER_REAL; } +{SIGN}?"."{DIGIT}+ { yylval = new_number_real(yytext); return TKN_NUMBER_REAL; } ["]([^"\\\n]|\\.|\\\n)*["] { char *str= cfg_strdup("lexer.l", yytext); @@ -73,12 +73,12 @@ SIGN [+-] size_t len = strlen(str); if(len) str[len-1] = 0; - yylval = string(str); + yylval = new_string(str); free(str); return TKN_STRING; } -0x{HEXDIGIT}+ { yylval = hexnumber(yytext); return TKN_NUMBER; } +0x{HEXDIGIT}+ { yylval = new_hexnumber(yytext); return TKN_NUMBER; } #\n#\ PROGRAMMER\ DEFINITIONS\n#\n+ { /* Record comments so far as prologue and skip */ cfg_capture_prologue(); @@ -121,6 +121,23 @@ SIGN [+-] } +prog_modes|mcuid|n_interrupts|n_page_erase { /* Components for assignment */ + Component_t *cp = cfg_comp_search(yytext, current_strct); + if(!cp) { + yyerror("Unknown component %s in %s", yytext, cfg_strct_name(current_strct)); + return YYERRCODE; + } + yylval = new_token(TKN_COMPONENT); + yylval->value.comp = cp; + ccap(); + return TKN_COMPONENT; +} + +PM_SPM|PM_TPI|PM_ISP|PM_PDI|PM_UPDI|PM_HVSP|PM_HVPP|PM_debugWIRE|PM_JTAG|PM_aWire { /* Constants */ + yylval = new_constant(yytext); + return TKN_NUMBER; +} + alias { yylval=NULL; return K_ALIAS; } allowfullpagebitstream { yylval=NULL; ccap(); return K_ALLOWFULLPAGEBITSTREAM; } avr910_devcode { yylval=NULL; ccap(); return K_AVR910_DEVCODE; } @@ -258,7 +275,17 @@ yes { yylval=new_token(K_YES); return K_YES; } "," { yylval = NULL; pyytext(); return TKN_COMMA; } "=" { yylval = NULL; pyytext(); return TKN_EQUAL; } ";" { yylval = NULL; pyytext(); return TKN_SEMI; } -"~" { yylval = NULL; pyytext(); return TKN_TILDE; } + +"|" { yylval = NULL; pyytext(); return OP_OR; } +"^" { yylval = NULL; pyytext(); return OP_XOR; } +"&" { yylval = NULL; pyytext(); return OP_AND; } +"+" { yylval = NULL; pyytext(); return OP_PLUS; } +"-" { yylval = NULL; pyytext(); return OP_MINUS; } +"*" { yylval = NULL; pyytext(); return OP_TIMES; } +"/" { yylval = NULL; pyytext(); return OP_DIVIDE; } +"%" { yylval = NULL; pyytext(); return OP_MODULO; } +"~" { yylval = NULL; pyytext(); return OP_TILDE; } + "(" { yylval = NULL; pyytext(); return TKN_LEFT_PAREN; } ")" { yylval = NULL; pyytext(); return TKN_RIGHT_PAREN; } diff --git a/src/libavrdude.h b/src/libavrdude.h index 9288b43b..3c7a6aec 100644 --- a/src/libavrdude.h +++ b/src/libavrdude.h @@ -169,6 +169,7 @@ enum ctl_stack_t { CTL_STACK_HVSP /* high voltage serial programming control stack */ }; + /* * serial programming instruction bit specifications */ @@ -183,19 +184,25 @@ typedef struct opcode { } OPCODE; -/* Any changes here, please also reflect in dev_part_strct() of developer_opts.c */ -#define AVRPART_SERIALOK 0x0001 /* part supports serial programming */ -#define AVRPART_PARALLELOK 0x0002 /* part supports parallel programming */ -#define AVRPART_PSEUDOPARALLEL 0x0004 /* part has pseudo parallel support */ -#define AVRPART_HAS_JTAG 0x0008 /* part has a JTAG i/f */ -#define AVRPART_ALLOWFULLPAGEBITSTREAM 0x0010 /* JTAG ICE mkII param. */ -#define AVRPART_ENABLEPAGEPROGRAMMING 0x0020 /* JTAG ICE mkII param. */ -#define AVRPART_HAS_DW 0x0040 /* part has a debugWire i/f */ -#define AVRPART_HAS_PDI 0x0080 /* part has PDI i/f rather than ISP (ATxmega) */ -#define AVRPART_AVR32 0x0100 /* part is in AVR32 family */ -#define AVRPART_HAS_TPI 0x0800 /* part has TPI i/f rather than ISP (ATtiny4/5/9/10) */ -#define AVRPART_IS_AT90S1200 0x1000 /* part is an AT90S1200 (needs special treatment) */ -#define AVRPART_HAS_UPDI 0x2000 /* part has UPDI i/f (AVR8X) */ +// Any changes here, please also reflect in dev_part_strct() of developer_opts.c +#define AVRPART_SERIALOK 1 // Part supports serial programming +#define AVRPART_PARALLELOK 2 // Part supports parallel programming +#define AVRPART_PSEUDOPARALLEL 4 // Part has pseudo parallel support +#define AVRPART_ALLOWFULLPAGEBITSTREAM 8 // JTAG ICE mkII param +#define AVRPART_ENABLEPAGEPROGRAMMING 16 // JTAG ICE mkII param +#define AVRPART_IS_AT90S1200 32 // Part is an AT90S1200, needs special treatment + +// Programming modes for parts and programmers: reflect changes in lexer.l, developer_opts.c and config.c +#define PM_SPM 1 // Bootloaders, self-programming with SPM opcodes or NVM Controllers +#define PM_TPI 2 // Tiny Programming Interface (t4, t5, t9, t10, t20, t40, t102, t104) +#define PM_ISP 4 // SPI programming for In-System Programming (almost all classic parts) +#define PM_PDI 8 // Program and Debug Interface (xmega parts) +#define PM_UPDI 16 // Unified Program and Debug Interface +#define PM_HVSP 32 // High Voltage Serial Programming (some classic parts) +#define PM_HVPP 64 // High Voltage Parallel Programming (most non-HVSP classic parts) +#define PM_debugWIRE 128 // Simpler alternative to JTAG (a subset of HVPP/HVSP parts) +#define PM_JTAG 256 // Joint Test Action Group standard (some classic parts, some xmega) +#define PM_aWire 512 // AVR32 parts #define HV_UPDI_VARIANT_0 0 /* Shared UPDI/GPIO/RESET pin, HV on UPDI pin (tinyAVR0/1/2)*/ #define HV_UPDI_VARIANT_1 1 /* Dedicated UPDI pin, no HV (megaAVR0/AVR-Dx) */ @@ -209,13 +216,24 @@ typedef struct opcode { #define TAG_ALLOCATED 1 /* memory byte is allocated */ -/* Any changes here, please also reflect in dev_part_strct() of developer_opts.c */ +/* + * Any changes in AVRPART or AVRMEM, please also ensure changes are made in + * - lexer.l + * - Either Component_t avr_comp[] of config.c or in config_gram.y + * - dev_part_strct() in developer_opts.c + * - avr_new_part() and/or avr_new_memtype() in avrpart.c for + * initialisation; note that all const char * must be initialised with "" + */ typedef struct avrpart { const char * desc; /* long part name */ const char * id; /* short part name */ LISTID comments; // Used by developer options -p*/[ASsr...] const char * parent_id; /* Used by developer options */ const char * family_id; /* family id in the SIB (avr8x) */ + int prog_modes; /* Programming interfaces, see #define PM_... */ + int mcuid; /* Unique id in 0..2039 for urclock programmer */ + int n_interrupts; /* Number of interrupts, used for vector bootloaders */ + int n_page_erase; /* If set, number of pages erased during NVM erase */ int hvupdi_variant; /* HV pulse on UPDI pin, no pin or RESET pin */ int stk500_devcode; /* stk500 device code */ int avr910_devcode; /* avr910 device code */ @@ -262,7 +280,7 @@ typedef struct avrpart { int programlockpulsewidth; /* stk500 v2 hv mode parameter */ int programlockpolltimeout; /* stk500 v2 hv mode parameter */ int synchcycles; /* stk500 v2 hv mode parameter */ - int hvspcmdexedelay; /* stk500 v2 xml file parameter */ + int hvspcmdexedelay; /* stk500 v2 hv mode file parameter */ unsigned char idr; /* JTAG ICE mkII XML file parameter */ unsigned char rampz; /* JTAG ICE mkII XML file parameter */ @@ -677,13 +695,21 @@ typedef enum { CONNTYPE_SPI } conntype_t; -/* Any changes here, please also reflect in dev_pgm_strct() of developer_opts.c */ +/* + * Any changes in PROGRAMMER, please also ensure changes are made in + * - lexer.l + * - Either Component_t avr_comp[] of config.c or config_gram.y + * - dev_pgm_strct() in developer_opts.c + * - pgm_new() in pgm.c for initialisation; note that all const char * must + * be initialised with "" + */ typedef struct programmer_t { LISTID id; const char *desc; void (*initpgm)(struct programmer_t *pgm); // Sets up the AVRDUDE programmer LISTID comments; // Used by developer options -c*/[ASsr...] const char *parent_id; // Used by developer options + int prog_modes; // Programming interfaces, see #define PM_... struct pindef_t pin[N_PINS]; conntype_t conntype; int baudrate; @@ -695,7 +721,7 @@ typedef struct programmer_t { const char *usbproduct; LISTID hvupdi_support; // List of UPDI HV variants the tool supports, see HV_UPDI_VARIANT_x - // Values below are not set by config_gram.y; make sure fd is first for dev_pgm_raw() + // Values below are not set by config_gram.y; ensure fd is first for dev_pgm_raw() union filedescriptor fd; char type[PGM_TYPELEN]; char port[PGM_PORTLEN]; diff --git a/src/linuxspi.c b/src/linuxspi.c index df57c7e6..512755e3 100644 --- a/src/linuxspi.c +++ b/src/linuxspi.c @@ -270,8 +270,8 @@ static void linuxspi_display(const PROGRAMMER* pgm, const char* p) { static int linuxspi_initialize(const PROGRAMMER *pgm, const AVRPART *p) { int tries, ret; - if (p->flags & AVRPART_HAS_TPI) { - /* We do not support tpi. This is a dedicated SPI thing */ + if (p->prog_modes & PM_TPI) { + /* We do not support TPI. This is a dedicated SPI thing */ avrdude_message(MSG_INFO, "%s: error: Programmer " LINUXSPI " does not support TPI\n", progname); return -1; } diff --git a/src/main.c b/src/main.c index 51dbc879..1e39fdbf 100644 --- a/src/main.c +++ b/src/main.c @@ -924,7 +924,7 @@ int main(int argc, char * argv []) for (ln=lfirst(updates); ln; ln=lnext(ln)) { upd = ldata(ln); if (upd->memtype == NULL) { - const char *mtype = (p->flags & AVRPART_HAS_PDI)? "application": "flash"; + const char *mtype = p->prog_modes & PM_PDI? "application": "flash"; avrdude_message(MSG_NOTICE2, "%s: defaulting memtype in -U %c:%s option to \"%s\"\n", progname, (upd->op == DEVICE_READ)? 'r': (upd->op == DEVICE_WRITE)? 'w': 'v', @@ -1062,7 +1062,7 @@ int main(int argc, char * argv []) * against 0xffffff / 0x000000 should ensure that the signature bytes * are valid. */ - if(!(p->flags & AVRPART_AVR32)) { + if(!(p->prog_modes & PM_aWire)) { // not AVR32 int attempt = 0; int waittime = 10000; /* 10 ms */ @@ -1071,7 +1071,7 @@ int main(int argc, char * argv []) if (init_ok) { rc = avr_signature(pgm, p); if (rc != LIBAVRDUDE_SUCCESS) { - if ((rc == LIBAVRDUDE_SOFTFAIL) && (p->flags & AVRPART_HAS_UPDI) && (attempt < 1)) { + if (rc == LIBAVRDUDE_SOFTFAIL && (p->prog_modes & PM_UPDI) && attempt < 1) { attempt++; if (pgm->read_sib) { // Read SIB and compare FamilyID @@ -1193,8 +1193,7 @@ int main(int argc, char * argv []) } if (uflags & UF_AUTO_ERASE) { - if ((p->flags & AVRPART_HAS_PDI) && pgm->page_erase != NULL && - lsize(updates) > 0) { + if ((p->prog_modes & PM_PDI) && pgm->page_erase && lsize(updates) > 0) { if (quell_progress < 2) { avrdude_message(MSG_INFO, "%s: NOTE: Programmer supports page erase for Xmega devices.\n" "%sEach page will be erased before programming it, but no chip erase is performed.\n" @@ -1203,7 +1202,7 @@ int main(int argc, char * argv []) } } else { AVRMEM * m; - const char *memname = (p->flags & AVRPART_HAS_PDI)? "application": "flash"; + const char *memname = p->prog_modes & PM_PDI? "application": "flash"; uflags &= ~UF_AUTO_ERASE; for (ln=lfirst(updates); ln; ln=lnext(ln)) { diff --git a/src/stk500v2.c b/src/stk500v2.c index bdff4612..37fe2314 100644 --- a/src/stk500v2.c +++ b/src/stk500v2.c @@ -1130,8 +1130,7 @@ retry: break; case PGMTYPE_JTAGICE3: - if (buf[1] == STATUS_CMD_FAILED && - (p->flags & AVRPART_HAS_DW) != 0) { + if (buf[1] == STATUS_CMD_FAILED && (p->prog_modes & PM_debugWIRE)) { unsigned char cmd[4], *resp; /* Try debugWIRE, and MONCON_DISABLE */ @@ -1239,16 +1238,13 @@ static int stk500v2_initialize(const PROGRAMMER *pgm, const AVRPART *p) { if ((PDATA(pgm)->pgmtype == PGMTYPE_STK600 || PDATA(pgm)->pgmtype == PGMTYPE_AVRISP_MKII || PDATA(pgm)->pgmtype == PGMTYPE_JTAGICE_MKII) != 0 - && (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_TPI)) != 0) { + && (p->prog_modes & (PM_PDI | PM_TPI)) != 0) { /* * This is an ATxmega device, must use XPROG protocol for the * remaining actions. */ - if ((p->flags & AVRPART_HAS_PDI) != 0) { - /* - * Find out where the border between application and boot area - * is. - */ + if (p->prog_modes & PM_PDI) { + // Find the border between application and boot area AVRMEM *bootmem = avr_locate_mem(p, "boot"); AVRMEM *flashmem = avr_locate_mem(p, "flash"); if (bootmem == NULL || flashmem == NULL) { @@ -1320,8 +1316,8 @@ static int stk500v2_jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { LNODEID ln; AVRMEM * m; - if ((p->flags & AVRPART_HAS_PDI) || - (p->flags & AVRPART_HAS_TPI)) { + // FIXME: condition below looks fishy, suspect the code wants !(p->prog_modes & (PM_debugWIRE | PM_JTAG)) + if (p->prog_modes & (PM_PDI | PM_TPI)) { avrdude_message(MSG_INFO, "%s: jtag3_initialize(): part %s has no ISP interface\n", progname, p->desc); return -1; @@ -1330,7 +1326,7 @@ static int stk500v2_jtag3_initialize(const PROGRAMMER *pgm, const AVRPART *p) { PROGRAMMER *pgmcp = pgm_dup(pgm); pgmcp->cookie = PDATA(pgm)->chained_pdata; - if (p->flags & AVRPART_HAS_DW) + if (p->prog_modes & PM_debugWIRE) parm[0] = PARM3_ARCH_TINY; else parm[0] = PARM3_ARCH_MEGA; @@ -1574,7 +1570,7 @@ static void stk500v2_enable(PROGRAMMER *pgm, const AVRPART *p) { if((PDATA(pgm)->pgmtype == PGMTYPE_STK600 || PDATA(pgm)->pgmtype == PGMTYPE_AVRISP_MKII || PDATA(pgm)->pgmtype == PGMTYPE_JTAGICE_MKII) != 0 - && (p->flags & (AVRPART_HAS_PDI | AVRPART_HAS_TPI)) != 0) { + && (p->prog_modes & (PM_PDI | PM_TPI)) != 0) { stk600_setup_xprog(pgm); } else { stk600_setup_isp(pgm); @@ -3689,7 +3685,7 @@ static int stk600_xprog_program_enable(const PROGRAMMER *pgm, const AVRPART *p) AVRMEM *mem = NULL; int use_tpi; - use_tpi = (p->flags & AVRPART_HAS_TPI) != 0; + use_tpi = (p->prog_modes & PM_TPI) != 0; if (!use_tpi) { if (p->nvm_base == 0) { @@ -3825,7 +3821,7 @@ static int stk600_xprog_write_byte(const PROGRAMMER *pgm, const AVRPART *p, cons memcode = XPRG_MEM_TYPE_LOCKBITS; } else if (strncmp(mem->desc, "fuse", strlen("fuse")) == 0) { memcode = XPRG_MEM_TYPE_FUSE; - if (p->flags & AVRPART_HAS_TPI) + if (p->prog_modes & PM_TPI) /* * TPI devices need a mystic erase prior to writing their * fuses. @@ -3855,7 +3851,7 @@ static int stk600_xprog_write_byte(const PROGRAMMER *pgm, const AVRPART *p, cons } } - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { /* * Some TPI memories (configuration aka. fuse) require a * larger write block size. We record that as a blocksize in @@ -4217,7 +4213,7 @@ static int stk600_xprog_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { AVRMEM *mem; unsigned int addr = 0; - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { if ((mem = avr_locate_mem(p, "flash")) == NULL) { avrdude_message(MSG_INFO, "%s: stk600_xprog_chip_erase(): no FLASH definition found for TPI device\n", progname); diff --git a/src/usbasp.c b/src/usbasp.c index 6a0e00f0..65750dda 100644 --- a/src/usbasp.c +++ b/src/usbasp.c @@ -674,7 +674,7 @@ static int usbasp_initialize(const PROGRAMMER *pgm, const AVRPART *p) { else pdata->capabilities = 0; - pdata->use_tpi = (pdata->capabilities & USBASP_CAP_TPI) && (p->flags & AVRPART_HAS_TPI); + pdata->use_tpi = (pdata->capabilities & USBASP_CAP_TPI) && (p->prog_modes & PM_TPI); // query support for 3 MHz SCK in UsbAsp-flash firmware // https://github.com/nofeletru/UsbAsp-flash pdata->sck_3mhz = ((pdata->capabilities & USBASP_CAP_3MHZ) != 0) ? 1 :0; diff --git a/src/usbtiny.c b/src/usbtiny.c index 5cdaad4a..2e319318 100644 --- a/src/usbtiny.c +++ b/src/usbtiny.c @@ -454,7 +454,7 @@ static int usbtiny_initialize (const PROGRAMMER *pgm, const AVRPART *p ) { // Let the device wake up. usleep(50000); - if (p->flags & AVRPART_HAS_TPI) { + if (p->prog_modes & PM_TPI) { /* Since there is a single TPIDATA line, MOSI and MISO must be linked together through a 1kOhm resistor. Verify that everything we send on MOSI gets mirrored back on MISO. */ @@ -605,7 +605,7 @@ static int usbtiny_spi(const PROGRAMMER *pgm, const unsigned char *cmd, unsigned static int usbtiny_chip_erase(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char res[4]; - if (p->flags & AVRPART_HAS_TPI) + if (p->prog_modes & PM_TPI) return avr_tpi_chip_erase(pgm, p); if (p->op[AVR_OP_CHIP_ERASE] == NULL) { @@ -773,7 +773,7 @@ static int usbtiny_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const AV static int usbtiny_program_enable(const PROGRAMMER *pgm, const AVRPART *p) { unsigned char buf[4]; - if (p->flags & AVRPART_HAS_TPI) + if (p->prog_modes & PM_TPI) return avr_tpi_program_enable(pgm, p, TPIPCR_GT_0b); else return usbtiny_avr_op(pgm, p, AVR_OP_PGM_ENABLE, buf);