/*
 * Do not edit: automatically generated by mkavrintel.pl
 *
 * avrintel.c
 *
 * Atmel AVR8L, AVR8, XMEGA and AVR8X family description of interrupts and more
 *
 * published under GNU General Public License, version 3 (GPL-3.0)
 * meta-author Stefan Rueger <stefan.rueger@urclocks.com>
 *
 * v 1.1
 * 20.11.2022
 *
 */

#include "ac_cfg.h"

#include <ctype.h>
#include <string.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdarg.h>
#include <limits.h>
#include <unistd.h>

#include "avrintel.h"

const uPcore_t uP_table[] = {   // Value of -1 typically means unknown
  //{mcu_name,       mcuid,  family, {sig,    na, ture}, flstart,  flsize, pgsiz, nb, bootsz, eestart, eesize, ep, rambeg, ramsiz, nf, nl,  ni,       isr_names}, // Source
  {"ATtiny4",            0, F_AVR8L, {0x1E, 0x8F, 0x0A},       0, 0x00200, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  10,    vtab_attiny9}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny5",            1, F_AVR8L, {0x1E, 0x8F, 0x09},       0, 0x00200, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  11,   vtab_attiny10}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny9",            2, F_AVR8L, {0x1E, 0x90, 0x08},       0, 0x00400, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  10,    vtab_attiny9}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny10",           3, F_AVR8L, {0x1E, 0x90, 0x03},       0, 0x00400, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  11,   vtab_attiny10}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny20",           4, F_AVR8L, {0x1E, 0x91, 0x0F},       0, 0x00800, 0x020,  0,      0,       0,      0,  0, 0x0040, 0x0080,  1,  1,  17,   vtab_attiny20}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny40",           5, F_AVR8L, {0x1E, 0x92, 0x0E},       0, 0x01000, 0x040,  0,      0,       0,      0,  0, 0x0040, 0x0100,  1,  1,  18,   vtab_attiny40}, // atdf, avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATtiny102",          6, F_AVR8L, {0x1E, 0x90, 0x0C},       0, 0x00400, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  16,  vtab_attiny104}, // atdf, avrdude, boot size (manual)
  {"ATtiny104",          7, F_AVR8L, {0x1E, 0x90, 0x0B},       0, 0x00400, 0x010,  0,      0,       0,      0,  0, 0x0040, 0x0020,  1,  1,  16,  vtab_attiny104}, // atdf, avrdude, boot size (manual)

  {"ATtiny11",           8,  F_AVR8, {0x1E, 0x90, 0x04},       0, 0x00400, 0x001,  0,      0,       0, 0x0040,  1, 0x0060, 0x0020,  1,  1,   5,   vtab_attiny11}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny12",           9,  F_AVR8, {0x1E, 0x90, 0x05},       0, 0x00400, 0x001,  0,      0,       0, 0x0040,  2, 0x0060, 0x0020,  1,  1,   6,   vtab_attiny12}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny13",          10,  F_AVR8, {0x1E, 0x90, 0x07},       0, 0x00400, 0x020,  0,      0,       0, 0x0040,  4, 0x0060, 0x0040,  2,  1,  10,  vtab_attiny13a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny13A",         11,  F_AVR8, {0x1E, 0x90, 0x07},       0, 0x00400, 0x020,  0,      0,       0, 0x0040,  4, 0x0060, 0x0040,  2,  1,  10,  vtab_attiny13a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny15",          12,  F_AVR8, {0x1E, 0x90, 0x06},       0, 0x00400, 0x001,  0,      0,       0, 0x0040,  2, 0x0060, 0x0020,  1,  1,   9,   vtab_attiny15}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny22",          13,  F_AVR8, {0x1E, 0x91, 0x06},       0, 0x00800,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0080,  1,  1,   3,   vtab_attiny22}, // avr-gcc 12.2.0
  {"ATtiny24",          14,  F_AVR8, {0x1E, 0x91, 0x0B},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny24A",         15,  F_AVR8, {0x1E, 0x91, 0x0B},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny25",          16,  F_AVR8, {0x1E, 0x91, 0x08},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  15,   vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny26",          17,  F_AVR8, {0x1E, 0x91, 0x09},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  2,  1,  12,   vtab_attiny26}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny28",          18,  F_AVR8, {0x1E, 0x91, 0x07},       0, 0x00800, 0x002,  0,      0,       0,      0,  0, 0x0060, 0x0020,  1,  1,   6,   vtab_attiny28}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny43U",         19,  F_AVR8, {0x1E, 0x92, 0x0C},       0, 0x01000, 0x040,  0,      0,       0, 0x0040,  4, 0x0060, 0x0100,  3,  1,  16,  vtab_attiny43u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny44",          20,  F_AVR8, {0x1E, 0x92, 0x07},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny44A",         21,  F_AVR8, {0x1E, 0x92, 0x07},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny45",          22,  F_AVR8, {0x1E, 0x92, 0x06},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  15,   vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny48",          23,  F_AVR8, {0x1E, 0x92, 0x09},       0, 0x01000, 0x040,  0,      0,       0, 0x0040,  4, 0x0100, 0x0100,  3,  1,  20,   vtab_attiny88}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny84",          24,  F_AVR8, {0x1E, 0x93, 0x0C},       0, 0x02000, 0x040,  0,      0,       0, 0x0200,  4, 0x0060, 0x0200,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny84A",         25,  F_AVR8, {0x1E, 0x93, 0x0C},       0, 0x02000, 0x040,  0,      0,       0, 0x0200,  4, 0x0060, 0x0200,  3,  1,  17,  vtab_attiny84a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny85",          26,  F_AVR8, {0x1E, 0x93, 0x0B},       0, 0x02000, 0x040,  0,      0,       0, 0x0200,  4, 0x0060, 0x0200,  3,  1,  15,   vtab_attiny85}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny87",          27,  F_AVR8, {0x1E, 0x93, 0x87},       0, 0x02000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny88",          28,  F_AVR8, {0x1E, 0x93, 0x11},       0, 0x02000, 0x040,  0,      0,       0, 0x0040,  4, 0x0100, 0x0200,  3,  1,  20,   vtab_attiny88}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny167",         29,  F_AVR8, {0x1E, 0x94, 0x87},       0, 0x04000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny261",         30,  F_AVR8, {0x1E, 0x91, 0x0C},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny261A",        31,  F_AVR8, {0x1E, 0x91, 0x0C},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny441",         32,  F_AVR8, {0x1E, 0x92, 0x15},       0, 0x01000, 0x010,  0,      0,       0, 0x0100,  4, 0x0100, 0x0100,  3,  1,  30,  vtab_attiny841}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny461",         33,  F_AVR8, {0x1E, 0x92, 0x08},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny461A",        34,  F_AVR8, {0x1E, 0x92, 0x08},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny828",         35,  F_AVR8, {0x1E, 0x93, 0x14},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  26,  vtab_attiny828}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny828R",        36,  F_AVR8, {0x1E, 0x93, 0x14},       0, 0x02000, 0x040, -1,     -1,       0, 0x0100,  4,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATtiny841",         37,  F_AVR8, {0x1E, 0x93, 0x15},       0, 0x02000, 0x010,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  30,  vtab_attiny841}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny861",         38,  F_AVR8, {0x1E, 0x93, 0x0D},       0, 0x02000, 0x040,  0,      0,       0, 0x0200,  4, 0x0060, 0x0200,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny861A",        39,  F_AVR8, {0x1E, 0x93, 0x0D},       0, 0x02000, 0x040,  0,      0,       0, 0x0200,  4, 0x0060, 0x0200,  3,  1,  19, vtab_attiny861a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1634",        40,  F_AVR8, {0x1E, 0x94, 0x12},       0, 0x04000, 0x020,  0,      0,       0, 0x0100,  4, 0x0100, 0x0400,  3,  1,  28, vtab_attiny1634}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1634R",       41,  F_AVR8, {0x1E, 0x94, 0x12},       0, 0x04000, 0x020, -1,     -1,       0, 0x0100,  4,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATtiny2313",        42,  F_AVR8, {0x1E, 0x91, 0x0A},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  19, vtab_attiny2313}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny2313A",       43,  F_AVR8, {0x1E, 0x91, 0x0A},       0, 0x00800, 0x020,  0,      0,       0, 0x0080,  4, 0x0060, 0x0080,  3,  1,  21, vtab_attiny4313}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny4313",        44,  F_AVR8, {0x1E, 0x92, 0x0D},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0060, 0x0100,  3,  1,  21, vtab_attiny4313}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega8",           45,  F_AVR8, {0x1E, 0x93, 0x07},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0400,  2,  1,  19,   vtab_atmega8a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega8A",          46,  F_AVR8, {0x1E, 0x93, 0x07},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0400,  2,  1,  19,   vtab_atmega8a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega8HVA",        47,  F_AVR8, {0x1E, 0x93, 0x10},       0, 0x02000, 0x080,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  1,  1,  21, vtab_atmega16hva}, // atdf, avr-gcc 12.2.0
  {"ATmega8U2",         48,  F_AVR8, {0x1E, 0x93, 0x89},       0, 0x02000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega16",          49,  F_AVR8, {0x1E, 0x94, 0x03},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0400,  2,  1,  21,  vtab_atmega16a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega16A",         50,  F_AVR8, {0x1E, 0x94, 0x03},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0400,  2,  1,  21,  vtab_atmega16a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega16HVA",       51,  F_AVR8, {0x1E, 0x94, 0x0C},       0, 0x04000, 0x080,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  1,  1,  21, vtab_atmega16hva}, // atdf, avr-gcc 12.2.0
  {"ATmega16HVB",       52,  F_AVR8, {0x1E, 0x94, 0x0D},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0400,  2,  1,  29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0
  {"ATmega16HVBrevB",   53,  F_AVR8, {0x1E, 0x94, 0x0D},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0400,  2,  1,  29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0
  {"ATmega16M1",        54,  F_AVR8, {0x1E, 0x94, 0x84},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0
  {"ATmega16HVA2",      55,  F_AVR8, {0x1E, 0x94, 0x0E},       0, 0x04000, 0x080, -1,     -1,      -1,     -1, -1, 0x0100, 0x0400,  2,  1,  22, vtab_atmega16hva2}, // avr-gcc 12.2.0
  {"ATmega16U2",        56,  F_AVR8, {0x1E, 0x94, 0x89},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega16U4",        57,  F_AVR8, {0x1E, 0x94, 0x88},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0500,  3,  1,  43, vtab_atmega32u4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32",          58,  F_AVR8, {0x1E, 0x95, 0x02},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0060, 0x0800,  2,  1,  21,  vtab_atmega323}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32A",         59,  F_AVR8, {0x1E, 0x95, 0x02},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0060, 0x0800,  2,  1,  21,  vtab_atmega323}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32HVB",       60,  F_AVR8, {0x1E, 0x95, 0x10},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  2,  1,  29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0
  {"ATmega32HVBrevB",   61,  F_AVR8, {0x1E, 0x95, 0x10},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  2,  1,  29, vtab_atmega32hvbrevb}, // atdf, avr-gcc 12.2.0
  {"ATmega32C1",        62,  F_AVR8, {0x1E, 0x95, 0x86},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0
  {"ATmega32M1",        63,  F_AVR8, {0x1E, 0x95, 0x84},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32U2",        64,  F_AVR8, {0x1E, 0x95, 0x8A},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0400,  3,  1,  29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32U4",        65,  F_AVR8, {0x1E, 0x95, 0x87},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0a00,  3,  1,  43, vtab_atmega32u4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega32U6",        66,  F_AVR8, {0x1E, 0x95, 0x88},       0, 0x08000, 0x080,  4, 0x0200,      -1,     -1, -1, 0x0100, 0x0a00,  3,  1,  38, vtab_atmega32u6}, // avr-gcc 12.2.0, boot size (manual)
  {"ATmega48",          67,  F_AVR8, {0x1E, 0x92, 0x05},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega48A",         68,  F_AVR8, {0x1E, 0x92, 0x05},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega48P",         69,  F_AVR8, {0x1E, 0x92, 0x0A},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega48PA",        70,  F_AVR8, {0x1E, 0x92, 0x0A},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega48PB",        71,  F_AVR8, {0x1E, 0x92, 0x10},       0, 0x01000, 0x040,  0,      0,       0, 0x0100,  4, 0x0100, 0x0200,  3,  1,  27, vtab_atmega168pb}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega64",          72,  F_AVR8, {0x1E, 0x96, 0x02},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega64A",         73,  F_AVR8, {0x1E, 0x96, 0x02},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega64HVE",       74,  F_AVR8, {0x1E, 0x96, 0x10},       0, 0x10000, 0x080,  4, 0x0400,      -1,     -1, -1, 0x0100, 0x1000,  2,  1,  25, vtab_atmega64hve2}, // avr-gcc 12.2.0, boot size (manual)
  {"ATmega64C1",        75,  F_AVR8, {0x1E, 0x96, 0x86},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0
  {"ATmega64M1",        76,  F_AVR8, {0x1E, 0x96, 0x84},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  31, vtab_atmega64m1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega64HVE2",      77,  F_AVR8, {0x1E, 0x96, 0x10},       0, 0x10000, 0x080,  4, 0x0400,       0, 0x0400,  4, 0x0100, 0x1000,  2,  1,  25, vtab_atmega64hve2}, // atdf, avr-gcc 12.2.0
  {"ATmega64RFR2",      78,  F_AVR8, {0x1E, 0xA6, 0x02},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0200, 0x2000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega88",          79,  F_AVR8, {0x1E, 0x93, 0x0A},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega88A",         80,  F_AVR8, {0x1E, 0x93, 0x0A},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega88P",         81,  F_AVR8, {0x1E, 0x93, 0x0F},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega88PA",        82,  F_AVR8, {0x1E, 0x93, 0x0F},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega88PB",        83,  F_AVR8, {0x1E, 0x93, 0x16},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  27, vtab_atmega168pb}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega103",         84,  F_AVR8, {0x1E, 0x97, 0x01},       0, 0x20000, 0x100, -1,     -1,       0, 0x1000,  1, 0x0060, 0x0fa0,  1,  1,  24,  vtab_atmega103}, // avr-gcc 12.2.0, avrdude
  {"ATmega128",         85,  F_AVR8, {0x1E, 0x97, 0x02},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x1000,  3,  1,  35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega128A",        86,  F_AVR8, {0x1E, 0x97, 0x02},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x1000,  3,  1,  35, vtab_atmega128a}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega128RFA1",     87,  F_AVR8, {0x1E, 0xA7, 0x01},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x4000,  3,  1,  72, vtab_atmega128rfa1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega128RFR2",     88,  F_AVR8, {0x1E, 0xA7, 0x02},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x4000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega161",         89,  F_AVR8, {0x1E, 0x94, 0x01},       0, 0x04000, 0x080,  1, 0x0400,       0, 0x0200,  1, 0x0060, 0x0400,  1,  1,  21,  vtab_atmega161}, // avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATmega162",         90,  F_AVR8, {0x1E, 0x94, 0x04},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  28,  vtab_atmega162}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega163",         91,  F_AVR8, {0x1E, 0x94, 0x02},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  1, 0x0060, 0x0400,  2,  1,  18,  vtab_atmega163}, // avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATmega164A",        92,  F_AVR8, {0x1E, 0x94, 0x0F},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega164P",        93,  F_AVR8, {0x1E, 0x94, 0x0A},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega164PA",       94,  F_AVR8, {0x1E, 0x94, 0x0A},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega165",         95,  F_AVR8, {0x1E, 0x94, 0x10},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  22, vtab_atmega645p}, // avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATmega165A",        96,  F_AVR8, {0x1E, 0x94, 0x10},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega165P",        97,  F_AVR8, {0x1E, 0x94, 0x07},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega165PA",       98,  F_AVR8, {0x1E, 0x94, 0x07},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega168",         99,  F_AVR8, {0x1E, 0x94, 0x06},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26,  vtab_atmega328}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega168A",       100,  F_AVR8, {0x1E, 0x94, 0x06},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega168P",       101,  F_AVR8, {0x1E, 0x94, 0x0B},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega168PA",      102,  F_AVR8, {0x1E, 0x94, 0x0B},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega168PB",      103,  F_AVR8, {0x1E, 0x94, 0x15},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  27, vtab_atmega168pb}, // atdf, avr-gcc 7.3.0, avrdude
  {"ATmega169",        104,  F_AVR8, {0x1E, 0x94, 0x05},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  23, vtab_atmega649p}, // avr-gcc 12.2.0, avrdude, boot size (manual)
  {"ATmega169A",       105,  F_AVR8, {0x1E, 0x94, 0x11},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega169P",       106,  F_AVR8, {0x1E, 0x94, 0x05},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega169PA",      107,  F_AVR8, {0x1E, 0x94, 0x05},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega256RFR2",    108,  F_AVR8, {0x1E, 0xA8, 0x02},       0, 0x40000, 0x100,  4, 0x0400,       0, 0x2000,  8, 0x0200, 0x8000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega323",        109,  F_AVR8, {0x1E, 0x95, 0x01},       0, 0x08000, 0x080,  4, 0x0200,      -1,     -1, -1, 0x0060, 0x0800,  2,  1,  21,  vtab_atmega323}, // avr-gcc 12.2.0, boot size (manual)
  {"ATmega324A",       110,  F_AVR8, {0x1E, 0x95, 0x15},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega324P",       111,  F_AVR8, {0x1E, 0x95, 0x08},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega324PA",      112,  F_AVR8, {0x1E, 0x95, 0x11},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega324PB",      113,  F_AVR8, {0x1E, 0x95, 0x17},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  51, vtab_atmega324pb}, // atdf, avrdude
  {"ATmega325",        114,  F_AVR8, {0x1E, 0x95, 0x05},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega325A",       115,  F_AVR8, {0x1E, 0x95, 0x05},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega325P",       116,  F_AVR8, {0x1E, 0x95, 0x0D},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega325PA",      117,  F_AVR8, {0x1E, 0x95, 0x0D},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega328",        118,  F_AVR8, {0x1E, 0x95, 0x14},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  26,  vtab_atmega328}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega328P",       119,  F_AVR8, {0x1E, 0x95, 0x0F},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega328PB",      120,  F_AVR8, {0x1E, 0x95, 0x16},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  45, vtab_atmega328pb}, // atdf, avr-gcc 7.3.0, avrdude
  {"ATmega329",        121,  F_AVR8, {0x1E, 0x95, 0x03},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega329A",       122,  F_AVR8, {0x1E, 0x95, 0x03},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega329P",       123,  F_AVR8, {0x1E, 0x95, 0x0B},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega329PA",      124,  F_AVR8, {0x1E, 0x95, 0x0B},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega406",        125,  F_AVR8, {0x1E, 0x95, 0x07},       0, 0x0a000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0800,  2,  1,  23,  vtab_atmega406}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega640",        126,  F_AVR8, {0x1E, 0x96, 0x08},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x2000,  3,  1,  57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega644",        127,  F_AVR8, {0x1E, 0x96, 0x09},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  28,  vtab_atmega644}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega644A",       128,  F_AVR8, {0x1E, 0x96, 0x09},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega644P",       129,  F_AVR8, {0x1E, 0x96, 0x0A},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega644PA",      130,  F_AVR8, {0x1E, 0x96, 0x0A},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  31, vtab_atmega644pa}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega644RFR2",    131,  F_AVR8, {0x1E, 0xA6, 0x03},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0200, 0x2000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega645",        132,  F_AVR8, {0x1E, 0x96, 0x05},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega645A",       133,  F_AVR8, {0x1E, 0x96, 0x05},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega645P",       134,  F_AVR8, {0x1E, 0x96, 0x0D},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  22, vtab_atmega645p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega649",        135,  F_AVR8, {0x1E, 0x96, 0x03},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega649A",       136,  F_AVR8, {0x1E, 0x96, 0x03},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega649P",       137,  F_AVR8, {0x1E, 0x96, 0x0B},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  23, vtab_atmega649p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1280",       138,  F_AVR8, {0x1E, 0x97, 0x03},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x2000,  3,  1,  57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1281",       139,  F_AVR8, {0x1E, 0x97, 0x04},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x2000,  3,  1,  57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1284",       140,  F_AVR8, {0x1E, 0x97, 0x06},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x4000,  3,  1,  35, vtab_atmega1284p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1284P",      141,  F_AVR8, {0x1E, 0x97, 0x05},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x4000,  3,  1,  35, vtab_atmega1284p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1284RFR2",   142,  F_AVR8, {0x1E, 0xA7, 0x03},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x4000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega2560",       143,  F_AVR8, {0x1E, 0x98, 0x01},       0, 0x40000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x2000,  3,  1,  57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega2561",       144,  F_AVR8, {0x1E, 0x98, 0x02},       0, 0x40000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0200, 0x2000,  3,  1,  57, vtab_atmega2561}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega2564RFR2",   145,  F_AVR8, {0x1E, 0xA8, 0x03},       0, 0x40000, 0x100,  4, 0x0400,       0, 0x2000,  8, 0x0200, 0x8000,  3,  1,  77, vtab_atmega2564rfr2}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3250",       146,  F_AVR8, {0x1E, 0x95, 0x06},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3250A",      147,  F_AVR8, {0x1E, 0x95, 0x06},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3250P",      148,  F_AVR8, {0x1E, 0x95, 0x0E},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3250PA",     149,  F_AVR8, {0x1E, 0x95, 0x0E},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3290",       150,  F_AVR8, {0x1E, 0x95, 0x04},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3290A",      151,  F_AVR8, {0x1E, 0x95, 0x04},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3290P",      152,  F_AVR8, {0x1E, 0x95, 0x0C},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3290PA",     153,  F_AVR8, {0x1E, 0x95, 0x0C},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6450",       154,  F_AVR8, {0x1E, 0x96, 0x06},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6450A",      155,  F_AVR8, {0x1E, 0x96, 0x06},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6450P",      156,  F_AVR8, {0x1E, 0x96, 0x0E},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6450p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6490",       157,  F_AVR8, {0x1E, 0x96, 0x04},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6490A",      158,  F_AVR8, {0x1E, 0x96, 0x04},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega6490P",      159,  F_AVR8, {0x1E, 0x96, 0x0C},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  25, vtab_atmega6490p}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega8515",       160,  F_AVR8, {0x1E, 0x93, 0x06},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0200,  2,  1,  17, vtab_atmega8515}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega8535",       161,  F_AVR8, {0x1E, 0x93, 0x08},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0060, 0x0200,  2,  1,  21, vtab_atmega8535}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT43USB320",       162,  F_AVR8, {0xff,   -1,   -1},       0, 0x10000,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0200, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"AT43USB355",       163,  F_AVR8, {0xff,   -1,   -1},       0, 0x06000,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0400, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"AT76C711",         164,  F_AVR8, {0xff,   -1,   -1},       0, 0x04000,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x07a0, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"AT86RF401",        165,  F_AVR8, {0x1E, 0x91, 0x81},       0, 0x00800,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0080,  0,  1,   3,  vtab_at86rf401}, // avr-gcc 12.2.0
  {"AT90PWM1",         166,  F_AVR8, {0x1E, 0x93, 0x83},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0
  {"AT90PWM2",         167,  F_AVR8, {0x1E, 0x93, 0x81},       0, 0x02000, 0x040,  4,     -1,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  32,   vtab_at90pwm2}, // avr-gcc 12.2.0, avrdude
  {"AT90PWM2B",        168,  F_AVR8, {0x1E, 0x93, 0x83},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  32,  vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM3",         169,  F_AVR8, {0x1E, 0x93, 0x81},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  32,  vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM3B",        170,  F_AVR8, {0x1E, 0x93, 0x83},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  32,  vtab_at90pwm3b}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90CAN32",        171,  F_AVR8, {0x1E, 0x95, 0x81},       0, 0x08000, 0x100,  4, 0x0400,       0, 0x0400,  8, 0x0100, 0x0800,  3,  1,  37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90CAN64",        172,  F_AVR8, {0x1E, 0x96, 0x81},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM81",        173,  F_AVR8, {0x1E, 0x93, 0x88},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0100,  3,  1,  20, vtab_at90pwm161}, // atdf, avr-gcc 12.2.0
  {"AT90USB82",        174,  F_AVR8, {0x1E, 0x93, 0x82},       0, 0x02000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90SCR100",       175,  F_AVR8, {0x1E, 0x96, 0xC1},       0, 0x10000, 0x100,  4, 0x0200,      -1,     -1, -1, 0x0100, 0x1000,  3,  1,  38, vtab_at90scr100}, // avr-gcc 12.2.0, boot size (manual)
  {"AT90CAN128",       176,  F_AVR8, {0x1E, 0x97, 0x81},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x1000,  3,  1,  37, vtab_at90can128}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM161",       177,  F_AVR8, {0x1E, 0x94, 0x8B},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  20, vtab_at90pwm161}, // atdf, avr-gcc 12.2.0
  {"AT90USB162",       178,  F_AVR8, {0x1E, 0x94, 0x82},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  29, vtab_atmega32u2}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM216",       179,  F_AVR8, {0x1E, 0x94, 0x83},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90PWM316",       180,  F_AVR8, {0x1E, 0x94, 0x83},       0, 0x04000, 0x080,  4, 0x0200,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  32, vtab_at90pwm316}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90USB646",       181,  F_AVR8, {0x1E, 0x96, 0x82},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90USB647",       182,  F_AVR8, {0x1E, 0x96, 0x82},       0, 0x10000, 0x100,  4, 0x0400,       0, 0x0800,  8, 0x0100, 0x1000,  3,  1,  38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90S1200",        183,  F_AVR8, {0x1E, 0x90, 0x01},       0, 0x00400, 0x001, -1,     -1,       0, 0x0040,  1, 0x0060, 0x0020,  1,  1,   4,  vtab_at90s1200}, // avr-gcc 12.2.0, avrdude
  {"AT90USB1286",      184,  F_AVR8, {0x1E, 0x97, 0x82},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x2000,  3,  1,  38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90USB1287",      185,  F_AVR8, {0x1E, 0x97, 0x82},       0, 0x20000, 0x100,  4, 0x0400,       0, 0x1000,  8, 0x0100, 0x2000,  3,  1,  38, vtab_atmega32u6}, // atdf, avr-gcc 12.2.0, avrdude
  {"AT90S2313",        186,  F_AVR8, {0x1E, 0x91, 0x01},       0, 0x00800, 0x001, -1,     -1,       0, 0x0080,  1, 0x0060, 0x0080,  1,  1,  11,  vtab_at90s2313}, // avr-gcc 12.2.0, avrdude
  {"AT90S2323",        187,  F_AVR8, {0x1E, 0x91, 0x02},       0, 0x00800,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0080,  1,  1,   3,   vtab_attiny22}, // avr-gcc 12.2.0
  {"AT90S2333",        188,  F_AVR8, {0x1E, 0x91, 0x05},       0, 0x00800, 0x001, -1,     -1,       0, 0x0080,  1, 0x0060, 0x0080, -1, -1,  14,  vtab_at90s4433}, // avr-gcc 12.2.0, avrdude
  {"AT90S2343",        189,  F_AVR8, {0x1E, 0x91, 0x03},       0, 0x00800, 0x001, -1,     -1,       0, 0x0080,  1, 0x0060, 0x0080,  1,  1,   3,   vtab_attiny22}, // avr-gcc 12.2.0, avrdude
  {"AT90S4414",        190,  F_AVR8, {0x1E, 0x92, 0x01},       0, 0x01000, 0x001, -1,     -1,       0, 0x0100,  1, 0x0060, 0x0100,  1,  1,  13,  vtab_at90s8515}, // avr-gcc 12.2.0, avrdude
  {"AT90S4433",        191,  F_AVR8, {0x1E, 0x92, 0x03},       0, 0x01000, 0x001, -1,     -1,       0, 0x0100,  1, 0x0060, 0x0080,  1,  1,  14,  vtab_at90s4433}, // avr-gcc 12.2.0, avrdude
  {"AT90S4434",        192,  F_AVR8, {0x1E, 0x92, 0x02},       0, 0x01000, 0x001, -1,     -1,       0, 0x0100,  1, 0x0060, 0x0100,  1,  1,  17,  vtab_at90s8535}, // avr-gcc 12.2.0, avrdude
  {"AT90S8515",        193,  F_AVR8, {0x1E, 0x93, 0x01},       0, 0x02000, 0x001, -1,     -1,       0, 0x0200,  1, 0x0060, 0x0200,  1,  1,  13,  vtab_at90s8515}, // avr-gcc 12.2.0, avrdude
  {"AT90C8534",        194,  F_AVR8, {0xff,   -1,   -1},       0, 0x02000,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0100, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"AT90S8535",        195,  F_AVR8, {0x1E, 0x93, 0x03},       0, 0x02000, 0x001, -1,     -1,       0, 0x0200,  1, 0x0060, 0x0200,  1,  1,  17,  vtab_at90s8535}, // avr-gcc 12.2.0, avrdude
  {"AT94K",            196,  F_AVR8, {0xff,   -1,   -1},       0, 0x08000,    -1, -1,     -1,      -1,     -1, -1, 0x0060, 0x0fa0, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"ATA5272",          197,  F_AVR8, {0x1E, 0x93, 0x87},       0, 0x02000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  37,    vtab_ata5272}, // atdf, avr-gcc 12.2.0
  {"ATA5505",          198,  F_AVR8, {0x1E, 0x94, 0x87},       0, 0x04000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0
  {"ATA5700M322",      199,  F_AVR8, {0x1E, 0x95, 0x67}, 0x08000, 0x08000, 0x040,  0,      0,       0, 0x0880, 16, 0x0200, 0x0400,  1,  1,  51, vtab_ata5702m322}, // atdf
  {"ATA5702M322",      200,  F_AVR8, {0x1E, 0x95, 0x69}, 0x08000, 0x08000, 0x040,  0,      0,       0, 0x0880, 16, 0x0200, 0x0400,  1,  1,  51, vtab_ata5702m322}, // atdf, avr-gcc 12.2.0
  {"ATA5781",          201,  F_AVR8, {0x1E, 0x95, 0x64},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA5782",          202,  F_AVR8, {0x1E, 0x95, 0x65}, 0x08000, 0x05000, 0x040,  1, 0x5000,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf, avr-gcc 12.2.0
  {"ATA5783",          203,  F_AVR8, {0x1E, 0x95, 0x66},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA5787",          204,  F_AVR8, {0x1E, 0x94, 0x6C}, 0x08000, 0x05200, 0x040,  0,      0,       0, 0x0400, 16, 0x0200, 0x0800,  1,  1,  44,    vtab_ata5835}, // atdf
  {"ATA5790",          205,  F_AVR8, {0x1E, 0x94, 0x61},       0, 0x04000, 0x080,  1, 0x0800,       0, 0x0800, 16, 0x0100, 0x0200,  1,  1,  30,    vtab_ata5790}, // atdf, avr-gcc 12.2.0
  {"ATA5790N",         206,  F_AVR8, {0x1E, 0x94, 0x62},       0, 0x04000, 0x080,  1, 0x0800,       0, 0x0800, 16, 0x0100, 0x0200,  1,  1,  31,    vtab_ata5791}, // atdf, avr-gcc 12.2.0
  {"ATA5791",          207,  F_AVR8, {0x1E, 0x94, 0x62},       0, 0x04000, 0x080,  1, 0x0800,       0, 0x0800, 16, 0x0100, 0x0200,  1,  1,  31,    vtab_ata5791}, // atdf, avr-gcc 7.3.0
  {"ATA5795",          208,  F_AVR8, {0x1E, 0x93, 0x61},       0, 0x02000, 0x040,  1, 0x0800,       0, 0x0800, 16, 0x0100, 0x0200,  1,  1,  23,    vtab_ata5795}, // atdf, avr-gcc 12.2.0
  {"ATA5831",          209,  F_AVR8, {0x1E, 0x95, 0x61}, 0x08000, 0x05000, 0x040,  1, 0x5000,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf, avr-gcc 12.2.0
  {"ATA5832",          210,  F_AVR8, {0x1E, 0x95, 0x62},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA5833",          211,  F_AVR8, {0x1E, 0x95, 0x63},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA5835",          212,  F_AVR8, {0x1E, 0x94, 0x6B}, 0x08000, 0x05200, 0x040,  0,      0,       0, 0x0400, 16, 0x0200, 0x0800,  1,  1,  44,    vtab_ata5835}, // atdf
  {"ATA6285",          213,  F_AVR8, {0x1E, 0x93, 0x82},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0140,  4, 0x0100, 0x0200,  2,  1,  27,    vtab_ata6289}, // atdf, avr-gcc 12.2.0
  {"ATA6286",          214,  F_AVR8, {0x1E, 0x93, 0x82},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0140,  4, 0x0100, 0x0200,  2,  1,  27,    vtab_ata6289}, // atdf, avr-gcc 12.2.0
  {"ATA6289",          215,  F_AVR8, {0x1E, 0x93, 0x82},       0, 0x02000, 0x040,  4, 0x0100,      -1,     -1, -1, 0x0100, 0x0200,  2,  1,  27,    vtab_ata6289}, // avr-gcc 12.2.0, boot size (manual)
  {"ATA6612C",         216,  F_AVR8, {0x1E, 0x93, 0x0A},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0
  {"ATA6613C",         217,  F_AVR8, {0x1E, 0x94, 0x06},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0
  {"ATA6614Q",         218,  F_AVR8, {0x1E, 0x95, 0x0F},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  26, vtab_atmega328p}, // atdf, avr-gcc 12.2.0
  {"ATA6616C",         219,  F_AVR8, {0x1E, 0x93, 0x87},       0, 0x02000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0
  {"ATA6617C",         220,  F_AVR8, {0x1E, 0x94, 0x87},       0, 0x04000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0
  {"ATA8210",          221,  F_AVR8, {0x1E, 0x95, 0x65}, 0x08000, 0x05000, 0x040,  1, 0x5000,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf, avr-gcc 7.3.0
  {"ATA8215",          222,  F_AVR8, {0x1E, 0x95, 0x64},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA8510",          223,  F_AVR8, {0x1E, 0x95, 0x61}, 0x08000, 0x05000, 0x040,  1, 0x5000,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf, avr-gcc 7.3.0
  {"ATA8515",          224,  F_AVR8, {0x1E, 0x95, 0x63},      -1,      -1,    -1,  0,      0,       0, 0x0400, 16, 0x0200, 0x0400,  1,  1,  42,    vtab_ata8515}, // atdf
  {"ATA664251",        225,  F_AVR8, {0x1E, 0x94, 0x87},       0, 0x04000, 0x080,  0,      0,       0, 0x0200,  4, 0x0100, 0x0200,  3,  1,  20,  vtab_attiny167}, // atdf, avr-gcc 12.2.0
  {"M3000",            226,  F_AVR8, {0xff,   -1,   -1},       0, 0x10000,    -1, -1,     -1,      -1,     -1, -1, 0x1000, 0x1000, -1, -1,   0,            NULL}, // avr-gcc 12.2.0
  {"LGT8F88P",         227,  F_AVR8, {0x1E, 0x93, 0x0F},       0, 0x02000, 0x040,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // avrdude, from ATmega88
  {"LGT8F168P",        228,  F_AVR8, {0x1E, 0x94, 0x0B},       0, 0x04000, 0x080,  4, 0x0100,       0, 0x0200,  4, 0x0100, 0x0400,  3,  1,  26, vtab_atmega328p}, // avrdude, from ATmega168P
  {"LGT8F328P",        229,  F_AVR8, {0x1E, 0x95, 0x0F},       0, 0x08000, 0x080,  4, 0x0200,       0, 0x0400,  4, 0x0100, 0x0800,  3,  1,  26, vtab_atmega328p}, // avrdude, from ATmega328P

  {"ATxmega8E5",       230, F_XMEGA, {0x1E, 0x93, 0x41},       0, 0x02800, 0x080,  1, 0x0800,       0, 0x0200, 32, 0x2000, 0x0400,  7,  1,  43, vtab_atxmega32e5}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega16A4",      231, F_XMEGA, {0x1E, 0x94, 0x41},       0, 0x05000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x0800,  6,  1,  94, vtab_atxmega32a4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega16A4U",     232, F_XMEGA, {0x1E, 0x94, 0x41},       0, 0x05000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x0800,  6,  1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega16C4",      233, F_XMEGA, {0x1E, 0x94, 0x43},       0, 0x05000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x0800,  6,  1, 127, vtab_atxmega32c4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega16D4",      234, F_XMEGA, {0x1E, 0x94, 0x42},       0, 0x05000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x0800,  6,  1,  91, vtab_atxmega32d4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega16E5",      235, F_XMEGA, {0x1E, 0x94, 0x45},       0, 0x05000, 0x080,  1, 0x1000,       0, 0x0200, 32, 0x2000, 0x0800,  7,  1,  43, vtab_atxmega32e5}, // atdf, avr-gcc 7.3.0, avrdude
  {"ATxmega32C3",      236, F_XMEGA, {0x1E, 0x95, 0x49},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0
  {"ATxmega32D3",      237, F_XMEGA, {0x1E, 0x95, 0x4A},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0
  {"ATxmega32A4",      238, F_XMEGA, {0x1E, 0x95, 0x41},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1,  94, vtab_atxmega32a4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega32A4U",     239, F_XMEGA, {0x1E, 0x95, 0x41},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega32C4",      240, F_XMEGA, {0x1E, 0x95, 0x44},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega32c4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega32D4",      241, F_XMEGA, {0x1E, 0x95, 0x42},       0, 0x09000, 0x100,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  6,  1,  91, vtab_atxmega32d4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega32E5",      242, F_XMEGA, {0x1E, 0x95, 0x4C},       0, 0x09000, 0x080,  1, 0x1000,       0, 0x0400, 32, 0x2000, 0x1000,  7,  1,  43, vtab_atxmega32e5}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64A1",      243, F_XMEGA, {0x1E, 0x96, 0x4E},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 125, vtab_atxmega128a1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64A1U",     244, F_XMEGA, {0x1E, 0x96, 0x4E},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega128a1u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64B1",      245, F_XMEGA, {0x1E, 0x96, 0x52},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1,  81, vtab_atxmega128b1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64A3",      246, F_XMEGA, {0x1E, 0x96, 0x42},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64A3U",     247, F_XMEGA, {0x1E, 0x96, 0x42},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64B3",      248, F_XMEGA, {0x1E, 0x96, 0x51},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1,  54, vtab_atxmega128b3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64C3",      249, F_XMEGA, {0x1E, 0x96, 0x49},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64D3",      250, F_XMEGA, {0x1E, 0x96, 0x4A},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64A4",      251, F_XMEGA, {0x1E, 0x96, 0x46},       0, 0x11000, 0x100, -1,     -1,       0, 0x0800, 32,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATxmega64A4U",     252, F_XMEGA, {0x1E, 0x96, 0x46},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega64D4",      253, F_XMEGA, {0x1E, 0x96, 0x47},       0, 0x11000, 0x100,  1, 0x1000,       0, 0x0800, 32, 0x2000, 0x1000,  6,  1,  91, vtab_atxmega128d4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128A1",     254, F_XMEGA, {0x1E, 0x97, 0x4C},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 125, vtab_atxmega128a1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128A1revD", 255, F_XMEGA, {0x1E, 0x97, 0x41},       0, 0x22000, 0x200, -1,     -1,       0, 0x0800, 32,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATxmega128A1U",    256, F_XMEGA, {0x1E, 0x97, 0x4C},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 127, vtab_atxmega128a1u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128B1",     257, F_XMEGA, {0x1E, 0x97, 0x4D},       0, 0x22000, 0x100,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1,  81, vtab_atxmega128b1}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128A3",     258, F_XMEGA, {0x1E, 0x97, 0x42},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128A3U",    259, F_XMEGA, {0x1E, 0x97, 0x42},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128B3",     260, F_XMEGA, {0x1E, 0x97, 0x4B},       0, 0x22000, 0x100,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1,  54, vtab_atxmega128b3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128C3",     261, F_XMEGA, {0x1E, 0x97, 0x52},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128D3",     262, F_XMEGA, {0x1E, 0x97, 0x48},       0, 0x22000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128A4",     263, F_XMEGA, {0x1E, 0x97, 0x46},       0, 0x22000, 0x200, -1,     -1,       0, 0x0800, 32,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATxmega128A4U",    264, F_XMEGA, {0x1E, 0x97, 0x46},       0, 0x22000, 0x100,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1, 127, vtab_atxmega128a4u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega128D4",     265, F_XMEGA, {0x1E, 0x97, 0x47},       0, 0x22000, 0x100,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x2000,  6,  1,  91, vtab_atxmega128d4}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega192A1",     266, F_XMEGA, {0x1E, 0x97, 0x4E},       0, 0x32000, 0x200, -1,     -1,       0, 0x0800, 32,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATxmega192A3",     267, F_XMEGA, {0x1E, 0x97, 0x44},       0, 0x32000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x4000,  6,  1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega192A3U",    268, F_XMEGA, {0x1E, 0x97, 0x44},       0, 0x32000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x4000,  6,  1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega192C3",     269, F_XMEGA, {0x1E, 0x97, 0x51},       0, 0x32000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x4000,  6,  1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega192D3",     270, F_XMEGA, {0x1E, 0x97, 0x49},       0, 0x32000, 0x200,  1, 0x2000,       0, 0x0800, 32, 0x2000, 0x4000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256A1",     271, F_XMEGA, {0x1E, 0x98, 0x46},       0, 0x42000, 0x200, -1,     -1,       0, 0x1000, 32,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"ATxmega256A3",     272, F_XMEGA, {0x1E, 0x98, 0x42},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 122, vtab_atxmega256a3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256A3B",    273, F_XMEGA, {0x1E, 0x98, 0x43},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 122, vtab_atxmega256a3b}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256A3BU",   274, F_XMEGA, {0x1E, 0x98, 0x43},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 127, vtab_atxmega256a3bu}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256A3U",    275, F_XMEGA, {0x1E, 0x98, 0x42},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 127, vtab_atxmega256a3u}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256C3",     276, F_XMEGA, {0x1E, 0x98, 0x46},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 127, vtab_atxmega256c3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega256D3",     277, F_XMEGA, {0x1E, 0x98, 0x44},       0, 0x42000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x4000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega384C3",     278, F_XMEGA, {0x1E, 0x98, 0x45},       0, 0x62000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x8000,  6,  1, 127, vtab_atxmega384c3}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATxmega384D3",     279, F_XMEGA, {0x1E, 0x98, 0x47},       0, 0x62000, 0x200,  1, 0x2000,       0, 0x1000, 32, 0x2000, 0x8000,  6,  1, 114, vtab_atxmega384d3}, // atdf, avr-gcc 12.2.0, avrdude

  {"ATtiny202",        280, F_AVR8X, {0x1E, 0x91, 0x23},       0, 0x00800, 0x040,  1,      0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10,  1,  26,  vtab_attiny402}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny204",        281, F_AVR8X, {0x1E, 0x91, 0x22},       0, 0x00800, 0x040,  1,      0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10,  1,  26,  vtab_attiny404}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny212",        282, F_AVR8X, {0x1E, 0x91, 0x21},       0, 0x00800, 0x040,  1,      0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10,  1,  26,  vtab_attiny412}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny214",        283, F_AVR8X, {0x1E, 0x91, 0x20},       0, 0x00800, 0x040,  1,      0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, 10,  1,  26,  vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny402",        284, F_AVR8X, {0x1E, 0x92, 0x27},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny402}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny404",        285, F_AVR8X, {0x1E, 0x92, 0x26},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny404}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny406",        286, F_AVR8X, {0x1E, 0x92, 0x25},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny406}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny412",        287, F_AVR8X, {0x1E, 0x92, 0x23},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny412}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny414",        288, F_AVR8X, {0x1E, 0x92, 0x22},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny416",        289, F_AVR8X, {0x1E, 0x92, 0x21},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny416auto",    290, F_AVR8X, {0x1E, 0x92, 0x28},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny817}, // atdf
  {"ATtiny417",        291, F_AVR8X, {0x1E, 0x92, 0x20},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, 10,  1,  26,  vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny424",        292, F_AVR8X, {0x1E, 0x92, 0x2C},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny426",        293, F_AVR8X, {0x1E, 0x92, 0x2B},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny427",        294, F_AVR8X, {0x1E, 0x92, 0x2A},       0, 0x01000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny804",        295, F_AVR8X, {0x1E, 0x93, 0x25},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny806",        296, F_AVR8X, {0x1E, 0x93, 0x24},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny807",        297, F_AVR8X, {0x1E, 0x93, 0x23},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny814",        298, F_AVR8X, {0x1E, 0x93, 0x22},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  26,  vtab_attiny814}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny816",        299, F_AVR8X, {0x1E, 0x93, 0x21},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  26,  vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny817",        300, F_AVR8X, {0x1E, 0x93, 0x20},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, 10,  1,  26,  vtab_attiny817}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny824",        301, F_AVR8X, {0x1E, 0x93, 0x29},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny826",        302, F_AVR8X, {0x1E, 0x93, 0x28},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny827",        303, F_AVR8X, {0x1E, 0x93, 0x27},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny1604",       304, F_AVR8X, {0x1E, 0x94, 0x25},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1606",       305, F_AVR8X, {0x1E, 0x94, 0x24},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1607",       306, F_AVR8X, {0x1E, 0x94, 0x23},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10,  1,  31, vtab_attiny1607}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1614",       307, F_AVR8X, {0x1E, 0x94, 0x22},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  31, vtab_attiny1614}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1616",       308, F_AVR8X, {0x1E, 0x94, 0x21},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1617",       309, F_AVR8X, {0x1E, 0x94, 0x20},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny1624",       310, F_AVR8X, {0x1E, 0x94, 0x2A},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny1626",       311, F_AVR8X, {0x1E, 0x94, 0x29},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny1627",       312, F_AVR8X, {0x1E, 0x94, 0x28},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny3214",       313, F_AVR8X, {0x1E, 0x95, 0x20},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10,  1,  31, vtab_attiny3214}, // avr-gcc 12.2.0
  {"ATtiny3216",       314, F_AVR8X, {0x1E, 0x95, 0x21},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10,  1,  31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny3217",       315, F_AVR8X, {0x1E, 0x95, 0x22},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3800, 0x0800, 10,  1,  31, vtab_attiny3217}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATtiny3224",       316, F_AVR8X, {0x1E, 0x95, 0x28},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny3226",       317, F_AVR8X, {0x1E, 0x95, 0x27},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATtiny3227",       318, F_AVR8X, {0x1E, 0x95, 0x26},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, 10,  1,  30, vtab_attiny3227}, // atdf, avrdude
  {"ATmega808",        319, F_AVR8X, {0x1E, 0x93, 0x26},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10,  1,  36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega809",        320, F_AVR8X, {0x1E, 0x93, 0x2A},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, 10,  1,  40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1608",       321, F_AVR8X, {0x1E, 0x94, 0x27},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega1609",       322, F_AVR8X, {0x1E, 0x94, 0x26},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0100, 32, 0x3800, 0x0800, 10,  1,  40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3208",       323, F_AVR8X, {0x1E, 0x95, 0x30},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3000, 0x1000, 10,  1,  36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega3209",       324, F_AVR8X, {0x1E, 0x95, 0x31},       0, 0x08000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x3000, 0x1000, 10,  1,  40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega4808",       325, F_AVR8X, {0x1E, 0x96, 0x50},       0, 0x0c000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x2800, 0x1800, 10,  1,  36, vtab_atmega4808}, // atdf, avr-gcc 12.2.0, avrdude
  {"ATmega4809",       326, F_AVR8X, {0x1E, 0x96, 0x51},       0, 0x0c000, 0x080,  1,      0, 0x01400, 0x0100, 64, 0x2800, 0x1800, 10,  1,  40, vtab_atmega4809}, // atdf, avr-gcc 12.2.0, avrdude
  {"AVR8EA28",         327, F_AVR8X, {0x1E, 0x93, 0x2C},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR8EA32",         328, F_AVR8X, {0x1E, 0x93, 0x2B},       0, 0x02000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR16DD14",        329, F_AVR8X, {0x1E, 0x94, 0x34},       0, 0x04000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7800, 0x0800, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR16DD20",        330, F_AVR8X, {0x1E, 0x94, 0x33},       0, 0x04000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7800, 0x0800, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR16DD28",        331, F_AVR8X, {0x1E, 0x94, 0x32},       0, 0x04000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7800, 0x0800, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR16EA28",        332, F_AVR8X, {0x1E, 0x94, 0x37},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR16DD32",        333, F_AVR8X, {0x1E, 0x94, 0x31},       0, 0x04000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7800, 0x0800, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR16EA32",        334, F_AVR8X, {0x1E, 0x94, 0x36},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR16EA48",        335, F_AVR8X, {0x1E, 0x94, 0x35},       0, 0x04000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR32DD14",        336, F_AVR8X, {0x1E, 0x95, 0x3B},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7000, 0x1000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR32DD20",        337, F_AVR8X, {0x1E, 0x95, 0x3A},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7000, 0x1000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR32DA28",        338, F_AVR8X, {0x1E, 0x95, 0x34},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  41, vtab_avr128da28}, // atdf, avrdude
  {"AVR32DB28",        339, F_AVR8X, {0x1E, 0x95, 0x37},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  42, vtab_avr128db28}, // atdf, avrdude
  {"AVR32DD28",        340, F_AVR8X, {0x1E, 0x95, 0x39},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7000, 0x1000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR32EA28",        341, F_AVR8X, {0x1E, 0x95, 0x3E},       0, 0x08000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR32DA32",        342, F_AVR8X, {0x1E, 0x95, 0x33},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  44, vtab_avr128da32}, // atdf, avrdude
  {"AVR32DB32",        343, F_AVR8X, {0x1E, 0x95, 0x36},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  44, vtab_avr128db32}, // atdf, avrdude
  {"AVR32DD32",        344, F_AVR8X, {0x1E, 0x95, 0x38},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x7000, 0x1000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR32EA32",        345, F_AVR8X, {0x1E, 0x95, 0x3D},       0, 0x08000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR32DA48",        346, F_AVR8X, {0x1E, 0x95, 0x32},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  58, vtab_avr128da48}, // atdf, avrdude
  {"AVR32DB48",        347, F_AVR8X, {0x1E, 0x95, 0x35},       0, 0x08000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x7000, 0x1000, 16,  4,  61, vtab_avr128db48}, // atdf, avrdude
  {"AVR32EA48",        348, F_AVR8X, {0x1E, 0x95, 0x3C},       0, 0x08000, 0x040,  1,      0, 0x01400, 0x0200,  8,     -1,     -1, -1, -1,   0,            NULL}, // avrdude
  {"AVR64DD14",        349, F_AVR8X, {0x1E, 0x96, 0x1D},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x6000, 0x2000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR64DD20",        350, F_AVR8X, {0x1E, 0x96, 0x1C},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x6000, 0x2000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR64DA28",        351, F_AVR8X, {0x1E, 0x96, 0x15},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  41, vtab_avr128da28}, // atdf, avrdude
  {"AVR64DB28",        352, F_AVR8X, {0x1E, 0x96, 0x19},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  42, vtab_avr128db28}, // atdf, avrdude
  {"AVR64DD28",        353, F_AVR8X, {0x1E, 0x96, 0x1B},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x6000, 0x2000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR64EA28",        354, F_AVR8X, {0x1E, 0x96, 0x20},       0, 0x10000, 0x080,  1,      0, 0x01400, 0x0200,  8, 0x6800, 0x1800, 16,  4,  37,  vtab_avr64ea32}, // atdf, avrdude
  {"AVR64DA32",        355, F_AVR8X, {0x1E, 0x96, 0x14},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  44, vtab_avr128da32}, // atdf, avrdude
  {"AVR64DB32",        356, F_AVR8X, {0x1E, 0x96, 0x18},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  44, vtab_avr128db32}, // atdf, avrdude
  {"AVR64DD32",        357, F_AVR8X, {0x1E, 0x96, 0x1A},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0100,  1, 0x6000, 0x2000, 16,  4,  36,  vtab_avr64dd32}, // atdf, avrdude
  {"AVR64EA32",        358, F_AVR8X, {0x1E, 0x96, 0x1F},       0, 0x10000, 0x080,  1,      0, 0x01400, 0x0200,  8, 0x6800, 0x1800, 16,  4,  37,  vtab_avr64ea32}, // atdf, avrdude
  {"AVR64DA48",        359, F_AVR8X, {0x1E, 0x96, 0x13},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  58, vtab_avr128da48}, // atdf, avrdude
  {"AVR64DB48",        360, F_AVR8X, {0x1E, 0x96, 0x17},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  61, vtab_avr128db48}, // atdf, avrdude
  {"AVR64EA48",        361, F_AVR8X, {0x1E, 0x96, 0x1E},       0, 0x10000, 0x080,  1,      0, 0x01400, 0x0200,  8, 0x6800, 0x1800, 16,  4,  45,  vtab_avr64ea48}, // atdf, avrdude
  {"AVR64DA64",        362, F_AVR8X, {0x1E, 0x96, 0x12},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  64, vtab_avr128da64}, // atdf, avrdude
  {"AVR64DB64",        363, F_AVR8X, {0x1E, 0x96, 0x16},       0, 0x10000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x6000, 0x2000, 16,  4,  65, vtab_avr128db64}, // atdf, avrdude
  {"AVR128DA28",       364, F_AVR8X, {0x1E, 0x97, 0x0A},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  41, vtab_avr128da28}, // atdf, avrdude
  {"AVR128DB28",       365, F_AVR8X, {0x1E, 0x97, 0x0E},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  42, vtab_avr128db28}, // atdf, avrdude
  {"AVR128DA32",       366, F_AVR8X, {0x1E, 0x97, 0x09},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  44, vtab_avr128da32}, // atdf, avrdude
  {"AVR128DB32",       367, F_AVR8X, {0x1E, 0x97, 0x0D},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  44, vtab_avr128db32}, // atdf, avrdude
  {"AVR128DA48",       368, F_AVR8X, {0x1E, 0x97, 0x08},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  58, vtab_avr128da48}, // atdf, avrdude
  {"AVR128DB48",       369, F_AVR8X, {0x1E, 0x97, 0x0C},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  61, vtab_avr128db48}, // atdf, avrdude
  {"AVR128DA64",       370, F_AVR8X, {0x1E, 0x97, 0x07},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  64, vtab_avr128da64}, // atdf, avrdude
  {"AVR128DB64",       371, F_AVR8X, {0x1E, 0x97, 0x0B},       0, 0x20000, 0x200,  1,      0, 0x01400, 0x0200,  1, 0x4000, 0x4000, 16,  4,  65, vtab_avr128db64}, // atdf, avrdude
};

const char * const vtab_attiny9[vts_attiny9] = { // ATtiny9, ATtiny4
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "TIM0_CAPT",                  //   3: Timer 0 Capture Event
  "TIM0_OVF",                   //   4: Timer 0 Overflow
  "TIM0_COMPA",                 //   5: Timer 0 Compare Match A
  "TIM0_COMPB",                 //   6: Timer 0 Compare Match B
  "ANA_COMP",                   //   7: Analog Comparator
  "WDT",                        //   8: Watchdog Time-out
  "VLM",                        //   9: Vcc Voltage Level Monitor
};

const char * const vtab_attiny10[vts_attiny10] = { // ATtiny10, ATtiny5
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "TIM0_CAPT",                  //   3: Timer 0 Capture Event
  "TIM0_OVF",                   //   4: Timer 0 Overflow
  "TIM0_COMPA",                 //   5: Timer 0 Compare Match A
  "TIM0_COMPB",                 //   6: Timer 0 Compare Match B
  "ANA_COMP",                   //   7: Analog Comparator
  "WDT",                        //   8: Watchdog Time-out
  "VLM",                        //   9: Vcc Voltage Level Monitor
  "ADC",                        //  10: ADC Conversion Complete
};

const char * const vtab_attiny20[vts_attiny20] = { // ATtiny20
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "WDT",                        //   4: Watchdog Time-out
  "TIM1_CAPT",                  //   5: Timer 1 Capture Event
  "TIM1_COMPA",                 //   6: Timer 1 Compare Match A
  "TIM1_COMPB",                 //   7: Timer 1 Compare Match B
  "TIM1_OVF",                   //   8: Timer 1 Overflow
  "TIM0_COMPA",                 //   9: Timer 0 Compare Match A
  "TIM0_COMPB",                 //  10: Timer 0 Compare Match B
  "TIM0_OVF",                   //  11: Timer 0 Overflow
  "ANA_COMP",                   //  12: Analog Comparator
  "ADC_ADC",                    //  13: Conversion Complete
  "TWI_SLAVE",                  //  14: 2-Wire Interface Periphery
  "SPI",                        //  15: SPI Serial Peripheral Interface
  "QTRIP",                      //  16: Touch Sensing
};

const char * const vtab_attiny40[vts_attiny40] = { // ATtiny40
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "PCINT2",                     //   4: Pin Change Interrupt 2
  "WDT",                        //   5: Watchdog Time-out
  "TIM1_CAPT",                  //   6: Timer 1 Capture Event
  "TIM1_COMPA",                 //   7: Timer 1 Compare Match A
  "TIM1_COMPB",                 //   8: Timer 1 Compare Match B
  "TIM1_OVF",                   //   9: Timer 1 Overflow
  "TIM0_COMPA",                 //  10: Timer 0 Compare Match A
  "TIM0_COMPB",                 //  11: Timer 0 Compare Match B
  "TIM0_OVF",                   //  12: Timer 0 Overflow
  "ANA_COMP",                   //  13: Analog Comparator
  "ADC",                        //  14: ADC Conversion Complete
  "TWI_SLAVE",                  //  15: 2-Wire Interface Periphery
  "SPI",                        //  16: SPI Serial Peripheral Interface
  "QTRIP",                      //  17: Touch Sensing
};

const char * const vtab_attiny104[vts_attiny104] = { // ATtiny104, ATtiny102
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "TIM0_CAPT",                  //   4: Timer 0 Capture Event
  "TIM0_OVF",                   //   5: Timer 0 Overflow
  "TIM0_COMPA",                 //   6: Timer 0 Compare Match A
  "TIM0_COMPB",                 //   7: Timer 0 Compare Match B
  "ANA_COMP",                   //   8: Analog Comparator
  "WDT",                        //   9: Watchdog Time-out
  "VLM",                        //  10: Vcc Voltage Level Monitor
  "ADC",                        //  11: ADC Conversion Complete
  "USART_RXS",                  //  12: USART Receive Start
  "USART_RXC",                  //  13: USART Receive Complete
  "USART_DRE",                  //  14: USART Data Register Empty
  "USART_TXC",                  //  15: USART Transmit Complete
};

const char * const vtab_attiny11[vts_attiny11] = { // ATtiny11
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "IO_PINS",                    //   2: External Interrupt
  "TIMER0_OVF",                 //   3: Timer 0 Overflow
  "ANA_COMP",                   //   4: Analog Comparator
};

const char * const vtab_attiny12[vts_attiny12] = { // ATtiny12
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "IO_PINS",                    //   2: External Interrupt
  "TIMER0_OVF",                 //   3: Timer 0 Overflow
  "EE_RDY",                     //   4: EEPROM Ready
  "ANA_COMP",                   //   5: Analog Comparator
};

const char * const vtab_attiny13a[vts_attiny13a] = { // ATtiny13A, ATtiny13
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "TIM0_OVF",                   //   3: Timer 0 Overflow
  "EE_RDY",                     //   4: EEPROM Ready
  "ANA_COMP",                   //   5: Analog Comparator
  "TIM0_COMPA",                 //   6: Timer 0 Compare Match A
  "TIM0_COMPB",                 //   7: Timer 0 Compare Match B
  "WDT",                        //   8: Watchdog Time-out
  "ADC",                        //   9: ADC Conversion Complete
};

const char * const vtab_attiny15[vts_attiny15] = { // ATtiny15
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "IO_PINS",                    //   2: External Interrupt
  "TIMER1_COMP",                //   3: Timer 1 Compare
  "TIMER1_OVF",                 //   4: Timer 1 Overflow
  "TIMER0_OVF",                 //   5: Timer 0 Overflow
  "EE_RDY",                     //   6: EEPROM Ready
  "ANA_COMP",                   //   7: Analog Comparator
  "ADC",                        //   8: ADC Conversion Complete
};

const char * const vtab_attiny22[vts_attiny22] = { // ATtiny22, AT90S2343, AT90S2323
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "TIMER0_OVF0",                //   2: Timer 0 Overflow
};

const char * const vtab_attiny26[vts_attiny26] = { // ATtiny26
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "IO_PINS",                    //   2: External Interrupt
  "TIMER1_CMPA",                //   3: Timer 1 Compare Match A
  "TIMER1_CMPB",                //   4: Timer 1 Compare Match B
  "TIMER1_OVF1",                //   5: Timer 1 Overflow
  "TIMER0_OVF0",                //   6: Timer 0 Overflow
  "USI_STRT",                   //   7: USI Start Condition
  "USI_OVF",                    //   8: USI Overflow
  "EE_RDY",                     //   9: EEPROM Ready
  "ANA_COMP",                   //  10: Analog Comparator
  "ADC",                        //  11: ADC Conversion Complete
};

const char * const vtab_attiny28[vts_attiny28] = { // ATtiny28
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "LOW_LEVEL_IO_PINS",          //   3: Low-level Input
  "TIMER0_OVF",                 //   4: Timer 0 Overflow
  "ANA_COMP",                   //   5: Analog Comparator
};

const char * const vtab_attiny43u[vts_attiny43u] = { // ATtiny43U
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "WDT",                        //   4: Watchdog Time-out
  "TIM1_COMPA",                 //   5: Timer 1 Compare Match A
  "TIM1_COMPB",                 //   6: Timer 1 Compare Match B
  "TIM1_OVF",                   //   7: Timer 1 Overflow
  "TIM0_COMPA",                 //   8: Timer 0 Compare Match A
  "TIM0_COMPB",                 //   9: Timer 0 Compare Match B
  "TIM0_OVF",                   //  10: Timer 0 Overflow
  "ANA_COMP",                   //  11: Analog Comparator
  "ADC",                        //  12: ADC Conversion Complete
  "EE_RDY",                     //  13: EEPROM Ready
  "USI_START",                  //  14: USI Start Condition
  "USI_OVF",                    //  15: USI Overflow
};

const char * const vtab_attiny84a[vts_attiny84a] = { // ATtiny84A, ATtiny84, ATtiny44A, ATtiny44, ATtiny24A, ATtiny24
  "RESET",                      //   0: Reset (various reasons)
  "EXT_INT0",                   //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "WDT",                        //   4: Watchdog Time-out
  "TIM1_CAPT",                  //   5: Timer 1 Capture Event
  "TIM1_COMPA",                 //   6: Timer 1 Compare Match A
  "TIM1_COMPB",                 //   7: Timer 1 Compare Match B
  "TIM1_OVF",                   //   8: Timer 1 Overflow
  "TIM0_COMPA",                 //   9: Timer 0 Compare Match A
  "TIM0_COMPB",                 //  10: Timer 0 Compare Match B
  "TIM0_OVF",                   //  11: Timer 0 Overflow
  "ANA_COMP",                   //  12: Analog Comparator
  "ADC",                        //  13: ADC Conversion Complete
  "EE_RDY",                     //  14: EEPROM Ready
  "USI_STR",                    //  15: USI Start Condition
  "USI_OVF",                    //  16: USI Overflow
};

const char * const vtab_attiny85[vts_attiny85] = { // ATtiny85, ATtiny45, ATtiny25
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "TIMER1_COMPA",               //   3: Timer 1 Compare Match A
  "TIMER1_OVF",                 //   4: Timer 1 Overflow
  "TIMER0_OVF",                 //   5: Timer 0 Overflow
  "EE_RDY",                     //   6: EEPROM Ready
  "ANA_COMP",                   //   7: Analog Comparator
  "ADC",                        //   8: ADC Conversion Complete
  "TIMER1_COMPB",               //   9: Timer 1 Compare Match B
  "TIMER0_COMPA",               //  10: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  11: Timer 0 Compare Match B
  "WDT",                        //  12: Watchdog Time-out
  "USI_START",                  //  13: USI Start Condition
  "USI_OVF",                    //  14: USI Overflow
};

const char * const vtab_attiny88[vts_attiny88] = { // ATtiny88, ATtiny48
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "PCINT3",                     //   6: Pin Change Interrupt 3
  "WDT",                        //   7: Watchdog Time-out
  "TIMER1_CAPT",                //   8: Timer 1 Capture Event
  "TIMER1_COMPA",               //   9: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  10: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  11: Timer 1 Overflow
  "TIMER0_COMPA",               //  12: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  13: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  14: Timer 0 Overflow
  "SPI_STC",                    //  15: SPI Serial Transfer Complete
  "ADC",                        //  16: ADC Conversion Complete
  "EE_RDY",                     //  17: EEPROM Ready
  "ANALOG_COMP",                //  18: Analog Comparator
  "TWI",                        //  19: 2-Wire Interface
};

const char * const vtab_attiny167[vts_attiny167] = { // ATtiny167, ATtiny87, ATA664251, ATA6617C, ATA6616C, ATA5505
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "WDT",                        //   5: Watchdog Time-out
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMPA",               //  10: Timer 0 Compare Match A
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "LIN_TC",                     //  12: LIN Transfer Complete
  "LIN_ERR",                    //  13: LIN Error
  "SPI_STC",                    //  14: SPI Serial Transfer Complete
  "ADC",                        //  15: ADC Conversion Complete
  "EE_RDY",                     //  16: EEPROM Ready
  "ANA_COMP",                   //  17: Analog Comparator
  "USI_START",                  //  18: USI Start Condition
  "USI_OVF",                    //  19: USI Overflow
};

const char * const vtab_attiny828[vts_attiny828] = { // ATtiny828
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "PCINT3",                     //   6: Pin Change Interrupt 3
  "WDT",                        //   7: Watchdog Time-out
  "TIMER1_CAPT",                //   8: Timer 1 Capture Event
  "TIMER1_COMPA",               //   9: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  10: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  11: Timer 1 Overflow
  "TIMER0_COMPA",               //  12: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  13: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  14: Timer 0 Overflow
  "SPI_STC",                    //  15: SPI Serial Transfer Complete
  "USART_START",                //  16: USART Start
  "USART_RX",                   //  17: USART Receive Complete
  "USART_UDRE",                 //  18: USART Data Register Empty
  "USART_TX",                   //  19: USART Transmit Complete
  "ADC",                        //  20: ADC Conversion Complete
  "EE_READY",                   //  21: EEPROM Ready
  "ANALOG_COMP",                //  22: Analog Comparator
  "TWI_SLAVE",                  //  23: 2-Wire Interface Periphery
  "SPM_Ready",                  //  24: Store Program Memory Ready
  "QTRIP",                      //  25: Touch Sensing
};

const char * const vtab_attiny841[vts_attiny841] = { // ATtiny841, ATtiny441
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "WDT",                        //   4: Watchdog Time-out
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_COMPA",               //   9: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  10: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "ANA_COMP0",                  //  12: Analog Comparator 0
  "ADC",                        //  13: ADC Conversion Complete
  "EE_RDY",                     //  14: EEPROM Ready
  "ANA_COMP1",                  //  15: Analog Comparator 1
  "TIMER2_CAPT",                //  16: Timer 2 Capture Event
  "TIMER2_COMPA",               //  17: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  18: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  19: Timer 2 Overflow
  "SPI",                        //  20: SPI Serial Peripheral Interface
  "USART0_START",               //  21: USART 0 Receive Start
  "USART0_RX",                  //  22: USART 0 Receive Complete
  "USART0_UDRE",                //  23: USART 0 Data Register Empty
  "USART0_TX",                  //  24: USART 0 Transmit Complete
  "USART1_START",               //  25: USART 1 Receive Start
  "USART1_RX",                  //  26: USART 1 Receive Complete
  "USART1_UDRE",                //  27: USART 1 Data Register Empty
  "USART1_TX",                  //  28: USART 1 Transmit Complete
  "TWI_SLAVE",                  //  29: 2-Wire Interface Periphery
};

const char * const vtab_attiny861a[vts_attiny861a] = { // ATtiny861A, ATtiny861, ATtiny461A, ATtiny461, ATtiny261A, ATtiny261
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT",                      //   2: Pin Change Interrupt
  "TIMER1_COMPA",               //   3: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   4: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   5: Timer 1 Overflow
  "TIMER0_OVF",                 //   6: Timer 0 Overflow
  "USI_START",                  //   7: USI Start Condition
  "USI_OVF",                    //   8: USI Overflow
  "EE_RDY",                     //   9: EEPROM Ready
  "ANA_COMP",                   //  10: Analog Comparator
  "ADC",                        //  11: ADC Conversion Complete
  "WDT",                        //  12: Watchdog Time-out
  "INT1",                       //  13: External Interrupt 1
  "TIMER0_COMPA",               //  14: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  15: Timer 0 Compare Match B
  "TIMER0_CAPT",                //  16: Timer 0 Capture Event
  "TIMER1_COMPD",               //  17: Timer 1 Compare Match D
  "FAULT_PROTECTION",           //  18: Timer 1 Fault Protection
};

const char * const vtab_attiny1634[vts_attiny1634] = { // ATtiny1634
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "PCINT2",                     //   4: Pin Change Interrupt 2
  "WDT",                        //   5: Watchdog Time-out
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMPA",               //  10: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  11: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  12: Timer 0 Overflow
  "ANA_COMP",                   //  13: Analog Comparator
  "ADC_READY",                  //  14: ADC Conversion Complete
  "USART0_START",               //  15: USART 0 Receive Start
  "USART0_RXC",                 //  16: USART 0 Receive Complete
  "USART0_UDRE",                //  17: USART 0 Data Register Empty
  "USART0_TXC",                 //  18: USART 0 Transmit Complete
  "USART1_START",               //  19: USART 1 Receive Start
  "USART1_RXC",                 //  20: USART 1 Receive Complete
  "USART1_UDRE",                //  21: USART 1 Data Register Empty
  "USART1_TXC",                 //  22: USART 1 Transmit Complete
  "USI_START",                  //  23: USI Start Condition
  "USI_OVERFLOW",               //  24: USI Overflow
  "TWI/TWI_SLAVE",              //  25: 2-Wire Interface/2-Wire Interface Periphery
  "EE_RDY",                     //  26: EEPROM Ready
  "QTRIP",                      //  27: Touch Sensing
};

const char * const vtab_attiny2313[vts_attiny2313] = { // ATtiny2313
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT",                //   3: Timer 1 Capture Event
  "TIMER1_COMPA",               //   4: Timer 1 Compare Match A
  "TIMER1_OVF",                 //   5: Timer 1 Overflow
  "TIMER0_OVF",                 //   6: Timer 0 Overflow
  "USART_RX",                   //   7: USART Receive Complete
  "USART_UDRE",                 //   8: USART Data Register Empty
  "USART_TX",                   //   9: USART Transmit Complete
  "ANA_COMP",                   //  10: Analog Comparator
  "PCINT",                      //  11: Pin Change Interrupt
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER0_COMPA",               //  13: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  14: Timer 0 Compare Match B
  "USI_START",                  //  15: USI Start Condition
  "USI_OVERFLOW",               //  16: USI Overflow
  "EEPROM_Ready",               //  17: EEPROM Ready
  "WDT_OVERFLOW",               //  18: Watchdog Timer Overflow
};

const char * const vtab_attiny4313[vts_attiny4313] = { // ATtiny4313, ATtiny2313A
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT",                //   3: Timer 1 Capture Event
  "TIMER1_COMPA",               //   4: Timer 1 Compare Match A
  "TIMER1_OVF",                 //   5: Timer 1 Overflow
  "TIMER0_OVF",                 //   6: Timer 0 Overflow
  "USART_RX",                   //   7: USART Receive Complete
  "USART_UDRE",                 //   8: USART Data Register Empty
  "USART_TX",                   //   9: USART Transmit Complete
  "ANA_COMP",                   //  10: Analog Comparator
  "PCINT_B",                    //  11: Pin Change Interrupt B
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER0_COMPA",               //  13: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  14: Timer 0 Compare Match B
  "USI_START",                  //  15: USI Start Condition
  "USI_OVERFLOW",               //  16: USI Overflow
  "EEPROM_Ready",               //  17: EEPROM Ready
  "WDT_OVERFLOW",               //  18: Watchdog Timer Overflow
  "PCINT_A",                    //  19: Pin Change Interrupt A
  "PCINT_D",                    //  20: Pin Change Interrupt D
};

const char * const vtab_atmega8a[vts_atmega8a] = { // ATmega8A, ATmega8
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER2_COMP",                //   3: Timer 2 Compare Match
  "TIMER2_OVF",                 //   4: Timer 2 Overflow
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_OVF",                 //   9: Timer 0 Overflow
  "SPI_STC",                    //  10: SPI Serial Transfer Complete
  "USART_RXC",                  //  11: USART Receive Complete
  "USART_UDRE",                 //  12: USART Data Register Empty
  "USART_TXC",                  //  13: USART Transmit Complete
  "ADC",                        //  14: ADC Conversion Complete
  "EE_RDY",                     //  15: EEPROM Ready
  "ANA_COMP",                   //  16: Analog Comparator
  "TWI",                        //  17: 2-Wire Interface
  "SPM_RDY",                    //  18: Store Program Memory Ready
};

const char * const vtab_atmega16a[vts_atmega16a] = { // ATmega16A, ATmega16
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER2_COMP",                //   3: Timer 2 Compare Match
  "TIMER2_OVF",                 //   4: Timer 2 Overflow
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_OVF",                 //   9: Timer 0 Overflow
  "SPI_STC",                    //  10: SPI Serial Transfer Complete
  "USART_RXC",                  //  11: USART Receive Complete
  "USART_UDRE",                 //  12: USART Data Register Empty
  "USART_TXC",                  //  13: USART Transmit Complete
  "ADC",                        //  14: ADC Conversion Complete
  "EE_RDY",                     //  15: EEPROM Ready
  "ANA_COMP",                   //  16: Analog Comparator
  "TWI",                        //  17: 2-Wire Interface
  "INT2",                       //  18: External Interrupt 2
  "TIMER0_COMP",                //  19: Timer 0 Compare Match
  "SPM_RDY",                    //  20: Store Program Memory Ready
};

const char * const vtab_atmega16hva[vts_atmega16hva] = { // ATmega16HVA, ATmega8HVA
  "RESET",                      //   0: Reset (various reasons)
  "BPINT",                      //   1: Battery Protection Interrupt
  "VREGMON",                    //   2: Voltage Regulator Monitor
  "INT0",                       //   3: External Interrupt 0
  "INT1",                       //   4: External Interrupt 1
  "INT2",                       //   5: External Interrupt 2
  "WDT",                        //   6: Watchdog Time-out
  "TIMER1_IC",                  //   7: Timer 1 Input Capture
  "TIMER1_COMPA",               //   8: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   9: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  10: Timer 1 Overflow
  "TIMER0_IC",                  //  11: Timer 0 Capture Event
  "TIMER0_COMPA",               //  12: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  13: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  14: Timer 0 Overflow
  "SPI_STC",                    //  15: SPI Serial Transfer Complete
  "VADC",                       //  16: Voltage ADC Conversion Complete
  "CCADC_CONV",                 //  17: Coulomb Counter ADC Conversion Complete
  "CCADC_REG_CUR",              //  18: Coloumb Counter ADC Regular Current
  "CCADC_ACC",                  //  19: Coloumb Counter ADC Accumulator
  "EE_READY",                   //  20: EEPROM Ready
};

const char * const vtab_atmega16hva2[vts_atmega16hva2] = { // ATmega16HVA2
  "RESET",                      //   0: Reset (various reasons)
  "BPINT",                      //   1: Battery Protection Interrupt
  "VREGMON",                    //   2: Voltage Regulator Monitor
  "INT0",                       //   3: External Interrupt 0
  "INT1",                       //   4: External Interrupt 1
  "INT2",                       //   5: External Interrupt 2
  "PCINT0",                     //   6: Pin Change Interrupt 0
  "WDT",                        //   7: Watchdog Time-out
  "TIMER1_IC",                  //   8: Timer 1 Input Capture
  "TIMER1_COMPA",               //   9: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  10: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  11: Timer 1 Overflow
  "TIMER0_IC",                  //  12: Timer 0 Capture Event
  "TIMER0_COMPA",               //  13: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  14: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  15: Timer 0 Overflow
  "SPI_STC",                    //  16: SPI Serial Transfer Complete
  "VADC",                       //  17: Voltage ADC Conversion Complete
  "CCADC_CONV",                 //  18: Coulomb Counter ADC Conversion Complete
  "CCADC_REG_CUR",              //  19: Coloumb Counter ADC Regular Current
  "CCADC_ACC",                  //  20: Coloumb Counter ADC Accumulator
  "EE_READY",                   //  21: EEPROM Ready
};

const char * const vtab_atmega32hvbrevb[vts_atmega32hvbrevb] = { // ATmega32HVBrevB, ATmega32HVB, ATmega16HVBrevB, ATmega16HVB
  "RESET",                      //   0: Reset (various reasons)
  "BPINT",                      //   1: Battery Protection Interrupt
  "VREGMON",                    //   2: Voltage Regulator Monitor
  "INT0",                       //   3: External Interrupt 0
  "INT1",                       //   4: External Interrupt 1
  "INT2",                       //   5: External Interrupt 2
  "INT3",                       //   6: External Interrupt 3
  "PCINT0",                     //   7: Pin Change Interrupt 0
  "PCINT1",                     //   8: Pin Change Interrupt 1
  "WDT",                        //   9: Watchdog Time-out
  "BGSCD",                      //  10: Bandgap Buffer Short Circuit Detected
  "CHDET",                      //  11: Charger Detect
  "TIMER1_IC",                  //  12: Timer 1 Input Capture
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_IC",                  //  16: Timer 0 Capture Event
  "TIMER0_COMPA",               //  17: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  18: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  19: Timer 0 Overflow
  "TWIBUSCD",                   //  20: 2-Wire Interface Bus Connect/Disconnect
  "TWI",                        //  21: 2-Wire Interface
  "SPI_STC",                    //  22: SPI Serial Transfer Complete
  "VADC",                       //  23: Voltage ADC Conversion Complete
  "CCADC_CONV",                 //  24: Coulomb Counter ADC Conversion Complete
  "CCADC_REG_CUR",              //  25: Coloumb Counter ADC Regular Current
  "CCADC_ACC",                  //  26: Coloumb Counter ADC Accumulator
  "EE_READY",                   //  27: EEPROM Ready
  "SPM",                        //  28: SPM Ready
};

const char * const vtab_atmega32u2[vts_atmega32u2] = { // ATmega32U2, ATmega16U2, ATmega8U2, AT90USB162, AT90USB82
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "PCINT1",                     //  10: Pin Change Interrupt 1
  "USB_GEN",                    //  11: USB General
  "USB_COM",                    //  12: USB Endpoint/Pipe Interrupt Communication Request
  "WDT",                        //  13: Watchdog Time-out
  "TIMER1_CAPT",                //  14: Timer 1 Capture Event
  "TIMER1_COMPA",               //  15: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  16: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  17: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  18: Timer 1 Overflow
  "TIMER0_COMPA",               //  19: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  20: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  21: Timer 0 Overflow
  "SPI_STC",                    //  22: SPI Serial Transfer Complete
  "USART1_RX",                  //  23: USART 1 Receive Complete
  "USART1_UDRE",                //  24: USART 1 Data Register Empty
  "USART1_TX",                  //  25: USART 1 Transmit Complete
  "ANALOG_COMP",                //  26: Analog Comparator
  "EE_READY",                   //  27: EEPROM Ready
  "SPM_READY",                  //  28: Store Program Memory Ready
};

const char * const vtab_atmega32u4[vts_atmega32u4] = { // ATmega32U4, ATmega16U4
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "Reserved1",                  //   5: Reserved 1
  "Reserved2",                  //   6: Reserved 2
  "INT6",                       //   7: External Interrupt 6
  "Reserved3",                  //   8: Reserved 3
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "USB_GEN",                    //  10: USB General
  "USB_COM",                    //  11: USB Endpoint/Pipe Interrupt Communication Request
  "WDT",                        //  12: Watchdog Time-out
  "Reserved4",                  //  13: Reserved 4
  "Reserved5",                  //  14: Reserved 5
  "Reserved6",                  //  15: Reserved 6
  "TIMER1_CAPT",                //  16: Timer 1 Capture Event
  "TIMER1_COMPA",               //  17: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  18: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  19: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  20: Timer 1 Overflow
  "TIMER0_COMPA",               //  21: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  22: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  23: Timer 0 Overflow
  "SPI_STC",                    //  24: SPI Serial Transfer Complete
  "USART1_RX",                  //  25: USART 1 Receive Complete
  "USART1_UDRE",                //  26: USART 1 Data Register Empty
  "USART1_TX",                  //  27: USART 1 Transmit Complete
  "ANALOG_COMP",                //  28: Analog Comparator
  "ADC",                        //  29: ADC Conversion Complete
  "EE_READY",                   //  30: EEPROM Ready
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  34: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "TWI",                        //  36: 2-Wire Interface
  "SPM_READY",                  //  37: Store Program Memory Ready
  "TIMER4_COMPA",               //  38: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  39: Timer 4 Compare Match B
  "TIMER4_COMPD",               //  40: Timer 4 Compare Match D
  "TIMER4_OVF",                 //  41: Timer 4 Overflow
  "TIMER4_FPF",                 //  42: Timer 4 Fault Protection
};

const char * const vtab_atmega32u6[vts_atmega32u6] = { // ATmega32U6, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "USB_GEN",                    //  10: USB General
  "USB_COM",                    //  11: USB Endpoint/Pipe Interrupt Communication Request
  "WDT",                        //  12: Watchdog Time-out
  "TIMER2_COMPA",               //  13: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  14: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  15: Timer 2 Overflow
  "TIMER1_CAPT",                //  16: Timer 1 Capture Event
  "TIMER1_COMPA",               //  17: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  18: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  19: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  20: Timer 1 Overflow
  "TIMER0_COMPA",               //  21: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  22: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  23: Timer 0 Overflow
  "SPI_STC",                    //  24: SPI Serial Transfer Complete
  "USART1_RX",                  //  25: USART 1 Receive Complete
  "USART1_UDRE",                //  26: USART 1 Data Register Empty
  "USART1_TX",                  //  27: USART 1 Transmit Complete
  "ANALOG_COMP",                //  28: Analog Comparator
  "ADC",                        //  29: ADC Conversion Complete
  "EE_READY",                   //  30: EEPROM Ready
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  34: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "TWI",                        //  36: 2-Wire Interface
  "SPM_READY",                  //  37: Store Program Memory Ready
};

const char * const vtab_atmega64m1[vts_atmega64m1] = { // ATmega64M1, ATmega64C1, ATmega32M1, ATmega32C1, ATmega16M1
  "RESET",                      //   0: Reset (various reasons)
  "ANACOMP0",                   //   1: Analog Comparator 0
  "ANACOMP1",                   //   2: Analog Comparator 1
  "ANACOMP2",                   //   3: Analog Comparator 2
  "ANACOMP3",                   //   4: Analog Comparator 3
  "PSC_FAULT",                  //   5: PSC Fault
  "PSC_EC",                     //   6: PSC End of Cycle
  "INT0",                       //   7: External Interrupt 0
  "INT1",                       //   8: External Interrupt 1
  "INT2",                       //   9: External Interrupt 2
  "INT3",                       //  10: External Interrupt 3
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  14: Timer 1 Overflow
  "TIMER0_COMPA",               //  15: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  16: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "CAN_INT",                    //  18: CAN MOB, Burst, General Errors
  "CAN_TOVF",                   //  19: CAN Timer Overflow
  "LIN_TC",                     //  20: LIN Transfer Complete
  "LIN_ERR",                    //  21: LIN Error
  "PCINT0",                     //  22: Pin Change Interrupt 0
  "PCINT1",                     //  23: Pin Change Interrupt 1
  "PCINT2",                     //  24: Pin Change Interrupt 2
  "PCINT3",                     //  25: Pin Change Interrupt 3
  "SPI_STC",                    //  26: SPI Serial Transfer Complete
  "ADC",                        //  27: ADC Conversion Complete
  "WDT",                        //  28: Watchdog Time-out
  "EE_READY",                   //  29: EEPROM Ready
  "SPM_READY",                  //  30: Store Program Memory Ready
};

const char * const vtab_atmega64hve2[vts_atmega64hve2] = { // ATmega64HVE2, ATmega64HVE
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "WDT",                        //   4: Watchdog Time-out
  "WAKEUP",                     //   5: Wake Up
  "TIMER1_IC",                  //   6: Timer 1 Input Capture
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_IC",                  //  10: Timer 0 Capture Event
  "TIMER0_COMPA",               //  11: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  12: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  13: Timer 0 Overflow
  "LIN_STATUS",                 //  14: Local Interconnect Network Status
  "LIN_ERROR",                  //  15: Local Interconnect Network Error
  "SPI_STC",                    //  16: SPI Serial Transfer Complete
  "VADC_CONV",                  //  17: Versatile Analog to Digital Conversion
  "VADC_ACC",                   //  18: Versatile Analog to Digital Compare or Capture
  "CADC_CONV",                  //  19: C-ADC Instantaneous Conversion Complete
  "CADC_REG_CUR",               //  20: C-ADC Regular Current
  "CADC_ACC",                   //  21: C-ADC Accumulated Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "SPM",                        //  23: SPM Ready
  "PLL",                        //  24: PLL
};

const char * const vtab_atmega103[vts_atmega103] = { // ATmega103
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "TIMER2_COMP",                //   9: Timer 2 Compare Match
  "TIMER2_OVF",                 //  10: Timer 2 Overflow
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  14: Timer 1 Overflow
  "TIMER0_COMP",                //  15: Timer 0 Compare Match
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI_STC",                    //  17: SPI Serial Transfer Complete
  "UART_RX",                    //  18: UART Receive Complete
  "UART_UDRE",                  //  19: UART Data Register Empty
  "UART_TX",                    //  20: UART Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
};

const char * const vtab_atmega128a[vts_atmega128a] = { // ATmega128A, ATmega128, ATmega64A, ATmega64
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "TIMER2_COMP",                //   9: Timer 2 Compare Match
  "TIMER2_OVF",                 //  10: Timer 2 Overflow
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  14: Timer 1 Overflow
  "TIMER0_COMP",                //  15: Timer 0 Compare Match
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI_STC",                    //  17: SPI Serial Transfer Complete
  "USART0_RX",                  //  18: USART 0 Receive Complete
  "USART0_UDRE",                //  19: USART 0 Data Register Empty
  "USART0_TX",                  //  20: USART 0 Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
  "TIMER1_COMPC",               //  24: Timer 1 Compare Match C
  "TIMER3_CAPT",                //  25: Timer 3 Capture Event
  "TIMER3_COMPA",               //  26: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  27: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  28: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  29: Timer 3 Overflow
  "USART1_RX",                  //  30: USART 1 Receive Complete
  "USART1_UDRE",                //  31: USART 1 Data Register Empty
  "USART1_TX",                  //  32: USART 1 Transmit Complete
  "TWI",                        //  33: 2-Wire Interface
  "SPM_READY",                  //  34: Store Program Memory Ready
};

const char * const vtab_atmega128rfa1[vts_atmega128rfa1] = { // ATmega128RFA1
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "PCINT1",                     //  10: Pin Change Interrupt 1
  "PCINT2",                     //  11: Pin Change Interrupt 2
  "WDT",                        //  12: Watchdog Time-out
  "TIMER2_COMPA",               //  13: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  14: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  15: Timer 2 Overflow
  "TIMER1_CAPT",                //  16: Timer 1 Capture Event
  "TIMER1_COMPA",               //  17: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  18: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  19: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  20: Timer 1 Overflow
  "TIMER0_COMPA",               //  21: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  22: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  23: Timer 0 Overflow
  "SPI_STC",                    //  24: SPI Serial Transfer Complete
  "USART0_RX",                  //  25: USART 0 Receive Complete
  "USART0_UDRE",                //  26: USART 0 Data Register Empty
  "USART0_TX",                  //  27: USART 0 Transmit Complete
  "ANALOG_COMP",                //  28: Analog Comparator
  "ADC",                        //  29: ADC Conversion Complete
  "EE_READY",                   //  30: EEPROM Ready
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  34: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "USART1_RX",                  //  36: USART 1 Receive Complete
  "USART1_UDRE",                //  37: USART 1 Data Register Empty
  "USART1_TX",                  //  38: USART 1 Transmit Complete
  "TWI",                        //  39: 2-Wire Interface
  "SPM_READY",                  //  40: Store Program Memory Ready
  "TIMER4_CAPT",                //  41: Timer 4 Capture Event
  "TIMER4_COMPA",               //  42: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  43: Timer 4 Compare Match B
  "TIMER4_COMPC",               //  44: Timer 4 Compare Match C
  "TIMER4_OVF",                 //  45: Timer 4 Overflow
  "TIMER5_CAPT",                //  46: Timer 5 Capture Event
  "TIMER5_COMPA",               //  47: Timer 5 Compare Match A
  "TIMER5_COMPB",               //  48: Timer 5 Compare Match B
  "TIMER5_COMPC",               //  49: Timer 5 Compare Match C
  "TIMER5_OVF",                 //  50: Timer 5 Overflow
  "USART2_RX",                  //  51: USART 2 Receive Complete
  "USART2_UDRE",                //  52: USART 2 Data Register Empty
  "USART2_TX",                  //  53: USART 2 Transmit Complete
  "USART3_RX",                  //  54: USART 3 Receive Complete
  "USART3_UDRE",                //  55: USART 3 Data Register Empty
  "USART3_TX",                  //  56: USART 3 Transmit Complete
  "TRX24_PLL_LOCK",             //  57: TRX24 PLL Lock
  "TRX24_PLL_UNLOCK",           //  58: TRX24 PLL Unlock
  "TRX24_RX_START",             //  59: TRX24 Receive Start
  "TRX24_RX_END",               //  60: TRX24 Receive End
  "TRX24_CCA_ED_DONE",          //  61: TRX24 CCA/ED Done
  "TRX24_XAH_AMI",              //  62: TRX24 XAH/AMI
  "TRX24_TX_END",               //  63: TRX24 Transmit End
  "TRX24_AWAKE",                //  64: TRX24 AWAKE - Transceiver is Reaching State TRX_OFF
  "SCNT_CMP1",                  //  65: Symbol Counter - Compare Match 1 Interrupt
  "SCNT_CMP2",                  //  66: Symbol Counter - Compare Match 2 Interrupt
  "SCNT_CMP3",                  //  67: Symbol Counter - Compare Match 3 Interrupt
  "SCNT_OVFL",                  //  68: Symbol Counter - Overflow Interrupt
  "SCNT_BACKOFF",               //  69: Symbol Counter - Backoff Interrupt
  "AES_READY",                  //  70: AES Engine Ready
  "BAT_LOW",                    //  71: Battery Voltage Below Threshold
};

const char * const vtab_atmega161[vts_atmega161] = { // ATmega161
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "UART0_RX",                   //  13: UART 0 Receive Complete
  "UART1_RX",                   //  14: UART 1 Receive Complete
  "UART0_UDRE",                 //  15: UART 0 Data Register Empty
  "UART1_UDRE",                 //  16: UART 1 Data Register Empty
  "UART0_TX",                   //  17: UART 0 Transmit Complete
  "UART1_TX",                   //  18: UART 1 Transmit Complete
  "EE_RDY",                     //  19: EEPROM Ready
  "ANA_COMP",                   //  20: Analog Comparator
};

const char * const vtab_atmega162[vts_atmega162] = { // ATmega162
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "PCINT0",                     //   4: Pin Change Interrupt 0
  "PCINT1",                     //   5: Pin Change Interrupt 1
  "TIMER3_CAPT",                //   6: Timer 3 Capture Event
  "TIMER3_COMPA",               //   7: Timer 3 Compare Match A
  "TIMER3_COMPB",               //   8: Timer 3 Compare Match B
  "TIMER3_OVF",                 //   9: Timer 3 Overflow
  "TIMER2_COMP",                //  10: Timer 2 Compare Match
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMP",                //  16: Timer 0 Compare Match
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "SPI_STC",                    //  18: SPI Serial Transfer Complete
  "USART0_RXC",                 //  19: USART 0 Receive Complete
  "USART1_RXC",                 //  20: USART 1 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART1_UDRE",                //  22: USART 1 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "USART1_TXC",                 //  24: USART 1 Transmit Complete
  "EE_RDY",                     //  25: EEPROM Ready
  "ANA_COMP",                   //  26: Analog Comparator
  "SPM_RDY",                    //  27: Store Program Memory Ready
};

const char * const vtab_atmega163[vts_atmega163] = { // ATmega163
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER2_COMP",                //   3: Timer 2 Compare Match
  "TIMER2_OVF",                 //   4: Timer 2 Overflow
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_OVF",                 //   9: Timer 0 Overflow
  "SPI_STC",                    //  10: SPI Serial Transfer Complete
  "UART_RX",                    //  11: UART Receive Complete
  "UART_UDRE",                  //  12: UART Data Register Empty
  "UART_TX",                    //  13: UART Transmit Complete
  "ADC",                        //  14: ADC Conversion Complete
  "EE_RDY",                     //  15: EEPROM Ready
  "ANA_COMP",                   //  16: Analog Comparator
  "TWI",                        //  17: 2-Wire Interface
};

const char * const vtab_atmega168pb[vts_atmega168pb] = { // ATmega168PB, ATmega88PB, ATmega48PB
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "WDT",                        //   6: Watchdog Time-out
  "TIMER2_COMPA",               //   7: Timer 2 Compare Match A
  "TIMER2_COMPB",               //   8: Timer 2 Compare Match B
  "TIMER2_OVF",                 //   9: Timer 2 Overflow
  "TIMER1_CAPT",                //  10: Timer 1 Capture Event
  "TIMER1_COMPA",               //  11: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  13: Timer 1 Overflow
  "TIMER0_COMPA",               //  14: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  15: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI_STC",                    //  17: SPI Serial Transfer Complete
  "USART_RX",                   //  18: USART Receive Complete
  "USART_UDRE",                 //  19: USART Data Register Empty
  "USART_TX",                   //  20: USART Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
  "TWI",                        //  24: 2-Wire Interface
  "SPM_Ready",                  //  25: Store Program Memory Ready
  "USART_START",                //  26: USART Start
};

const char * const vtab_atmega323[vts_atmega323] = { // ATmega323, ATmega32A, ATmega32
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "USART_RXC",                  //  13: USART Receive Complete
  "USART_UDRE",                 //  14: USART Data Register Empty
  "USART_TXC",                  //  15: USART Transmit Complete
  "ADC",                        //  16: ADC Conversion Complete
  "EE_RDY",                     //  17: EEPROM Ready
  "ANA_COMP",                   //  18: Analog Comparator
  "TWI",                        //  19: 2-Wire Interface
  "SPM_RDY",                    //  20: Store Program Memory Ready
};

const char * const vtab_atmega324pb[vts_atmega324pb] = { // ATmega324PB
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "PCINT0",                     //   4: Pin Change Interrupt 0
  "PCINT1",                     //   5: Pin Change Interrupt 1
  "PCINT2",                     //   6: Pin Change Interrupt 2
  "PCINT3",                     //   7: Pin Change Interrupt 3
  "WDT",                        //   8: Watchdog Time-out
  "TIMER2_COMPA",               //   9: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  10: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  17: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  18: Timer 0 Overflow
  "SPI0_STC",                   //  19: SPI 0 Serial Transfer Complete
  "USART0_RX",                  //  20: USART 0 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART0_TX",                  //  22: USART 0 Transmit Complete
  "ANALOG_COMP",                //  23: Analog Comparator
  "ADC",                        //  24: ADC Conversion Complete
  "EE_READY",                   //  25: EEPROM Ready
  "TWI0",                       //  26: 2-Wire Interface 0
  "SPM_READY",                  //  27: Store Program Memory Ready
  "USART1_RX",                  //  28: USART 1 Receive Complete
  "USART1_UDRE",                //  29: USART 1 Data Register Empty
  "USART1_TX",                  //  30: USART 1 Transmit Complete
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_OVF",                 //  34: Timer 3 Overflow
  "USART0_START",               //  35: USART 0 Receive Start
  "USART1_START",               //  36: USART 1 Receive Start
  "PCINT4",                     //  37: Pin Change Interrupt 4
  "XOSCFD",                     //  38: Crystal Failure Detect
  "PTC_EOC",                    //  39: PTC End of Conversion
  "PTC_WCOMP",                  //  40: PTC Window Comparator Mode
  "SPI1_STC",                   //  41: SPI 1 Serial Transfer Complete
  "TWI1",                       //  42: 2-Wire Interface 1
  "TIMER4_CAPT",                //  43: Timer 4 Capture Event
  "TIMER4_COMPA",               //  44: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  45: Timer 4 Compare Match B
  "TIMER4_OVF",                 //  46: Timer 4 Overflow
  "USART2_RX",                  //  47: USART 2 Receive Complete
  "USART2_UDRE",                //  48: USART 2 Data Register Empty
  "USART2_TX",                  //  49: USART 2 Transmit Complete
  "USART2_START",               //  50: USART 2 Receive Start
};

const char * const vtab_atmega328[vts_atmega328] = { // ATmega328, ATmega168
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "WDT",                        //   6: Watchdog Time-out
  "TIMER2_COMPA",               //   7: Timer 2 Compare Match A
  "TIMER2_COMPB",               //   8: Timer 2 Compare Match B
  "TIMER2_OVF",                 //   9: Timer 2 Overflow
  "TIMER1_CAPT",                //  10: Timer 1 Capture Event
  "TIMER1_COMPA",               //  11: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  13: Timer 1 Overflow
  "TIMER0_COMPA",               //  14: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  15: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI_STC",                    //  17: SPI Serial Transfer Complete
  "USART_RX",                   //  18: USART Receive Complete
  "USART_UDRE",                 //  19: USART Data Register Empty
  "USART_TX",                   //  20: USART Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
  "TWI",                        //  24: 2-Wire Interface
  "SPM_READY",                  //  25: Store Program Memory Ready
};

const char * const vtab_atmega328p[vts_atmega328p] = { // ATmega328P, ATmega168PA, ATmega168P, ATmega168A, ATmega88PA, ATmega88P, ATmega88A, ATmega88, ATmega48PA, ATmega48P, ATmega48A, ATmega48, ATA6614Q, ATA6613C, ATA6612C
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "WDT",                        //   6: Watchdog Time-out
  "TIMER2_COMPA",               //   7: Timer 2 Compare Match A
  "TIMER2_COMPB",               //   8: Timer 2 Compare Match B
  "TIMER2_OVF",                 //   9: Timer 2 Overflow
  "TIMER1_CAPT",                //  10: Timer 1 Capture Event
  "TIMER1_COMPA",               //  11: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  13: Timer 1 Overflow
  "TIMER0_COMPA",               //  14: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  15: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI_STC",                    //  17: SPI Serial Transfer Complete
  "USART_RX",                   //  18: USART Receive Complete
  "USART_UDRE",                 //  19: USART Data Register Empty
  "USART_TX",                   //  20: USART Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
  "TWI",                        //  24: 2-Wire Interface
  "SPM_Ready",                  //  25: Store Program Memory Ready
};

const char * const vtab_atmega328pb[vts_atmega328pb] = { // ATmega328PB
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "WDT",                        //   6: Watchdog Time-out
  "TIMER2_COMPA",               //   7: Timer 2 Compare Match A
  "TIMER2_COMPB",               //   8: Timer 2 Compare Match B
  "TIMER2_OVF",                 //   9: Timer 2 Overflow
  "TIMER1_CAPT",                //  10: Timer 1 Capture Event
  "TIMER1_COMPA",               //  11: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  12: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  13: Timer 1 Overflow
  "TIMER0_COMPA",               //  14: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  15: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  16: Timer 0 Overflow
  "SPI0_STC",                   //  17: SPI 0 Serial Transfer Complete
  "USART0_RX",                  //  18: USART 0 Receive Complete
  "USART0_UDRE",                //  19: USART 0 Data Register Empty
  "USART0_TX",                  //  20: USART 0 Transmit Complete
  "ADC",                        //  21: ADC Conversion Complete
  "EE_READY",                   //  22: EEPROM Ready
  "ANALOG_COMP",                //  23: Analog Comparator
  "TWI0",                       //  24: 2-Wire Interface 0
  "SPM_Ready",                  //  25: Store Program Memory Ready
  "USART0_START",               //  26: USART 0 Receive Start
  "PCINT3",                     //  27: Pin Change Interrupt 3
  "USART1_RX",                  //  28: USART 1 Receive Complete
  "USART1_UDRE",                //  29: USART 1 Data Register Empty
  "USART1_TX",                  //  30: USART 1 Transmit Complete
  "USART1_START",               //  31: USART 1 Receive Start
  "TIMER3_CAPT",                //  32: Timer 3 Capture Event
  "TIMER3_COMPA",               //  33: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  34: Timer 3 Compare Match B
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "CFD",                        //  36: Clock Failure Detection
  "PTC_EOC",                    //  37: PTC End of Conversion
  "PTC_WCOMP",                  //  38: PTC Window Comparator Mode
  "SPI1_STC",                   //  39: SPI 1 Serial Transfer Complete
  "TWI1",                       //  40: 2-Wire Interface 1
  "TIMER4_CAPT",                //  41: Timer 4 Capture Event
  "TIMER4_COMPA",               //  42: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  43: Timer 4 Compare Match B
  "TIMER4_OVF",                 //  44: Timer 4 Overflow
};

const char * const vtab_atmega406[vts_atmega406] = { // ATmega406
  "RESET",                      //   0: Reset (various reasons)
  "BPINT",                      //   1: Battery Protection Interrupt
  "INT0",                       //   2: External Interrupt 0
  "INT1",                       //   3: External Interrupt 1
  "INT2",                       //   4: External Interrupt 2
  "INT3",                       //   5: External Interrupt 3
  "PCINT0",                     //   6: Pin Change Interrupt 0
  "PCINT1",                     //   7: Pin Change Interrupt 1
  "WDT",                        //   8: Watchdog Time-out
  "WAKE_UP",                    //   9: Wake Up
  "TIM1_COMP",                  //  10: Timer 1 Compare and Match
  "TIM1_OVF",                   //  11: Timer 1 Overflow
  "TIM0_COMPA",                 //  12: Timer 0 Compare Match A
  "TIM0_COMPB",                 //  13: Timer 0 Compare Match B
  "TIM0_OVF",                   //  14: Timer 0 Overflow
  "TWI_BUS_CD",                 //  15: 2-Wire Interface Bus Connect/Disconnect
  "TWI",                        //  16: 2-Wire Interface
  "VADC",                       //  17: Voltage ADC Conversion Complete
  "CCADC_CONV",                 //  18: Coulomb Counter ADC Conversion Complete
  "CCADC_REG_CUR",              //  19: Coloumb Counter ADC Regular Current
  "CCADC_ACC",                  //  20: Coloumb Counter ADC Accumulator
  "EE_READY",                   //  21: EEPROM Ready
  "SPM_READY",                  //  22: Store Program Memory Ready
};

const char * const vtab_atmega644[vts_atmega644] = { // ATmega644
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "PCINT0",                     //   4: Pin Change Interrupt 0
  "PCINT1",                     //   5: Pin Change Interrupt 1
  "PCINT2",                     //   6: Pin Change Interrupt 2
  "PCINT3",                     //   7: Pin Change Interrupt 3
  "WDT",                        //   8: Watchdog Time-out
  "TIMER2_COMPA",               //   9: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  10: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  17: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  18: Timer 0 Overflow
  "SPI_STC",                    //  19: SPI Serial Transfer Complete
  "USART0_RX",                  //  20: USART 0 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART0_TX",                  //  22: USART 0 Transmit Complete
  "ANALOG_COMP",                //  23: Analog Comparator
  "ADC",                        //  24: ADC Conversion Complete
  "EE_READY",                   //  25: EEPROM Ready
  "TWI",                        //  26: 2-Wire Interface
  "SPM_READY",                  //  27: Store Program Memory Ready
};

const char * const vtab_atmega644pa[vts_atmega644pa] = { // ATmega644PA, ATmega644P, ATmega644A, ATmega324PA, ATmega324P, ATmega324A, ATmega164PA, ATmega164P, ATmega164A
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "PCINT0",                     //   4: Pin Change Interrupt 0
  "PCINT1",                     //   5: Pin Change Interrupt 1
  "PCINT2",                     //   6: Pin Change Interrupt 2
  "PCINT3",                     //   7: Pin Change Interrupt 3
  "WDT",                        //   8: Watchdog Time-out
  "TIMER2_COMPA",               //   9: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  10: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  17: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  18: Timer 0 Overflow
  "SPI_STC",                    //  19: SPI Serial Transfer Complete
  "USART0_RX",                  //  20: USART 0 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART0_TX",                  //  22: USART 0 Transmit Complete
  "ANALOG_COMP",                //  23: Analog Comparator
  "ADC",                        //  24: ADC Conversion Complete
  "EE_READY",                   //  25: EEPROM Ready
  "TWI",                        //  26: 2-Wire Interface
  "SPM_READY",                  //  27: Store Program Memory Ready
  "USART1_RX",                  //  28: USART 1 Receive Complete
  "USART1_UDRE",                //  29: USART 1 Data Register Empty
  "USART1_TX",                  //  30: USART 1 Transmit Complete
};

const char * const vtab_atmega645p[vts_atmega645p] = { // ATmega645P, ATmega645A, ATmega645, ATmega325PA, ATmega325P, ATmega325A, ATmega325, ATmega165PA, ATmega165P, ATmega165A, ATmega165
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "USART0_RX",                  //  13: USART 0 Receive Complete
  "USART0_UDRE",                //  14: USART 0 Data Register Empty
  "USART0_TX",                  //  15: USART 0 Transmit Complete
  "USI_START",                  //  16: USI Start Condition
  "USI_OVERFLOW",               //  17: USI Overflow
  "ANALOG_COMP",                //  18: Analog Comparator
  "ADC",                        //  19: ADC Conversion Complete
  "EE_READY",                   //  20: EEPROM Ready
  "SPM_READY",                  //  21: Store Program Memory Ready
};

const char * const vtab_atmega649p[vts_atmega649p] = { // ATmega649P, ATmega649A, ATmega649, ATmega329PA, ATmega329P, ATmega329A, ATmega329, ATmega169PA, ATmega169P, ATmega169A, ATmega169
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "USART0_RX",                  //  13: USART 0 Receive Complete
  "USART0_UDRE",                //  14: USART 0 Data Register Empty
  "USART0_TX",                  //  15: USART 0 Transmit Complete
  "USI_START",                  //  16: USI Start Condition
  "USI_OVERFLOW",               //  17: USI Overflow
  "ANALOG_COMP",                //  18: Analog Comparator
  "ADC",                        //  19: ADC Conversion Complete
  "EE_READY",                   //  20: EEPROM Ready
  "SPM_READY",                  //  21: Store Program Memory Ready
  "LCD",                        //  22: LCD Start of Frame
};

const char * const vtab_atmega1284p[vts_atmega1284p] = { // ATmega1284P, ATmega1284
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "PCINT0",                     //   4: Pin Change Interrupt 0
  "PCINT1",                     //   5: Pin Change Interrupt 1
  "PCINT2",                     //   6: Pin Change Interrupt 2
  "PCINT3",                     //   7: Pin Change Interrupt 3
  "WDT",                        //   8: Watchdog Time-out
  "TIMER2_COMPA",               //   9: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  10: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  17: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  18: Timer 0 Overflow
  "SPI_STC",                    //  19: SPI Serial Transfer Complete
  "USART0_RX",                  //  20: USART 0 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART0_TX",                  //  22: USART 0 Transmit Complete
  "ANALOG_COMP",                //  23: Analog Comparator
  "ADC",                        //  24: ADC Conversion Complete
  "EE_READY",                   //  25: EEPROM Ready
  "TWI",                        //  26: 2-Wire Interface
  "SPM_READY",                  //  27: Store Program Memory Ready
  "USART1_RX",                  //  28: USART 1 Receive Complete
  "USART1_UDRE",                //  29: USART 1 Data Register Empty
  "USART1_TX",                  //  30: USART 1 Transmit Complete
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_OVF",                 //  34: Timer 3 Overflow
};

const char * const vtab_atmega2561[vts_atmega2561] = { // ATmega2561, ATmega2560, ATmega1281, ATmega1280, ATmega640
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "PCINT1",                     //  10: Pin Change Interrupt 1
  "PCINT2",                     //  11: Pin Change Interrupt 2
  "WDT",                        //  12: Watchdog Time-out
  "TIMER2_COMPA",               //  13: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  14: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  15: Timer 2 Overflow
  "TIMER1_CAPT",                //  16: Timer 1 Capture Event
  "TIMER1_COMPA",               //  17: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  18: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  19: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  20: Timer 1 Overflow
  "TIMER0_COMPA",               //  21: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  22: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  23: Timer 0 Overflow
  "SPI_STC",                    //  24: SPI Serial Transfer Complete
  "USART0_RX",                  //  25: USART 0 Receive Complete
  "USART0_UDRE",                //  26: USART 0 Data Register Empty
  "USART0_TX",                  //  27: USART 0 Transmit Complete
  "ANALOG_COMP",                //  28: Analog Comparator
  "ADC",                        //  29: ADC Conversion Complete
  "EE_READY",                   //  30: EEPROM Ready
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  34: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "USART1_RX",                  //  36: USART 1 Receive Complete
  "USART1_UDRE",                //  37: USART 1 Data Register Empty
  "USART1_TX",                  //  38: USART 1 Transmit Complete
  "TWI",                        //  39: 2-Wire Interface
  "SPM_READY",                  //  40: Store Program Memory Ready
  "TIMER4_CAPT",                //  41: Timer 4 Capture Event
  "TIMER4_COMPA",               //  42: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  43: Timer 4 Compare Match B
  "TIMER4_COMPC",               //  44: Timer 4 Compare Match C
  "TIMER4_OVF",                 //  45: Timer 4 Overflow
  "TIMER5_CAPT",                //  46: Timer 5 Capture Event
  "TIMER5_COMPA",               //  47: Timer 5 Compare Match A
  "TIMER5_COMPB",               //  48: Timer 5 Compare Match B
  "TIMER5_COMPC",               //  49: Timer 5 Compare Match C
  "TIMER5_OVF",                 //  50: Timer 5 Overflow
  "USART2_RX",                  //  51: USART 2 Receive Complete
  "USART2_UDRE",                //  52: USART 2 Data Register Empty
  "USART2_TX",                  //  53: USART 2 Transmit Complete
  "USART3_RX",                  //  54: USART 3 Receive Complete
  "USART3_UDRE",                //  55: USART 3 Data Register Empty
  "USART3_TX",                  //  56: USART 3 Transmit Complete
};

const char * const vtab_atmega2564rfr2[vts_atmega2564rfr2] = { // ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "PCINT0",                     //   9: Pin Change Interrupt 0
  "PCINT1",                     //  10: Pin Change Interrupt 1
  "PCINT2",                     //  11: Pin Change Interrupt 2
  "WDT",                        //  12: Watchdog Time-out
  "TIMER2_COMPA",               //  13: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  14: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  15: Timer 2 Overflow
  "TIMER1_CAPT",                //  16: Timer 1 Capture Event
  "TIMER1_COMPA",               //  17: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  18: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  19: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  20: Timer 1 Overflow
  "TIMER0_COMPA",               //  21: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  22: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  23: Timer 0 Overflow
  "SPI_STC",                    //  24: SPI Serial Transfer Complete
  "USART0_RX",                  //  25: USART 0 Receive Complete
  "USART0_UDRE",                //  26: USART 0 Data Register Empty
  "USART0_TX",                  //  27: USART 0 Transmit Complete
  "ANALOG_COMP",                //  28: Analog Comparator
  "ADC",                        //  29: ADC Conversion Complete
  "EE_READY",                   //  30: EEPROM Ready
  "TIMER3_CAPT",                //  31: Timer 3 Capture Event
  "TIMER3_COMPA",               //  32: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  33: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  34: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  35: Timer 3 Overflow
  "USART1_RX",                  //  36: USART 1 Receive Complete
  "USART1_UDRE",                //  37: USART 1 Data Register Empty
  "USART1_TX",                  //  38: USART 1 Transmit Complete
  "TWI",                        //  39: 2-Wire Interface
  "SPM_READY",                  //  40: Store Program Memory Ready
  "TIMER4_CAPT",                //  41: Timer 4 Capture Event
  "TIMER4_COMPA",               //  42: Timer 4 Compare Match A
  "TIMER4_COMPB",               //  43: Timer 4 Compare Match B
  "TIMER4_COMPC",               //  44: Timer 4 Compare Match C
  "TIMER4_OVF",                 //  45: Timer 4 Overflow
  "TIMER5_CAPT",                //  46: Timer 5 Capture Event
  "TIMER5_COMPA",               //  47: Timer 5 Compare Match A
  "TIMER5_COMPB",               //  48: Timer 5 Compare Match B
  "TIMER5_COMPC",               //  49: Timer 5 Compare Match C
  "TIMER5_OVF",                 //  50: Timer 5 Overflow
  "RESERVED_51",                //  51: Reserved 51
  "RESERVED_52",                //  52: Reserved 52
  "RESERVED_53",                //  53: Reserved 53
  "RESERVED_54",                //  54: Reserved 54
  "RESERVED_55",                //  55: Reserved 55
  "RESERVED_56",                //  56: Reserved 56
  "TRX24_PLL_LOCK",             //  57: TRX24 PLL Lock
  "TRX24_PLL_UNLOCK",           //  58: TRX24 PLL Unlock
  "TRX24_RX_START",             //  59: TRX24 Receive Start
  "TRX24_RX_END",               //  60: TRX24 Receive End
  "TRX24_CCA_ED_DONE",          //  61: TRX24 CCA/ED Done
  "TRX24_XAH_AMI",              //  62: TRX24 XAH/AMI
  "TRX24_TX_END",               //  63: TRX24 Transmit End
  "TRX24_AWAKE",                //  64: TRX24 AWAKE - Transceiver is Reaching State TRX_OFF
  "SCNT_CMP1",                  //  65: Symbol Counter - Compare Match 1 Interrupt
  "SCNT_CMP2",                  //  66: Symbol Counter - Compare Match 2 Interrupt
  "SCNT_CMP3",                  //  67: Symbol Counter - Compare Match 3 Interrupt
  "SCNT_OVFL",                  //  68: Symbol Counter - Overflow Interrupt
  "SCNT_BACKOFF",               //  69: Symbol Counter - Backoff Interrupt
  "AES_READY",                  //  70: AES Engine Ready
  "BAT_LOW",                    //  71: Battery Voltage Below Threshold
  "TRX24_TX_START",             //  72: TRX24 Transmit Start
  "TRX24_AMI0",                 //  73: TRX24 Address Match 0
  "TRX24_AMI1",                 //  74: TRX24 Address Match 1
  "TRX24_AMI2",                 //  75: TRX24 Address Match 2
  "TRX24_AMI3",                 //  76: TRX24 Address Match 3
};

const char * const vtab_atmega6450p[vts_atmega6450p] = { // ATmega6450P, ATmega6450A, ATmega6450, ATmega3250PA, ATmega3250P, ATmega3250A, ATmega3250
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "USART_RX",                   //  13: USART Receive Complete
  "USART_UDRE",                 //  14: USART Data Register Empty
  "USART0_TX",                  //  15: USART 0 Transmit Complete
  "USI_START",                  //  16: USI Start Condition
  "USI_OVERFLOW",               //  17: USI Overflow
  "ANALOG_COMP",                //  18: Analog Comparator
  "ADC",                        //  19: ADC Conversion Complete
  "EE_READY",                   //  20: EEPROM Ready
  "SPM_READY",                  //  21: Store Program Memory Ready
  "NOT_USED",                   //  22: Reserved
  "PCINT2",                     //  23: Pin Change Interrupt 2
  "PCINT3",                     //  24: Pin Change Interrupt 3
};

const char * const vtab_atmega6490p[vts_atmega6490p] = { // ATmega6490P, ATmega6490A, ATmega6490, ATmega3290PA, ATmega3290P, ATmega3290A, ATmega3290
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "PCINT0",                     //   2: Pin Change Interrupt 0
  "PCINT1",                     //   3: Pin Change Interrupt 1
  "TIMER2_COMP",                //   4: Timer 2 Compare Match
  "TIMER2_OVF",                 //   5: Timer 2 Overflow
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMP",                //  10: Timer 0 Compare Match
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "SPI_STC",                    //  12: SPI Serial Transfer Complete
  "USART_RX",                   //  13: USART Receive Complete
  "USART_UDRE",                 //  14: USART Data Register Empty
  "USART0_TX",                  //  15: USART 0 Transmit Complete
  "USI_START",                  //  16: USI Start Condition
  "USI_OVERFLOW",               //  17: USI Overflow
  "ANALOG_COMP",                //  18: Analog Comparator
  "ADC",                        //  19: ADC Conversion Complete
  "EE_READY",                   //  20: EEPROM Ready
  "SPM_READY",                  //  21: Store Program Memory Ready
  "LCD",                        //  22: LCD Start of Frame
  "PCINT2",                     //  23: Pin Change Interrupt 2
  "PCINT3",                     //  24: Pin Change Interrupt 3
};

const char * const vtab_atmega8515[vts_atmega8515] = { // ATmega8515
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT",                //   3: Timer 1 Capture Event
  "TIMER1_COMPA",               //   4: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   5: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   6: Timer 1 Overflow
  "TIMER0_OVF",                 //   7: Timer 0 Overflow
  "SPI_STC",                    //   8: SPI Serial Transfer Complete
  "USART_RX",                   //   9: USART Receive Complete
  "USART_UDRE",                 //  10: USART Data Register Empty
  "USART_TX",                   //  11: USART Transmit Complete
  "ANA_COMP",                   //  12: Analog Comparator
  "INT2",                       //  13: External Interrupt 2
  "TIMER0_COMP",                //  14: Timer 0 Compare Match
  "EE_RDY",                     //  15: EEPROM Ready
  "SPM_RDY",                    //  16: Store Program Memory Ready
};

const char * const vtab_atmega8535[vts_atmega8535] = { // ATmega8535
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER2_COMP",                //   3: Timer 2 Compare Match
  "TIMER2_OVF",                 //   4: Timer 2 Overflow
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_OVF",                 //   9: Timer 0 Overflow
  "SPI_STC",                    //  10: SPI Serial Transfer Complete
  "USART_RX",                   //  11: USART Receive Complete
  "USART_UDRE",                 //  12: USART Data Register Empty
  "USART_TX",                   //  13: USART Transmit Complete
  "ADC",                        //  14: ADC Conversion Complete
  "EE_RDY",                     //  15: EEPROM Ready
  "ANA_COMP",                   //  16: Analog Comparator
  "TWI",                        //  17: 2-Wire Interface
  "INT2",                       //  18: External Interrupt 2
  "TIMER0_COMP",                //  19: Timer 0 Compare Match
  "SPM_RDY",                    //  20: Store Program Memory Ready
};

const char * const vtab_at86rf401[vts_at86rf401] = { // AT86RF401
  "RESET",                      //   0: Reset (various reasons)
  "TXDONE",                     //   1: Transmit Complete
  "TXEMPTY",                    //   2: Transmit Register Empty
};

const char * const vtab_at90pwm2[vts_at90pwm2] = { // AT90PWM2
  "RESET",                      //   0: Reset (various reasons)
  "PSC2_CAPT",                  //   1: PSC 2 Capture Event
  "PSC2_EC",                    //   2: PSC 2 End Cycle
  "PSC1_CAPT",                  //   3: PSC 1 Capture Event
  "PSC1_EC",                    //   4: PSC 1 End Cycle
  "PSC0_CAPT",                  //   5: PSC 0 Capture Event
  "PSC0_EC",                    //   6: PSC 0 End Cycle
  "ANALOG_COMP_0",              //   7: Analog Comparator 0
  "ANALOG_COMP_1",              //   8: Analog Comparator 1
  "ANALOG_COMP_2",              //   9: Analog Comparator 2
  "INT0",                       //  10: External Interrupt 0
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "UNUSED",                     //  14: not implemented on this device
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMP_A",              //  16: Timer 0 Compare Match A
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "ADC",                        //  18: ADC Conversion Complete
  "INT1",                       //  19: External Interrupt 1
  "SPI_STC",                    //  20: SPI Serial Transfer Complete
  "USART_RX",                   //  21: USART Receive Complete
  "USART_UDRE",                 //  22: USART Data Register Empty
  "USART_TX",                   //  23: USART Transmit Complete
  "INT2",                       //  24: External Interrupt 2
  "WDT",                        //  25: Watchdog Time-out
  "EE_READY",                   //  26: EEPROM Ready
  "TIMER0_COMPB",               //  27: Timer 0 Compare Match B
  "INT3",                       //  28: External Interrupt 3
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "SPM_READY",                  //  31: Store Program Memory Ready
};

const char * const vtab_at90pwm3b[vts_at90pwm3b] = { // AT90PWM3B, AT90PWM3, AT90PWM2B
  "RESET",                      //   0: Reset (various reasons)
  "PSC2_CAPT",                  //   1: PSC 2 Capture Event
  "PSC2_EC",                    //   2: PSC 2 End Cycle
  "PSC1_CAPT",                  //   3: PSC 1 Capture Event
  "PSC1_EC",                    //   4: PSC 1 End Cycle
  "PSC0_CAPT",                  //   5: PSC 0 Capture Event
  "PSC0_EC",                    //   6: PSC 0 End Cycle
  "ANALOG_COMP_0",              //   7: Analog Comparator 0
  "ANALOG_COMP_1",              //   8: Analog Comparator 1
  "ANALOG_COMP_2",              //   9: Analog Comparator 2
  "INT0",                       //  10: External Interrupt 0
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "RESERVED15",                 //  14: Reserved 15
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "ADC",                        //  18: ADC Conversion Complete
  "INT1",                       //  19: External Interrupt 1
  "SPI_STC",                    //  20: SPI Serial Transfer Complete
  "USART_RX",                   //  21: USART Receive Complete
  "USART_UDRE",                 //  22: USART Data Register Empty
  "USART_TX",                   //  23: USART Transmit Complete
  "INT2",                       //  24: External Interrupt 2
  "WDT",                        //  25: Watchdog Time-out
  "EE_READY",                   //  26: EEPROM Ready
  "TIMER0_COMPB",               //  27: Timer 0 Compare Match B
  "INT3",                       //  28: External Interrupt 3
  "RESERVED30",                 //  29: Reserved 30
  "RESERVED31",                 //  30: Reserved 31
  "SPM_READY",                  //  31: Store Program Memory Ready
};

const char * const vtab_at90scr100[vts_at90scr100] = { // AT90SCR100
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "PCINT0",                     //   5: Pin Change Interrupt 0
  "PCINT1",                     //   6: Pin Change Interrupt 1
  "PCINT2",                     //   7: Pin Change Interrupt 2
  "WDT",                        //   8: Watchdog Time-out
  "TIMER2_COMPA",               //   9: Timer 2 Compare Match A
  "TIMER2_COMPB",               //  10: Timer 2 Compare Match B
  "TIMER2_OVF",                 //  11: Timer 2 Overflow
  "TIMER1_CAPT",                //  12: Timer 1 Capture Event
  "TIMER1_COMPA",               //  13: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  14: Timer 1 Compare Match B
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMPA",               //  16: Timer 0 Compare Match A
  "TIMER0_COMPB",               //  17: Timer 0 Compare Match B
  "TIMER0_OVF",                 //  18: Timer 0 Overflow
  "SPI_STC",                    //  19: SPI Serial Transfer Complete
  "USART0_RX",                  //  20: USART 0 Receive Complete
  "USART0_UDRE",                //  21: USART 0 Data Register Empty
  "USART0_TX",                  //  22: USART 0 Transmit Complete
  "SUPPLY_MON",                 //  23: Supply Monitor
  "RFU",                        //  24: Reserved for Future Use
  "EE_READY",                   //  25: EEPROM Ready
  "TWI",                        //  26: 2-Wire Interface
  "SPM_READY",                  //  27: Store Program Memory Ready
  "KEYBOARD",                   //  28: Keyboard Input Change
  "AES_Operation",              //  29: AES Operation
  "HSSPI",                      //  30: High-Speed SPI
  "USB_Endpoint",               //  31: USB Endpoint
  "USB_Protocol",               //  32: USB Protocol
  "SCIB",                       //  33: Smart Card Reader Interface
  "USBHost_Control",            //  34: USB Host Controller
  "USBHost_Pipe",               //  35: USB Host Pipe
  "CPRES",                      //  36: Card Presence Detection
  "PCINT3",                     //  37: Pin Change Interrupt 3
};

const char * const vtab_at90can128[vts_at90can128] = { // AT90CAN128, AT90CAN64, AT90CAN32
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "INT2",                       //   3: External Interrupt 2
  "INT3",                       //   4: External Interrupt 3
  "INT4",                       //   5: External Interrupt 4
  "INT5",                       //   6: External Interrupt 5
  "INT6",                       //   7: External Interrupt 6
  "INT7",                       //   8: External Interrupt 7
  "TIMER2_COMP",                //   9: Timer 2 Compare Match
  "TIMER2_OVF",                 //  10: Timer 2 Overflow
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "TIMER1_COMPC",               //  14: Timer 1 Compare Match C
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMP",                //  16: Timer 0 Compare Match
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "CANIT",                      //  18: CAN Transfer Complete or Error
  "OVRIT",                      //  19: CAN Timer Overrun
  "SPI_STC",                    //  20: SPI Serial Transfer Complete
  "USART0_RX",                  //  21: USART 0 Receive Complete
  "USART0_UDRE",                //  22: USART 0 Data Register Empty
  "USART0_TX",                  //  23: USART 0 Transmit Complete
  "ANALOG_COMP",                //  24: Analog Comparator
  "ADC",                        //  25: ADC Conversion Complete
  "EE_READY",                   //  26: EEPROM Ready
  "TIMER3_CAPT",                //  27: Timer 3 Capture Event
  "TIMER3_COMPA",               //  28: Timer 3 Compare Match A
  "TIMER3_COMPB",               //  29: Timer 3 Compare Match B
  "TIMER3_COMPC",               //  30: Timer 3 Compare Match C
  "TIMER3_OVF",                 //  31: Timer 3 Overflow
  "USART1_RX",                  //  32: USART 1 Receive Complete
  "USART1_UDRE",                //  33: USART 1 Data Register Empty
  "USART1_TX",                  //  34: USART 1 Transmit Complete
  "TWI",                        //  35: 2-Wire Interface
  "SPM_READY",                  //  36: Store Program Memory Ready
};

const char * const vtab_at90pwm161[vts_at90pwm161] = { // AT90PWM161, AT90PWM81
  "RESET",                      //   0: Reset (various reasons)
  "PSC2_CAPT",                  //   1: PSC 2 Capture Event
  "PSC2_EC",                    //   2: PSC 2 End Cycle
  "PSC2_EEC",                   //   3: PSC 2 End Of Enhanced Cycle
  "PSC0_CAPT",                  //   4: PSC 0 Capture Event
  "PSC0_EC",                    //   5: PSC 0 End Cycle
  "PSC0_EEC",                   //   6: PSC 0 End Of Enhanced Cycle
  "ANALOG_COMP_1",              //   7: Analog Comparator 1
  "ANALOG_COMP_2",              //   8: Analog Comparator 2
  "ANALOG_COMP_3",              //   9: Analog Comparator 3
  "INT0",                       //  10: External Interrupt 0
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_OVF",                 //  12: Timer 1 Overflow
  "ADC",                        //  13: ADC Conversion Complete
  "INT1",                       //  14: External Interrupt 1
  "SPI_STC",                    //  15: SPI Serial Transfer Complete
  "INT2",                       //  16: External Interrupt 2
  "WDT",                        //  17: Watchdog Time-out
  "EE_READY",                   //  18: EEPROM Ready
  "SPM_READY",                  //  19: Store Program Memory Ready
};

const char * const vtab_at90pwm316[vts_at90pwm316] = { // AT90PWM316, AT90PWM216, AT90PWM1
  "RESET",                      //   0: Reset (various reasons)
  "PSC2_CAPT",                  //   1: PSC 2 Capture Event
  "PSC2_EC",                    //   2: PSC 2 End Cycle
  "PSC1_CAPT",                  //   3: PSC 1 Capture Event
  "PSC1_EC",                    //   4: PSC 1 End Cycle
  "PSC0_CAPT",                  //   5: PSC 0 Capture Event
  "PSC0_EC",                    //   6: PSC 0 End Cycle
  "ANALOG_COMP_0",              //   7: Analog Comparator 0
  "ANALOG_COMP_1",              //   8: Analog Comparator 1
  "ANALOG_COMP_2",              //   9: Analog Comparator 2
  "INT0",                       //  10: External Interrupt 0
  "TIMER1_CAPT",                //  11: Timer 1 Capture Event
  "TIMER1_COMPA",               //  12: Timer 1 Compare Match A
  "TIMER1_COMPB",               //  13: Timer 1 Compare Match B
  "RESERVED15",                 //  14: Reserved 15
  "TIMER1_OVF",                 //  15: Timer 1 Overflow
  "TIMER0_COMP_A",              //  16: Timer 0 Compare Match A
  "TIMER0_OVF",                 //  17: Timer 0 Overflow
  "ADC",                        //  18: ADC Conversion Complete
  "INT1",                       //  19: External Interrupt 1
  "SPI_STC",                    //  20: SPI Serial Transfer Complete
  "USART_RX",                   //  21: USART Receive Complete
  "USART_UDRE",                 //  22: USART Data Register Empty
  "USART_TX",                   //  23: USART Transmit Complete
  "INT2",                       //  24: External Interrupt 2
  "WDT",                        //  25: Watchdog Time-out
  "EE_READY",                   //  26: EEPROM Ready
  "TIMER0_COMPB",               //  27: Timer 0 Compare Match B
  "INT3",                       //  28: External Interrupt 3
  "RESERVED30",                 //  29: Reserved 30
  "RESERVED31",                 //  30: Reserved 31
  "SPM_READY",                  //  31: Store Program Memory Ready
};

const char * const vtab_at90s1200[vts_at90s1200] = { // AT90S1200
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "TIMER0_OVF",                 //   2: Timer 0 Overflow
  "ANA_COMP",                   //   3: Analog Comparator
};

const char * const vtab_at90s2313[vts_at90s2313] = { // AT90S2313
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT1",               //   3: Timer 1 Capture Event
  "TIMER1_COMP1",               //   4: Timer 1 Compare
  "TIMER1_OVF1",                //   5: Timer 1 Overflow
  "TIMER0_OVF0",                //   6: Timer 0 Overflow
  "UART_RX",                    //   7: UART Receive Complete
  "UART_UDRE",                  //   8: UART Data Register Empty
  "UART_TX",                    //   9: UART Transmit Complete
  "ANA_COMP",                   //  10: Analog Comparator
};

const char * const vtab_at90s4433[vts_at90s4433] = { // AT90S4433, AT90S2333
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT",                //   3: Timer 1 Capture Event
  "TIMER1_COMP",                //   4: Timer 1 Compare
  "TIMER1_OVF",                 //   5: Timer 1 Overflow
  "TIMER0_OVF",                 //   6: Timer 0 Overflow
  "SPI_STC",                    //   7: SPI Serial Transfer Complete
  "UART_RX",                    //   8: UART Receive Complete
  "UART_UDRE",                  //   9: UART Data Register Empty
  "UART_TX",                    //  10: UART Transmit Complete
  "ADC",                        //  11: ADC Conversion Complete
  "EE_RDY",                     //  12: EEPROM Ready
  "ANA_COMP",                   //  13: Analog Comparator
};

const char * const vtab_at90s8515[vts_at90s8515] = { // AT90S8515, AT90S4414
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER1_CAPT",                //   3: Timer 1 Capture Event
  "TIMER1_COMPA",               //   4: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   5: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   6: Timer 1 Overflow
  "TIMER0_OVF",                 //   7: Timer 0 Overflow
  "SPI_STC",                    //   8: SPI Serial Transfer Complete
  "UART_RX",                    //   9: UART Receive Complete
  "UART_UDRE",                  //  10: UART Data Register Empty
  "UART_TX",                    //  11: UART Transmit Complete
  "ANA_COMP",                   //  12: Analog Comparator
};

const char * const vtab_at90s8535[vts_at90s8535] = { // AT90S8535, AT90S4434
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "TIMER2_COMP",                //   3: Timer 2 Compare Match
  "TIMER2_OVF",                 //   4: Timer 2 Overflow
  "TIMER1_CAPT",                //   5: Timer 1 Capture Event
  "TIMER1_COMPA",               //   6: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   7: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   8: Timer 1 Overflow
  "TIMER0_OVF",                 //   9: Timer 0 Overflow
  "SPI_STC",                    //  10: SPI Serial Transfer Complete
  "UART_RX",                    //  11: UART Receive Complete
  "UART_UDRE",                  //  12: UART Data Register Empty
  "UART_TX",                    //  13: UART Transmit Complete
  "ADC",                        //  14: ADC Conversion Complete
  "EE_RDY",                     //  15: EEPROM Ready
  "ANA_COMP",                   //  16: Analog Comparator
};

const char * const vtab_ata5272[vts_ata5272] = { // ATA5272
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "WDT",                        //   5: Watchdog Time-out
  "TIMER1_CAPT",                //   6: Timer 1 Capture Event
  "TIMER1_COMPA",               //   7: Timer 1 Compare Match A
  "TIMER1_COMPB",               //   8: Timer 1 Compare Match B
  "TIMER1_OVF",                 //   9: Timer 1 Overflow
  "TIMER0_COMPA",               //  10: Timer 0 Compare Match A
  "TIMER0_OVF",                 //  11: Timer 0 Overflow
  "LIN_TC",                     //  12: LIN Transfer Complete
  "LIN_ERR",                    //  13: LIN Error
  "SPI_STC",                    //  14: SPI Serial Transfer Complete
  "ADC",                        //  15: ADC Conversion Complete
  "EE_RDY",                     //  16: EEPROM Ready
  "UNUSED",                     //  17: not implemented on this device
  "UNUSED",                     //  18: not implemented on this device
  "USI_OVF",                    //  19: USI Overflow
  "UNUSED",                     //  20: not implemented on this device
  "UNUSED",                     //  21: not implemented on this device
  "UNUSED",                     //  22: not implemented on this device
  "UNUSED",                     //  23: not implemented on this device
  "UNUSED",                     //  24: not implemented on this device
  "UNUSED",                     //  25: not implemented on this device
  "UNUSED",                     //  26: not implemented on this device
  "UNUSED",                     //  27: not implemented on this device
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "UNUSED",                     //  31: not implemented on this device
  "UNUSED",                     //  32: not implemented on this device
  "UNUSED",                     //  33: not implemented on this device
  "ANA_COMP",                   //  34: Analog Comparator
  "UNUSED",                     //  35: not implemented on this device
  "USI_START",                  //  36: USI Start Condition
};

const char * const vtab_ata5702m322[vts_ata5702m322] = { // ATA5702M322, ATA5700M322
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCI0",                       //   3: Pin Change Interrupt Request 0
  "PCI1",                       //   4: Pin Change Interrupt Request 1
  "VMON",                       //   5: Voltage Monitoring
  "AVCCR",                      //   6: AVCC Reset
  "AVCCL",                      //   7: AVCC Low
  "T0INT",                      //   8: Timer 0 Interrupt
  "T1COMP",                     //   9: Timer 1 Compare and Match
  "T1OVF",                      //  10: Timer 1 Overflow
  "T2COMP",                     //  11: Timer 2 Compare and Match
  "T2OVF",                      //  12: Timer 2 Overflow
  "T3CAP",                      //  13: Timer 3 Capture Event
  "T3COMP",                     //  14: Timer 3 Compare and Match
  "T3OVF",                      //  15: Timer 3 Overflow
  "T4CAP",                      //  16: Timer 4 Capture Event
  "T4COMP",                     //  17: Timer 4 Compare and Match
  "T4OVF",                      //  18: Timer 4 Overflow
  "T5COMP",                     //  19: Timer 5 Compare and Match
  "T5OVF",                      //  20: Timer 5 Overflow
  "SPI",                        //  21: SPI Serial Peripheral Interface
  "SRX_FIFO",                   //  22: SPI Receive Buffer
  "STX_FIFO",                   //  23: SPI Transmit Buffer
  "SSM",                        //  24: Sequencer State Machine
  "DFFLR",                      //  25: Data FIFO Fill Level Reached
  "DFOUE",                      //  26: Data FIFO Overflow or Underflow Error
  "SFFLR",                      //  27: RSSI/Preamble FIFO Fill Level Reached
  "SFOUE",                      //  28: RSSI/Preamble FIFO Overflow or Underflow Error
  "TMTCF",                      //  29: Transmit Modulator Telegram Finished
  "AES",                        //  30: AES Crypto Unit
  "TPINT",                      //  31: Transponder Mode Interrupt
  "TPTOERR",                    //  32: Transponder Timeout Error
  "LFID0INT",                   //  33: LF Receiver Identifier 0 Interrupt
  "LFID1INT",                   //  34: LF Receiver Identifier 1 Interrupt
  "LFFEINT",                    //  35: LF Receiver Frame End Interrupt
  "LFBCR",                      //  36: LF Receiver Bit Count Reached
  "LFPBD",                      //  37: LF Receiver PreBurst Detected
  "LFDE",                       //  38: LF Receiver Decoder Error
  "LFEOT",                      //  39: LF Receiver End of Telegram
  "LFTCOR",                     //  40: LF Receiver Timer Compare
  "LFRSCO",                     //  41: LF Receiver RSSI Measurement
  "LDFFLR",                     //  42: Data FIFO Fill Level Reached
  "LDFOUE",                     //  43: Data FIFO Overflow or Underflow Error
  "EXCM",                       //  44: External Input Clock Break Down
  "E2CINT",                     //  45: EEPROM Error Correction Interrupt
  "ERDY",                       //  46: EEPROM Ready
  "SPMR",                       //  47: Store Program Memory Ready
  "TWI1",                       //  48: 2-Wire Interface 1
  "SPI2",                       //  49: SPI 2 Serial Peripheral Interface
  "TWI2",                       //  50: 2-Wire Interface 2
};

const char * const vtab_ata5790[vts_ata5790] = { // ATA5790
  "RESET",                      //   0: Reset (various reasons)
  "TPINT",                      //   1: Transponder Mode Interrupt
  "INT0",                       //   2: External Interrupt 0
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "VMINT",                      //   5: Voltage Monitoring Interrupt
  "T0INT",                      //   6: Timer 0 Interrupt
  "LFID0INT",                   //   7: LF Receiver Identifier 0 Interrupt
  "LFID1INT",                   //   8: LF Receiver Identifier 1 Interrupt
  "LFFEINT",                    //   9: LF Receiver Frame End Interrupt
  "LFDBINT",                    //  10: LF Receiver Data Buffer Full Interrupt
  "T3CAPINT",                   //  11: Timer 3 Capture Event Interrupt
  "T3COMINT",                   //  12: Timer 3 Compare and Match Interrupt
  "T3OVFINT",                   //  13: Timer 3 Overflow Interrupt
  "T2COMINT",                   //  14: Timer 2 Compare and Match Interrupt
  "T2OVFINT",                   //  15: Timer 2 Overflow Interrupt
  "T1INT",                      //  16: Timer 1 Interrupt
  "SPISTC",                     //  17: SPI Serial Transfer Complete
  "TMRXBINT",                   //  18: Timer Modulator Receive Buffer Interrupt
  "TMTXBINT",                   //  19: Timer Modulator Transmit Buffer Interrupt
  "TMTXCINT",                   //  20: Timer Modulator Transmit Complete Interrupt
  "AESINT",                     //  21: AES Crypto Unit Interrupt
  "LFRSSINT",                   //  22: LF Receiver RSSI Interrupt
  "LFSDINT",                    //  23: LF Receiver Signal Detect Interrupt
  "LFMDINT",                    //  24: LF Receiver Manchester Decoder Error Interrupt
  "EXCMINT",                    //  25: External Input Clock Monitoring Interrupt
  "EXXMINT",                    //  26: External XTAL Oscillator Break Down Interrupt
  "RTCINT",                     //  27: Real Time Clock Interrupt
  "EEREADY",                    //  28: EEPROM Ready
  "SPMREADY",                   //  29: Store Program Memory Ready
};

const char * const vtab_ata5791[vts_ata5791] = { // ATA5791, ATA5790N
  "RESET",                      //   0: Reset (various reasons)
  "TPINT",                      //   1: Transponder Mode Interrupt
  "INT0",                       //   2: External Interrupt 0
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "VMINT",                      //   5: Voltage Monitoring Interrupt
  "T0INT",                      //   6: Timer 0 Interrupt
  "LFID0INT",                   //   7: LF Receiver Identifier 0 Interrupt
  "LFID1INT",                   //   8: LF Receiver Identifier 1 Interrupt
  "LFFEINT",                    //   9: LF Receiver Frame End Interrupt
  "LFDBINT",                    //  10: LF Receiver Data Buffer Full Interrupt
  "T3CAPINT",                   //  11: Timer 3 Capture Event Interrupt
  "T3COMINT",                   //  12: Timer 3 Compare and Match Interrupt
  "T3OVFINT",                   //  13: Timer 3 Overflow Interrupt
  "T3COM2INT",                  //  14: Timer 3 Compare and Match 2 Interrupt
  "T2COMINT",                   //  15: Timer 2 Compare and Match Interrupt
  "T2OVFINT",                   //  16: Timer 2 Overflow Interrupt
  "T1INT",                      //  17: Timer 1 Interrupt
  "SPISTC",                     //  18: SPI Serial Transfer Complete
  "TMRXBINT",                   //  19: Timer Modulator Receive Buffer Interrupt
  "TMTXBINT",                   //  20: Timer Modulator Transmit Buffer Interrupt
  "TMTXCINT",                   //  21: Timer Modulator Transmit Complete Interrupt
  "AESINT",                     //  22: AES Crypto Unit Interrupt
  "LFRSSINT",                   //  23: LF Receiver RSSI Interrupt
  "LFSDINT",                    //  24: LF Receiver Signal Detect Interrupt
  "LFMDINT",                    //  25: LF Receiver Manchester Decoder Error Interrupt
  "EXCMINT",                    //  26: External Input Clock Monitoring Interrupt
  "EXXMINT",                    //  27: External XTAL Oscillator Break Down Interrupt
  "RTCINT",                     //  28: Real Time Clock Interrupt
  "EEREADY",                    //  29: EEPROM Ready
  "SPMREADY",                   //  30: Store Program Memory Ready
};

const char * const vtab_ata5795[vts_ata5795] = { // ATA5795
  "RESET",                      //   0: Reset (various reasons)
  "TPINT",                      //   1: Transponder Mode Interrupt
  "INT0",                       //   2: External Interrupt 0
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "VMINT",                      //   5: Voltage Monitoring Interrupt
  "T0INT",                      //   6: Timer 0 Interrupt
  "T3CAPINT",                   //   7: Timer 3 Capture Event Interrupt
  "T3COMINT",                   //   8: Timer 3 Compare and Match Interrupt
  "T3OVFINT",                   //   9: Timer 3 Overflow Interrupt
  "T2COMINT",                   //  10: Timer 2 Compare and Match Interrupt
  "T2OVFINT",                   //  11: Timer 2 Overflow Interrupt
  "T1INT",                      //  12: Timer 1 Interrupt
  "SPISTC",                     //  13: SPI Serial Transfer Complete
  "TMRXBINT",                   //  14: Timer Modulator Receive Buffer Interrupt
  "TMTXBINT",                   //  15: Timer Modulator Transmit Buffer Interrupt
  "TMTXCINT",                   //  16: Timer Modulator Transmit Complete Interrupt
  "AESINT",                     //  17: AES Crypto Unit Interrupt
  "EXCMINT",                    //  18: External Input Clock Monitoring Interrupt
  "EXXMINT",                    //  19: External XTAL Oscillator Break Down Interrupt
  "RTCINT",                     //  20: Real Time Clock Interrupt
  "EEREADY",                    //  21: EEPROM Ready
  "SPMREADY",                   //  22: Store Program Memory Ready
};

const char * const vtab_ata5835[vts_ata5835] = { // ATA5835, ATA5787
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCI0",                       //   3: Pin Change Interrupt Request 0
  "PCI1",                       //   4: Pin Change Interrupt Request 1
  "VMON",                       //   5: Voltage Monitoring
  "AVCCR",                      //   6: AVCC Reset
  "AVCCL",                      //   7: AVCC Low
  "T0INT",                      //   8: Timer 0 Interrupt
  "T1COMP",                     //   9: Timer 1 Compare and Match
  "T1OVF",                      //  10: Timer 1 Overflow
  "T2COMP",                     //  11: Timer 2 Compare and Match
  "T2OVF",                      //  12: Timer 2 Overflow
  "T3CAP",                      //  13: Timer 3 Capture Event
  "T3COMP",                     //  14: Timer 3 Compare and Match
  "T3OVF",                      //  15: Timer 3 Overflow
  "T4CAP",                      //  16: Timer 4 Capture Event
  "T4COMP",                     //  17: Timer 4 Compare and Match
  "T4OVF",                      //  18: Timer 4 Overflow
  "T5COMP",                     //  19: Timer 5 Compare and Match
  "T5OVF",                      //  20: Timer 5 Overflow
  "SPI",                        //  21: SPI Serial Peripheral Interface
  "SRX_FIFO",                   //  22: SPI Receive Buffer
  "STX_FIFO",                   //  23: SPI Transmit Buffer
  "LINTC",                      //  24: LIN Transfer Complete
  "LINERR",                     //  25: LIN Error
  "SSM",                        //  26: Sequencer State Machine
  "DFFLR",                      //  27: Data FIFO Fill Level Reached
  "DFOUE",                      //  28: Data FIFO Overflow or Underflow Error
  "SFFLR",                      //  29: RSSI/Preamble FIFO Fill Level Reached
  "SFOUE",                      //  30: RSSI/Preamble FIFO Overflow or Underflow Error
  "TMTCF",                      //  31: Transmit Modulator Telegram Finished
  "UHF_WCOA",                   //  32: UHF Receiver Wake Up OK on Receive Path A
  "UHF_WCOB",                   //  33: UHF Receiver Wake Up OK on Receive Path B
  "UHF_SOTA",                   //  34: UHF Receiver Start of Telegram OK on Receive Path A
  "UHF_SOTB",                   //  35: UHF Receiver Start of Telegram OK on Receive Path B
  "UHF_EOTA",                   //  36: UHF Receiver End of Telegram on Receive Path A
  "UHF_EOTB",                   //  37: UHF Receiver End of Telegram on Receive Path B
  "UHF_NBITA",                  //  38: UHF Receiver New Bit on Receive Path A
  "UHF_NBITB",                  //  39: UHF Receiver New Bit on Receive Path B
  "EXCM",                       //  40: External Input Clock Break Down
  "ERDY",                       //  41: EEPROM Ready
  "SPMR",                       //  42: Store Program Memory Ready
  "IDFULL",                     //  43: IDSCAN Full
};

const char * const vtab_ata6289[vts_ata6289] = { // ATA6289, ATA6286, ATA6285
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCINT0",                     //   3: Pin Change Interrupt 0
  "PCINT1",                     //   4: Pin Change Interrupt 1
  "PCINT2",                     //   5: Pin Change Interrupt 2
  "INTVM",                      //   6: Voltage Monitor Interrupt
  "SENINT",                     //   7: Sensor Interface Interrupt
  "INTT0",                      //   8: Timer 0 Interval Interrupt
  "LFWP",                       //   9: LF-Receiver Wake-up
  "T3CAP",                      //  10: Timer 3 Capture Event
  "T3COMA",                     //  11: Timer 3 Compare Match A
  "T3COMB",                     //  12: Timer 3 Compare Match B
  "T3OVF",                      //  13: Timer 3 Overflow
  "T2CAP",                      //  14: Timer 2 Capture Event
  "T2COM",                      //  15: Timer 2 Compare Match
  "T2OVF",                      //  16: Timer 2 Overflow
  "SPISTC",                     //  17: SPI Serial Transfer Complete
  "LFRXB",                      //  18: LF Receive Buffer
  "INTT1",                      //  19: Timer 1 Interval Interrupt
  "T2RXB",                      //  20: Timer 2 SSI Receive Buffer
  "T2TXB",                      //  21: Timer 2 SSI Transmit Buffer
  "T2TXC",                      //  22: Timer 2 SSI Transmit Complete
  "LFREOB",                     //  23: LF-Receiver End of Burst
  "EXCM",                       //  24: External Input Clock Break Down
  "EEREADY",                    //  25: EEPROM Ready
  "SPM_RDY",                    //  26: Store Program Memory Ready
};

const char * const vtab_ata8515[vts_ata8515] = { // ATA8515, ATA8510, ATA8215, ATA8210, ATA5833, ATA5832, ATA5831, ATA5783, ATA5782, ATA5781
  "RESET",                      //   0: Reset (various reasons)
  "INT0",                       //   1: External Interrupt 0
  "INT1",                       //   2: External Interrupt 1
  "PCI0",                       //   3: Pin Change Interrupt Request 0
  "PCI1",                       //   4: Pin Change Interrupt Request 1
  "VMON",                       //   5: Voltage Monitoring
  "AVCCR",                      //   6: AVCC Reset
  "AVCCL",                      //   7: AVCC Low
  "T0INT",                      //   8: Timer 0 Interrupt
  "T1COMP",                     //   9: Timer 1 Compare and Match
  "T1OVF",                      //  10: Timer 1 Overflow
  "T2COMP",                     //  11: Timer 2 Compare and Match
  "T2OVF",                      //  12: Timer 2 Overflow
  "T3CAP",                      //  13: Timer 3 Capture Event
  "T3COMP",                     //  14: Timer 3 Compare and Match
  "T3OVF",                      //  15: Timer 3 Overflow
  "T4CAP",                      //  16: Timer 4 Capture Event
  "T4COMP",                     //  17: Timer 4 Compare and Match
  "T4OVF",                      //  18: Timer 4 Overflow
  "T5COMP",                     //  19: Timer 5 Compare and Match
  "T5OVF",                      //  20: Timer 5 Overflow
  "SPI",                        //  21: SPI Serial Peripheral Interface
  "SRX_FIFO",                   //  22: SPI Receive Buffer
  "STX_FIFO",                   //  23: SPI Transmit Buffer
  "SSM",                        //  24: Sequencer State Machine
  "DFFLR",                      //  25: Data FIFO Fill Level Reached
  "DFOUE",                      //  26: Data FIFO Overflow or Underflow Error
  "SFFLR",                      //  27: RSSI/Preamble FIFO Fill Level Reached
  "SFOUE",                      //  28: RSSI/Preamble FIFO Overflow or Underflow Error
  "TMTCF",                      //  29: Transmit Modulator Telegram Finished
  "UHF_WCOB",                   //  30: UHF Receiver Wake Up OK on Receive Path B
  "UHF_WCOA",                   //  31: UHF Receiver Wake Up OK on Receive Path A
  "UHF_SOTB",                   //  32: UHF Receiver Start of Telegram OK on Receive Path B
  "UHF_SOTA",                   //  33: UHF Receiver Start of Telegram OK on Receive Path A
  "UHF_EOTB",                   //  34: UHF Receiver End of Telegram on Receive Path B
  "UHF_EOTA",                   //  35: UHF Receiver End of Telegram on Receive Path A
  "UHF_NBITB",                  //  36: UHF Receiver New Bit on Receive Path B
  "UHF_NBITA",                  //  37: UHF Receiver New Bit on Receive Path A
  "EXCM",                       //  38: External Input Clock Break Down
  "ERDY",                       //  39: EEPROM Ready
  "SPMR",                       //  40: Store Program Memory Ready
  "IDFULL",                     //  41: IDSCAN Full
};

const char * const vtab_atxmega32a4[vts_atxmega32a4] = { // ATxmega32A4, ATxmega16A4
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF",                   //  14: TC C0 Overflow
  "TCC0_ERR",                   //  15: TC C0 Error
  "TCC0_CCA",                   //  16: TC C0 Compare or Capture A
  "TCC0_CCB",                   //  17: TC C0 Compare or Capture B
  "TCC0_CCC",                   //  18: TC C0 Compare or Capture C
  "TCC0_CCD",                   //  19: TC C0 Compare or Capture D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "HIRESE_OVF",                 //  53: High-resolution Extension Overflow
  "HIRESE_ERR",                 //  54: High-resolution Extension Error
  "HIRESE_CCA",                 //  55: High-resolution Extension Compare and Capture A
  "HIRESE_CCB",                 //  56: High-resolution Extension Compare and Capture B
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF",                   //  77: TC D0 Overflow
  "TCD0_ERR",                   //  78: TC D0 Error
  "TCD0_CCA",                   //  79: TC D0 Compare or Capture A
  "TCD0_CCB",                   //  80: TC D0 Compare or Capture B
  "TCD0_CCC",                   //  81: TC D0 Compare or Capture C
  "TCD0_CCD",                   //  82: TC D0 Compare or Capture D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
};

const char * const vtab_atxmega32c4[vts_atxmega32c4] = { // ATxmega32C4, ATxmega16C4
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "UNUSED",                     //   6: not implemented on this device
  "UNUSED",                     //   7: not implemented on this device
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "UNUSED",                     //  31: not implemented on this device
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "UNUSED",                     //  58: not implemented on this device
  "UNUSED",                     //  59: not implemented on this device
  "UNUSED",                     //  60: not implemented on this device
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "UNUSED",                     //  91: not implemented on this device
  "UNUSED",                     //  92: not implemented on this device
  "UNUSED",                     //  93: not implemented on this device
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "UNUSED",                     // 104: not implemented on this device
  "UNUSED",                     // 105: not implemented on this device
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "UNUSED",                     // 108: not implemented on this device
  "UNUSED",                     // 109: not implemented on this device
  "UNUSED",                     // 110: not implemented on this device
  "UNUSED",                     // 111: not implemented on this device
  "UNUSED",                     // 112: not implemented on this device
  "UNUSED",                     // 113: not implemented on this device
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "UNUSED",                     // 119: not implemented on this device
  "UNUSED",                     // 120: not implemented on this device
  "UNUSED",                     // 121: not implemented on this device
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega32d4[vts_atxmega32d4] = { // ATxmega32D4, ATxmega16D4
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "UNUSED",                     //   6: not implemented on this device
  "UNUSED",                     //   7: not implemented on this device
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "UNUSED",                     //  31: not implemented on this device
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "UNUSED",                     //  58: not implemented on this device
  "UNUSED",                     //  59: not implemented on this device
  "UNUSED",                     //  60: not implemented on this device
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF",                   //  77: TC D0 Overflow
  "TCD0_ERR",                   //  78: TC D0 Error
  "TCD0_CCA",                   //  79: TC D0 Compare or Capture A
  "TCD0_CCB",                   //  80: TC D0 Compare or Capture B
  "TCD0_CCC",                   //  81: TC D0 Compare or Capture C
  "TCD0_CCD",                   //  82: TC D0 Compare or Capture D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
};

const char * const vtab_atxmega32e5[vts_atxmega32e5] = { // ATxmega32E5, ATxmega16E5, ATxmega8E5
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTR_INT",                  //   2: External Interrupt PORT R
  "EDMA_CH0",                   //   3: External DMA Channel 0
  "EDMA_CH1",                   //   4: External DMA Channel 1
  "EDMA_CH2",                   //   5: External DMA Channel 2
  "EDMA_CH3",                   //   6: External DMA Channel 3
  "RTC_OVF",                    //   7: RTC Overflow
  "RTC_COMP",                   //   8: RTC Compare
  "PORTC_INT",                  //   9: External Interrupt PORT C
  "TWIC_TWIS",                  //  10: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  11: 2-Wire Interface C Controller
  "TCC4_OVF",                   //  12: TC C4 Overflow
  "TCC4_ERR",                   //  13: TC C4 Error
  "TCC4_CCA",                   //  14: TC C4 Compare or Capture A
  "TCC4_CCB",                   //  15: TC C4 Compare or Capture B
  "TCC4_CCC",                   //  16: TC C4 Compare or Capture C
  "TCC4_CCD",                   //  17: TC C4 Compare or Capture D
  "TCC5_OVF",                   //  18: TC C5 Overflow
  "TCC5_ERR",                   //  19: TC C5 Error
  "TCC5_CCA",                   //  20: TC C5 Compare or Capture A
  "TCC5_CCB",                   //  21: TC C5 Compare or Capture B
  "SPIC_INT",                   //  22: SPI C Interrupt
  "USARTC0_RXC",                //  23: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  24: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  25: USARTC 0 Transmission Complete
  "NVM_EE",                     //  26: NVM EEPROM
  "NVM_SPM",                    //  27: NVM SPM
  "XCL_UNF",                    //  28: XMEGA Custom Logic Underflow
  "XCL_CC",                     //  29: XMEGA Custom Logic Compare or Capture
  "PORTA_INT",                  //  30: External Interrupt PORT A
  "ACA_AC0",                    //  31: ACA AC 0 Interrupt
  "ACA_AC1",                    //  32: ACA AC 1 Interrupt
  "ACA_ACW",                    //  33: ACA AC Window Mode
  "ADCA_CH0",                   //  34: ADCA Interrupt 0
  "PORTD_INT",                  //  35: External Interrupt PORT D
  "TCD5_OVF",                   //  36: TC D5 Overflow
  "TCD5_ERR",                   //  37: TC D5 Error
  "TCD5_CCA",                   //  38: TC D5 Compare or Capture A
  "TCD5_CCB",                   //  39: TC D5 Compare or Capture B
  "USARTD0_RXC",                //  40: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  41: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  42: USARTD 0 Transmission Complete
};

const char * const vtab_atxmega128a1[vts_atxmega128a1] = { // ATxmega128A1, ATxmega64A1
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF",                   //  14: TC C0 Overflow
  "TCC0_ERR",                   //  15: TC C0 Error
  "TCC0_CCA",                   //  16: TC C0 Compare or Capture A
  "TCC0_CCB",                   //  17: TC C0 Compare or Capture B
  "TCC0_CCC",                   //  18: TC C0 Compare or Capture C
  "TCC0_CCD",                   //  19: TC C0 Compare or Capture D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "SPIE_INT",                   //  57: SPI E Interrupt
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "USARTE1_RXC",                //  61: USARTE 1 Reception Complete
  "USARTE1_DRE",                //  62: USARTE 1 Data Register Empty
  "USARTE1_TXC",                //  63: USARTE 1 Transmission Complete
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "TWID_TWIS",                  //  75: 2-Wire Interface D Periphery
  "TWID_TWIM",                  //  76: 2-Wire Interface D Controller
  "TCD0_OVF",                   //  77: TC D0 Overflow
  "TCD0_ERR",                   //  78: TC D0 Error
  "TCD0_CCA",                   //  79: TC D0 Compare or Capture A
  "TCD0_CCB",                   //  80: TC D0 Compare or Capture B
  "TCD0_CCC",                   //  81: TC D0 Compare or Capture C
  "TCD0_CCD",                   //  82: TC D0 Compare or Capture D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "PORTQ_INT0",                 //  94: External Interrupt 0 PORT Q
  "PORTQ_INT1",                 //  95: External Interrupt 1 PORT Q
  "PORTH_INT0",                 //  96: External Interrupt 0 PORT H
  "PORTH_INT1",                 //  97: External Interrupt 1 PORT H
  "PORTJ_INT0",                 //  98: External Interrupt 0 PORT J
  "PORTJ_INT1",                 //  99: External Interrupt 1 PORT J
  "PORTK_INT0",                 // 100: External Interrupt 0 PORT K
  "PORTK_INT1",                 // 101: External Interrupt 1 PORT K
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "TWIF_TWIS",                  // 106: 2-Wire Interface F Periphery
  "TWIF_TWIM",                  // 107: 2-Wire Interface F Controller
  "TCF0_OVF",                   // 108: TC F0 Overflow
  "TCF0_ERR",                   // 109: TC F0 Error
  "TCF0_CCA",                   // 110: TC F0 Compare or Capture A
  "TCF0_CCB",                   // 111: TC F0 Compare or Capture B
  "TCF0_CCC",                   // 112: TC F0 Compare or Capture C
  "TCF0_CCD",                   // 113: TC F0 Compare or Capture D
  "TCF1_OVF",                   // 114: TC F1 Overflow
  "TCF1_ERR",                   // 115: TC F1 Error
  "TCF1_CCA",                   // 116: TC F1 Compare or Capture A
  "TCF1_CCB",                   // 117: TC F1 Compare or Capture B
  "SPIF_INT",                   // 118: SPI F Interrupt
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
  "USARTF1_RXC",                // 122: USARTF 1 Reception Complete
  "USARTF1_DRE",                // 123: USARTF 1 Data Register Empty
  "USARTF1_TXC",                // 124: USARTF 1 Transmission Complete
};

const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { // ATxmega128A1U, ATxmega64A1U
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "SPIE_INT",                   //  57: SPI E Interrupt
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "USARTE1_RXC",                //  61: USARTE 1 Reception Complete
  "USARTE1_DRE",                //  62: USARTE 1 Data Register Empty
  "USARTE1_TXC",                //  63: USARTE 1 Transmission Complete
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "TWID_TWIS",                  //  75: 2-Wire Interface D Periphery
  "TWID_TWIM",                  //  76: 2-Wire Interface D Controller
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "PORTQ_INT0",                 //  94: External Interrupt 0 PORT Q
  "PORTQ_INT1",                 //  95: External Interrupt 1 PORT Q
  "PORTH_INT0",                 //  96: External Interrupt 0 PORT H
  "PORTH_INT1",                 //  97: External Interrupt 1 PORT H
  "PORTJ_INT0",                 //  98: External Interrupt 0 PORT J
  "PORTJ_INT1",                 //  99: External Interrupt 1 PORT J
  "PORTK_INT0",                 // 100: External Interrupt 0 PORT K
  "PORTK_INT1",                 // 101: External Interrupt 1 PORT K
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "TWIF_TWIS",                  // 106: 2-Wire Interface F Periphery
  "TWIF_TWIM",                  // 107: 2-Wire Interface F Controller
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
  "TCF1_OVF",                   // 114: TC F1 Overflow
  "TCF1_ERR",                   // 115: TC F1 Error
  "TCF1_CCA",                   // 116: TC F1 Compare or Capture A
  "TCF1_CCB",                   // 117: TC F1 Compare or Capture B
  "SPIF_INT",                   // 118: SPI F Interrupt
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
  "USARTF1_RXC",                // 122: USARTF 1 Reception Complete
  "USARTF1_DRE",                // 123: USARTF 1 Data Register Empty
  "USARTF1_TXC",                // 124: USARTF 1 Transmission Complete
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega128b1[vts_atxmega128b1] = { // ATxmega128B1, ATxmega64B1
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "USB_BUSEVENT",               //  31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               //  32: USB Transaction Complete
  "UNUSED",                     //  33: not implemented on this device
  "UNUSED",                     //  34: not implemented on this device
  "LCD_INT",                    //  35: LCD Interrupt
  "AES_INT",                    //  36: AES Interrupt
  "NVM_EE",                     //  37: NVM EEPROM
  "NVM_SPM",                    //  38: NVM SPM
  "PORTB_INT0",                 //  39: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  40: External Interrupt 1 PORT B
  "ACB_AC0",                    //  41: ACB AC 0 Interrupt
  "ACB_AC1",                    //  42: ACB AC 1 Interrupt
  "ACB_ACW",                    //  43: ACB AC Window Mode
  "ADCB_CH0",                   //  44: ADCB Interrupt 0
  "UNUSED",                     //  45: not implemented on this device
  "UNUSED",                     //  46: not implemented on this device
  "UNUSED",                     //  47: not implemented on this device
  "PORTD_INT0",                 //  48: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  49: External Interrupt 1 PORT D
  "PORTG_INT0",                 //  50: External Interrupt 0 PORT G
  "PORTG_INT1",                 //  51: External Interrupt 1 PORT G
  "PORTM_INT0",                 //  52: External Interrupt 0 PORT M
  "PORTM_INT1",                 //  53: External Interrupt 1 PORT M
  "PORTE_INT0",                 //  54: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  55: External Interrupt 1 PORT E
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "TCE0_OVF/TCE2_LUNF",         //  58: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  59: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  60: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  61: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  62: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  63: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "UNUSED",                     //  64: not implemented on this device
  "UNUSED",                     //  65: not implemented on this device
  "UNUSED",                     //  66: not implemented on this device
  "UNUSED",                     //  67: not implemented on this device
  "UNUSED",                     //  68: not implemented on this device
  "USARTE0_RXC",                //  69: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  70: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  71: USARTE 0 Transmission Complete
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "PORTA_INT0",                 //  75: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  76: External Interrupt 1 PORT A
  "ACA_AC0",                    //  77: ACA AC 0 Interrupt
  "ACA_AC1",                    //  78: ACA AC 1 Interrupt
  "ACA_ACW",                    //  79: ACA AC Window Mode
  "ADCA_CH0",                   //  80: ADCA Interrupt 0
};

const char * const vtab_atxmega128b3[vts_atxmega128b3] = { // ATxmega128B3, ATxmega64B3
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "USB_BUSEVENT",               //  31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               //  32: USB Transaction Complete
  "UNUSED",                     //  33: not implemented on this device
  "UNUSED",                     //  34: not implemented on this device
  "LCD_INT",                    //  35: LCD Interrupt
  "AES_INT",                    //  36: AES Interrupt
  "NVM_EE",                     //  37: NVM EEPROM
  "NVM_SPM",                    //  38: NVM SPM
  "PORTB_INT0",                 //  39: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  40: External Interrupt 1 PORT B
  "ACB_AC0",                    //  41: ACB AC 0 Interrupt
  "ACB_AC1",                    //  42: ACB AC 1 Interrupt
  "ACB_ACW",                    //  43: ACB AC Window Mode
  "ADCB_CH0",                   //  44: ADCB Interrupt 0
  "UNUSED",                     //  45: not implemented on this device
  "UNUSED",                     //  46: not implemented on this device
  "UNUSED",                     //  47: not implemented on this device
  "PORTD_INT0",                 //  48: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  49: External Interrupt 1 PORT D
  "PORTG_INT0",                 //  50: External Interrupt 0 PORT G
  "PORTG_INT1",                 //  51: External Interrupt 1 PORT G
  "PORTM_INT0",                 //  52: External Interrupt 0 PORT M
  "PORTM_INT1",                 //  53: External Interrupt 1 PORT M
};

const char * const vtab_atxmega128a4u[vts_atxmega128a4u] = { // ATxmega128A4U, ATxmega64A4U, ATxmega32A4U, ATxmega16A4U
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "UNUSED",                     // 104: not implemented on this device
  "UNUSED",                     // 105: not implemented on this device
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "UNUSED",                     // 108: not implemented on this device
  "UNUSED",                     // 109: not implemented on this device
  "UNUSED",                     // 110: not implemented on this device
  "UNUSED",                     // 111: not implemented on this device
  "UNUSED",                     // 112: not implemented on this device
  "UNUSED",                     // 113: not implemented on this device
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "UNUSED",                     // 119: not implemented on this device
  "UNUSED",                     // 120: not implemented on this device
  "UNUSED",                     // 121: not implemented on this device
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega128d4[vts_atxmega128d4] = { // ATxmega128D4, ATxmega64D4
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "UNUSED",                     //   6: not implemented on this device
  "UNUSED",                     //   7: not implemented on this device
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "UNUSED",                     //  31: not implemented on this device
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
};

const char * const vtab_atxmega256a3[vts_atxmega256a3] = { // ATxmega256A3, ATxmega192A3, ATxmega128A3, ATxmega64A3
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF",                   //  14: TC C0 Overflow
  "TCC0_ERR",                   //  15: TC C0 Error
  "TCC0_CCA",                   //  16: TC C0 Compare or Capture A
  "TCC0_CCB",                   //  17: TC C0 Compare or Capture B
  "TCC0_CCC",                   //  18: TC C0 Compare or Capture C
  "TCC0_CCD",                   //  19: TC C0 Compare or Capture D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "SPIE_INT",                   //  57: SPI E Interrupt
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "USARTE1_RXC",                //  61: USARTE 1 Reception Complete
  "USARTE1_DRE",                //  62: USARTE 1 Data Register Empty
  "USARTE1_TXC",                //  63: USARTE 1 Transmission Complete
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF",                   //  77: TC D0 Overflow
  "TCD0_ERR",                   //  78: TC D0 Error
  "TCD0_CCA",                   //  79: TC D0 Compare or Capture A
  "TCD0_CCB",                   //  80: TC D0 Compare or Capture B
  "TCD0_CCC",                   //  81: TC D0 Compare or Capture C
  "TCD0_CCD",                   //  82: TC D0 Compare or Capture D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF",                   // 108: TC F0 Overflow
  "TCF0_ERR",                   // 109: TC F0 Error
  "TCF0_CCA",                   // 110: TC F0 Compare or Capture A
  "TCF0_CCB",                   // 111: TC F0 Compare or Capture B
  "TCF0_CCC",                   // 112: TC F0 Compare or Capture C
  "TCF0_CCD",                   // 113: TC F0 Compare or Capture D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
};

const char * const vtab_atxmega256a3b[vts_atxmega256a3b] = { // ATxmega256A3B
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC32_OVF",                  //  10: RTC32 Overflow
  "RTC32_COMP",                 //  11: RTC32 Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF",                   //  14: TC C0 Overflow
  "TCC0_ERR",                   //  15: TC C0 Error
  "TCC0_CCA",                   //  16: TC C0 Compare or Capture A
  "TCC0_CCB",                   //  17: TC C0 Compare or Capture B
  "TCC0_CCC",                   //  18: TC C0 Compare or Capture C
  "TCC0_CCD",                   //  19: TC C0 Compare or Capture D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF",                   //  47: TC E0 Overflow
  "TCE0_ERR",                   //  48: TC E0 Error
  "TCE0_CCA",                   //  49: TC E0 Compare or Capture A
  "TCE0_CCB",                   //  50: TC E0 Compare or Capture B
  "TCE0_CCC",                   //  51: TC E0 Compare or Capture C
  "TCE0_CCD",                   //  52: TC E0 Compare or Capture D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF",                   //  77: TC D0 Overflow
  "TCD0_ERR",                   //  78: TC D0 Error
  "TCD0_CCA",                   //  79: TC D0 Compare or Capture A
  "TCD0_CCB",                   //  80: TC D0 Compare or Capture B
  "TCD0_CCC",                   //  81: TC D0 Compare or Capture C
  "TCD0_CCD",                   //  82: TC D0 Compare or Capture D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF",                   // 108: TC F0 Overflow
  "TCF0_ERR",                   // 109: TC F0 Error
  "TCF0_CCA",                   // 110: TC F0 Compare or Capture A
  "TCF0_CCB",                   // 111: TC F0 Compare or Capture B
  "TCF0_CCC",                   // 112: TC F0 Compare or Capture C
  "TCF0_CCD",                   // 113: TC F0 Compare or Capture D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
};

const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { // ATxmega256A3BU
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC32_OVF",                  //  10: RTC32 Overflow
  "RTC32_COMP",                 //  11: RTC32 Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { // ATxmega256A3U, ATxmega192A3U, ATxmega128A3U, ATxmega64A3U
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "DMA_CH2",                    //   8: DMA Channel 2
  "DMA_CH3",                    //   9: DMA Channel 3
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "ACB_AC0",                    //  36: ACB AC 0 Interrupt
  "ACB_AC1",                    //  37: ACB AC 1 Interrupt
  "ACB_ACW",                    //  38: ACB AC Window Mode
  "ADCB_CH0",                   //  39: ADCB Interrupt 0
  "ADCB_CH1",                   //  40: ADCB Interrupt 1
  "ADCB_CH2",                   //  41: ADCB Interrupt 2
  "ADCB_CH3",                   //  42: ADCB Interrupt 3
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "TCE1_OVF",                   //  53: TC E1 Overflow
  "TCE1_ERR",                   //  54: TC E1 Error
  "TCE1_CCA",                   //  55: TC E1 Compare or Capture A
  "TCE1_CCB",                   //  56: TC E1 Compare or Capture B
  "SPIE_INT",                   //  57: SPI E Interrupt
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "USARTE1_RXC",                //  61: USARTE 1 Reception Complete
  "USARTE1_DRE",                //  62: USARTE 1 Data Register Empty
  "USARTE1_TXC",                //  63: USARTE 1 Transmission Complete
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "ADCA_CH1",                   //  72: ADCA Interrupt 1
  "ADCA_CH2",                   //  73: ADCA Interrupt 2
  "ADCA_CH3",                   //  74: ADCA Interrupt 3
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "TCD1_OVF",                   //  83: TC D1 Overflow
  "TCD1_ERR",                   //  84: TC D1 Error
  "TCD1_CCA",                   //  85: TC D1 Compare or Capture A
  "TCD1_CCB",                   //  86: TC D1 Compare or Capture B
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "USARTD1_RXC",                //  91: USARTD 1 Reception Complete
  "USARTD1_DRE",                //  92: USARTD 1 Data Register Empty
  "USARTD1_TXC",                //  93: USARTD 1 Transmission Complete
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "USARTF0_RXC",                // 119: USARTF 0 Reception Complete
  "USARTF0_DRE",                // 120: USARTF 0 Data Register Empty
  "USARTF0_TXC",                // 121: USARTF 0 Transmission Complete
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega256c3[vts_atxmega256c3] = { // ATxmega256C3, ATxmega192C3, ATxmega128C3, ATxmega64C3, ATxmega32C3
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "UNUSED",                     //   6: not implemented on this device
  "UNUSED",                     //   7: not implemented on this device
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "UNUSED",                     //  31: not implemented on this device
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "UNUSED",                     //  91: not implemented on this device
  "UNUSED",                     //  92: not implemented on this device
  "UNUSED",                     //  93: not implemented on this device
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "UNUSED",                     // 119: not implemented on this device
  "UNUSED",                     // 120: not implemented on this device
  "UNUSED",                     // 121: not implemented on this device
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega384c3[vts_atxmega384c3] = { // ATxmega384C3
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "DMA_CH0",                    //   6: DMA Channel 0
  "DMA_CH1",                    //   7: DMA Channel 1
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "USARTC1_RXC",                //  28: USARTC 1 Reception Complete
  "USARTC1_DRE",                //  29: USARTC 1 Data Register Empty
  "USARTC1_TXC",                //  30: USARTC 1 Transmission Complete
  "AES_INT",                    //  31: AES Interrupt
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "UNUSED",                     //  91: not implemented on this device
  "UNUSED",                     //  92: not implemented on this device
  "UNUSED",                     //  93: not implemented on this device
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
  "UNUSED",                     // 114: not implemented on this device
  "UNUSED",                     // 115: not implemented on this device
  "UNUSED",                     // 116: not implemented on this device
  "UNUSED",                     // 117: not implemented on this device
  "UNUSED",                     // 118: not implemented on this device
  "UNUSED",                     // 119: not implemented on this device
  "UNUSED",                     // 120: not implemented on this device
  "UNUSED",                     // 121: not implemented on this device
  "UNUSED",                     // 122: not implemented on this device
  "UNUSED",                     // 123: not implemented on this device
  "UNUSED",                     // 124: not implemented on this device
  "USB_BUSEVENT",               // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error
  "USB_TRNCOMPL",               // 126: USB Transaction Complete
};

const char * const vtab_atxmega384d3[vts_atxmega384d3] = { // ATxmega384D3, ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3, ATxmega32D3
  "RESET",                      //   0: Reset (various reasons)
  "OSC_OSCF",                   //   1: Oscillator Failure NMI
  "PORTC_INT0",                 //   2: External Interrupt 0 PORT C
  "PORTC_INT1",                 //   3: External Interrupt 1 PORT C
  "PORTR_INT0",                 //   4: External Interrupt 0 PORT R
  "PORTR_INT1",                 //   5: External Interrupt 1 PORT R
  "UNUSED",                     //   6: not implemented on this device
  "UNUSED",                     //   7: not implemented on this device
  "UNUSED",                     //   8: not implemented on this device
  "UNUSED",                     //   9: not implemented on this device
  "RTC_OVF",                    //  10: RTC Overflow
  "RTC_COMP",                   //  11: RTC Compare
  "TWIC_TWIS",                  //  12: 2-Wire Interface C Periphery
  "TWIC_TWIM",                  //  13: 2-Wire Interface C Controller
  "TCC0_OVF/TCC2_LUNF",         //  14: TC C0 Overflow/TC C2 Low Byte Underflow
  "TCC0_ERR/TCC2_HUNF",         //  15: TC C0 Error/TC C2 High Byte Underflow
  "TCC0_CCA/TCC2_LCMPA",        //  16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A
  "TCC0_CCB/TCC2_LCMPB",        //  17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B
  "TCC0_CCC/TCC2_LCMPC",        //  18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C
  "TCC0_CCD/TCC2_LCMPD",        //  19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D
  "TCC1_OVF",                   //  20: TC C1 Overflow
  "TCC1_ERR",                   //  21: TC C1 Error
  "TCC1_CCA",                   //  22: TC C1 Compare or Capture A
  "TCC1_CCB",                   //  23: TC C1 Compare or Capture B
  "SPIC_INT",                   //  24: SPI C Interrupt
  "USARTC0_RXC",                //  25: USARTC 0 Reception Complete
  "USARTC0_DRE",                //  26: USARTC 0 Data Register Empty
  "USARTC0_TXC",                //  27: USARTC 0 Transmission Complete
  "UNUSED",                     //  28: not implemented on this device
  "UNUSED",                     //  29: not implemented on this device
  "UNUSED",                     //  30: not implemented on this device
  "UNUSED",                     //  31: not implemented on this device
  "NVM_EE",                     //  32: NVM EEPROM
  "NVM_SPM",                    //  33: NVM SPM
  "PORTB_INT0",                 //  34: External Interrupt 0 PORT B
  "PORTB_INT1",                 //  35: External Interrupt 1 PORT B
  "UNUSED",                     //  36: not implemented on this device
  "UNUSED",                     //  37: not implemented on this device
  "UNUSED",                     //  38: not implemented on this device
  "UNUSED",                     //  39: not implemented on this device
  "UNUSED",                     //  40: not implemented on this device
  "UNUSED",                     //  41: not implemented on this device
  "UNUSED",                     //  42: not implemented on this device
  "PORTE_INT0",                 //  43: External Interrupt 0 PORT E
  "PORTE_INT1",                 //  44: External Interrupt 1 PORT E
  "TWIE_TWIS",                  //  45: 2-Wire Interface E Periphery
  "TWIE_TWIM",                  //  46: 2-Wire Interface E Controller
  "TCE0_OVF/TCE2_LUNF",         //  47: TC E0 Overflow/TC E2 Low Byte Underflow
  "TCE0_ERR/TCE2_HUNF",         //  48: TC E0 Error/TC E2 High Byte Underflow
  "TCE0_CCA/TCE2_LCMPA",        //  49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A
  "TCE0_CCB/TCE2_LCMPB",        //  50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B
  "TCE0_CCC/TCE2_LCMPC",        //  51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C
  "TCE0_CCD/TCE2_LCMPD",        //  52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D
  "UNUSED",                     //  53: not implemented on this device
  "UNUSED",                     //  54: not implemented on this device
  "UNUSED",                     //  55: not implemented on this device
  "UNUSED",                     //  56: not implemented on this device
  "UNUSED",                     //  57: not implemented on this device
  "USARTE0_RXC",                //  58: USARTE 0 Reception Complete
  "USARTE0_DRE",                //  59: USARTE 0 Data Register Empty
  "USARTE0_TXC",                //  60: USARTE 0 Transmission Complete
  "UNUSED",                     //  61: not implemented on this device
  "UNUSED",                     //  62: not implemented on this device
  "UNUSED",                     //  63: not implemented on this device
  "PORTD_INT0",                 //  64: External Interrupt 0 PORT D
  "PORTD_INT1",                 //  65: External Interrupt 1 PORT D
  "PORTA_INT0",                 //  66: External Interrupt 0 PORT A
  "PORTA_INT1",                 //  67: External Interrupt 1 PORT A
  "ACA_AC0",                    //  68: ACA AC 0 Interrupt
  "ACA_AC1",                    //  69: ACA AC 1 Interrupt
  "ACA_ACW",                    //  70: ACA AC Window Mode
  "ADCA_CH0",                   //  71: ADCA Interrupt 0
  "UNUSED",                     //  72: not implemented on this device
  "UNUSED",                     //  73: not implemented on this device
  "UNUSED",                     //  74: not implemented on this device
  "UNUSED",                     //  75: not implemented on this device
  "UNUSED",                     //  76: not implemented on this device
  "TCD0_OVF/TCD2_LUNF",         //  77: TC D0 Overflow/TC D2 Low Byte Underflow
  "TCD0_ERR/TCD2_HUNF",         //  78: TC D0 Error/TC D2 High Byte Underflow
  "TCD0_CCA/TCD2_LCMPA",        //  79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A
  "TCD0_CCB/TCD2_LCMPB",        //  80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B
  "TCD0_CCC/TCD2_LCMPC",        //  81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C
  "TCD0_CCD/TCD2_LCMPD",        //  82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D
  "UNUSED",                     //  83: not implemented on this device
  "UNUSED",                     //  84: not implemented on this device
  "UNUSED",                     //  85: not implemented on this device
  "UNUSED",                     //  86: not implemented on this device
  "SPID_INT",                   //  87: SPI D Interrupt
  "USARTD0_RXC",                //  88: USARTD 0 Reception Complete
  "USARTD0_DRE",                //  89: USARTD 0 Data Register Empty
  "USARTD0_TXC",                //  90: USARTD 0 Transmission Complete
  "UNUSED",                     //  91: not implemented on this device
  "UNUSED",                     //  92: not implemented on this device
  "UNUSED",                     //  93: not implemented on this device
  "UNUSED",                     //  94: not implemented on this device
  "UNUSED",                     //  95: not implemented on this device
  "UNUSED",                     //  96: not implemented on this device
  "UNUSED",                     //  97: not implemented on this device
  "UNUSED",                     //  98: not implemented on this device
  "UNUSED",                     //  99: not implemented on this device
  "UNUSED",                     // 100: not implemented on this device
  "UNUSED",                     // 101: not implemented on this device
  "UNUSED",                     // 102: not implemented on this device
  "UNUSED",                     // 103: not implemented on this device
  "PORTF_INT0",                 // 104: External Interrupt 0 PORT F
  "PORTF_INT1",                 // 105: External Interrupt 1 PORT F
  "UNUSED",                     // 106: not implemented on this device
  "UNUSED",                     // 107: not implemented on this device
  "TCF0_OVF/TCF2_LUNF",         // 108: TC F0 Overflow/TC F2 Low Byte Underflow
  "TCF0_ERR/TCF2_HUNF",         // 109: TC F0 Error/TC F2 High Byte Underflow
  "TCF0_CCA/TCF2_LCMPA",        // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A
  "TCF0_CCB/TCF2_LCMPB",        // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B
  "TCF0_CCC/TCF2_LCMPC",        // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C
  "TCF0_CCD/TCF2_LCMPD",        // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D
};

const char * const vtab_attiny402[vts_attiny402] = { // ATtiny402, ATtiny202
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "UNUSED",                     //   4: not implemented on this device
  "UNUSED",                     //   5: not implemented on this device
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "UNUSED",                     //  14: not implemented on this device
  "UNUSED",                     //  15: not implemented on this device
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny404[vts_attiny404] = { // ATtiny404, ATtiny204
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "UNUSED",                     //   5: not implemented on this device
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "UNUSED",                     //  14: not implemented on this device
  "UNUSED",                     //  15: not implemented on this device
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny406[vts_attiny406] = { // ATtiny406
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "PORTC_PORT",                 //   5: Interrupt PORT C
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "UNUSED",                     //  14: not implemented on this device
  "UNUSED",                     //  15: not implemented on this device
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny412[vts_attiny412] = { // ATtiny412, ATtiny212
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "UNUSED",                     //   4: not implemented on this device
  "UNUSED",                     //   5: not implemented on this device
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny814[vts_attiny814] = { // ATtiny814, ATtiny414, ATtiny214
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "UNUSED",                     //   5: not implemented on this device
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny817[vts_attiny817] = { // ATtiny817, ATtiny816, ATtiny417, ATtiny416auto, ATtiny416
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "PORTC_PORT",                 //   5: Interrupt PORT C
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "AC0_AC",                     //  16: AC0 AC Interrupt
  "ADC0_RESRDY",                //  17: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  18: ADC 0 Window Comparator
  "TWI0_TWIS",                  //  19: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  20: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  21: SPI 0 Interrupt
  "USART0_RXC",                 //  22: USART 0 Receive Complete
  "USART0_DRE",                 //  23: USART 0 Data Register Empty
  "USART0_TXC",                 //  24: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  25: NVM EEPROM
};

const char * const vtab_attiny1607[vts_attiny1607] = { // ATtiny1607, ATtiny1606, ATtiny1604, ATtiny807, ATtiny806, ATtiny804
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "PORTC_PORT",                 //   5: Interrupt PORT C
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "UNUSED",                     //  14: not implemented on this device
  "UNUSED",                     //  15: not implemented on this device
  "UNUSED",                     //  16: not implemented on this device
  "AC0_AC",                     //  17: AC0 AC Interrupt
  "UNUSED",                     //  18: not implemented on this device
  "UNUSED",                     //  19: not implemented on this device
  "ADC0_RESRDY",                //  20: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  21: ADC 0 Window Comparator
  "UNUSED",                     //  22: not implemented on this device
  "UNUSED",                     //  23: not implemented on this device
  "TWI0_TWIS",                  //  24: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  25: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  26: SPI 0 Interrupt
  "USART0_RXC",                 //  27: USART 0 Receive Complete
  "USART0_DRE",                 //  28: USART 0 Data Register Empty
  "USART0_TXC",                 //  29: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  30: NVM EEPROM
};

const char * const vtab_attiny1614[vts_attiny1614] = { // ATtiny1614
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "UNUSED",                     //   5: not implemented on this device
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCB1_INT",                   //  14: TC B1 Interrupt
  "TCD0_OVF",                   //  15: TC D0 Overflow
  "TCD0_TRIG",                  //  16: TC D0 Trigger
  "AC0_AC",                     //  17: AC0 AC Interrupt
  "AC1_AC",                     //  18: AC1 AC Interrupt
  "AC2_AC",                     //  19: AC2 AC Interrupt
  "ADC0_RESRDY",                //  20: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  21: ADC 0 Window Comparator
  "ADC1_RESRDY",                //  22: ADC 1 Result Ready
  "ADC1_WCOMP",                 //  23: ADC 1 Window Comparator
  "TWI0_TWIS",                  //  24: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  25: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  26: SPI 0 Interrupt
  "USART0_RXC",                 //  27: USART 0 Receive Complete
  "USART0_DRE",                 //  28: USART 0 Data Register Empty
  "USART0_TXC",                 //  29: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  30: NVM EEPROM
};

const char * const vtab_attiny3214[vts_attiny3214] = { // ATtiny3214
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "PORTC_PORT",                 //   5: Interrupt PORT C
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF",                  //   8: TC A0 Low Underflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0",                  //  10: TC A0 Compare 0
  "TCA0_CMP1",                  //  11: TC A0 Compare 1
  "TCA0_CMP2",                  //  12: TC A0 Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCB1_INT",                   //  14: TC B1 Interrupt
  "TCD0_OVF",                   //  15: TC D0 Overflow
  "TCD0_TRIG",                  //  16: TC D0 Trigger
  "AC0_AC",                     //  17: AC0 AC Interrupt
  "AC1_AC",                     //  18: AC1 AC Interrupt
  "AC2_AC",                     //  19: AC2 AC Interrupt
  "ADC0_RESRDY",                //  20: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  21: ADC 0 Window Comparator
  "ADC1_RESRDY",                //  22: ADC 1 Result Ready
  "ADC1_WCOMP",                 //  23: ADC 1 Window Comparator
  "TWI0_TWIS",                  //  24: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  25: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  26: SPI 0 Interrupt
  "USART0_RXC",                 //  27: USART 0 Receive Complete
  "USART0_DRE",                 //  28: USART 0 Data Register Empty
  "USART0_TXC",                 //  29: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  30: NVM EEPROM
};

const char * const vtab_attiny3217[vts_attiny3217] = { // ATtiny3217, ATtiny3216, ATtiny1617, ATtiny1616
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "PORTA_PORT",                 //   3: Interrupt PORT A
  "PORTB_PORT",                 //   4: Interrupt PORT B
  "PORTC_PORT",                 //   5: Interrupt PORT C
  "RTC_CNT",                    //   6: RTC Counter Interrupt
  "RTC_PIT",                    //   7: RTC Periodic Interrupt Timer
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCB1_INT",                   //  14: TC B1 Interrupt
  "TCD0_OVF",                   //  15: TC D0 Overflow
  "TCD0_TRIG",                  //  16: TC D0 Trigger
  "AC0_AC",                     //  17: AC0 AC Interrupt
  "AC1_AC",                     //  18: AC1 AC Interrupt
  "AC2_AC",                     //  19: AC2 AC Interrupt
  "ADC0_RESRDY",                //  20: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  21: ADC 0 Window Comparator
  "ADC1_RESRDY",                //  22: ADC 1 Result Ready
  "ADC1_WCOMP",                 //  23: ADC 1 Window Comparator
  "TWI0_TWIS",                  //  24: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  25: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  26: SPI 0 Interrupt
  "USART0_RXC",                 //  27: USART 0 Receive Complete
  "USART0_DRE",                 //  28: USART 0 Data Register Empty
  "USART0_TXC",                 //  29: USART 0 Transmit Complete
  "NVMCTRL_EE",                 //  30: NVM EEPROM
};

const char * const vtab_attiny3227[vts_attiny3227] = { // ATtiny3227, ATtiny3226, ATtiny3224, ATtiny1627, ATtiny1626, ATtiny1624, ATtiny827, ATtiny826, ATtiny824, ATtiny427, ATtiny426, ATtiny424
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "PORTB_PORT",                 //   7: Interrupt PORT B
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TWI0_TWIS",                  //  14: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  15: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  16: SPI 0 Interrupt
  "USART0_RXC",                 //  17: USART 0 Receive Complete
  "USART0_DRE",                 //  18: USART 0 Data Register Empty
  "USART0_TXC",                 //  19: USART 0 Transmit Complete
  "AC0_AC",                     //  20: AC0 AC Interrupt
  "ADC0_ERROR",                 //  21: ADC 0 Error
  "ADC0_RESRDY",                //  22: ADC 0 Result Ready
  "ADC0_SAMPRDY",               //  23: ADC 0 Sample Ready
  "PORTC_PORT",                 //  24: Interrupt PORT C
  "TCB1_INT",                   //  25: TC B1 Interrupt
  "USART1_RXC",                 //  26: USART 1 Receive Complete
  "USART1_DRE",                 //  27: USART 1 Data Register Empty
  "USART1_TXC",                 //  28: USART 1 Transmit Complete
  "NVMCTRL_EE",                 //  29: NVM EEPROM
};

const char * const vtab_atmega4808[vts_atmega4808] = { // ATmega4808, ATmega3208, ATmega1608, ATmega808
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TWI0_TWIS",                  //  14: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  15: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  16: SPI 0 Interrupt
  "USART0_RXC",                 //  17: USART 0 Receive Complete
  "USART0_DRE",                 //  18: USART 0 Data Register Empty
  "USART0_TXC",                 //  19: USART 0 Transmit Complete
  "PORTD_PORT",                 //  20: Interrupt PORT D
  "AC0_AC",                     //  21: AC0 AC Interrupt
  "ADC0_RESRDY",                //  22: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  23: ADC 0 Window Comparator
  "PORTC_PORT",                 //  24: Interrupt PORT C
  "TCB2_INT",                   //  25: TC B2 Interrupt
  "USART1_RXC",                 //  26: USART 1 Receive Complete
  "USART1_DRE",                 //  27: USART 1 Data Register Empty
  "USART1_TXC",                 //  28: USART 1 Transmit Complete
  "PORTF_PORT",                 //  29: Interrupt PORT F
  "NVMCTRL_EE",                 //  30: NVM EEPROM
  "USART2_RXC",                 //  31: USART 2 Receive Complete
  "USART2_DRE",                 //  32: USART 2 Data Register Empty
  "USART2_TXC",                 //  33: USART 2 Transmit Complete
  "PORTB_PORT",                 //  34: Interrupt PORT B
  "PORTE_PORT",                 //  35: Interrupt PORT E
};

const char * const vtab_atmega4809[vts_atmega4809] = { // ATmega4809, ATmega3209, ATmega1609, ATmega809
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TWI0_TWIS",                  //  14: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  15: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  16: SPI 0 Interrupt
  "USART0_RXC",                 //  17: USART 0 Receive Complete
  "USART0_DRE",                 //  18: USART 0 Data Register Empty
  "USART0_TXC",                 //  19: USART 0 Transmit Complete
  "PORTD_PORT",                 //  20: Interrupt PORT D
  "AC0_AC",                     //  21: AC0 AC Interrupt
  "ADC0_RESRDY",                //  22: ADC 0 Result Ready
  "ADC0_WCOMP",                 //  23: ADC 0 Window Comparator
  "PORTC_PORT",                 //  24: Interrupt PORT C
  "TCB2_INT",                   //  25: TC B2 Interrupt
  "USART1_RXC",                 //  26: USART 1 Receive Complete
  "USART1_DRE",                 //  27: USART 1 Data Register Empty
  "USART1_TXC",                 //  28: USART 1 Transmit Complete
  "PORTF_PORT",                 //  29: Interrupt PORT F
  "NVMCTRL_EE",                 //  30: NVM EEPROM
  "USART2_RXC",                 //  31: USART 2 Receive Complete
  "USART2_DRE",                 //  32: USART 2 Data Register Empty
  "USART2_TXC",                 //  33: USART 2 Transmit Complete
  "PORTB_PORT",                 //  34: Interrupt PORT B
  "PORTE_PORT",                 //  35: Interrupt PORT E
  "TCB3_INT",                   //  36: TC B3 Interrupt
  "USART3_RXC",                 //  37: USART 3 Receive Complete
  "USART3_DRE",                 //  38: USART 3 Data Register Empty
  "USART3_TXC",                 //  39: USART 3 Transmit Complete
};

const char * const vtab_avr64dd32[vts_avr64dd32] = { // AVR64DD32, AVR64DD28, AVR64DD20, AVR64DD14, AVR32DD32, AVR32DD28, AVR32DD20, AVR32DD14, AVR16DD32, AVR16DD28, AVR16DD20, AVR16DD14
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "MVIO_MVIO",                  //   4: Multi-Voltage I/O
  "RTC_CNT",                    //   5: RTC Counter Interrupt
  "RTC_PIT",                    //   6: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   7: Configurable Custom Logic
  "PORTA_PORT",                 //   8: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   9: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //  10: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  11: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  12: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  13: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  14: TC B0 Interrupt
  "TCB1_INT",                   //  15: TC B1 Interrupt
  "TCD0_OVF",                   //  16: TC D0 Overflow
  "TCD0_TRIG",                  //  17: TC D0 Trigger
  "TWI0_TWIS",                  //  18: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  19: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  20: SPI 0 Interrupt
  "USART0_RXC",                 //  21: USART 0 Receive Complete
  "USART0_DRE",                 //  22: USART 0 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "PORTD_PORT",                 //  24: Interrupt PORT D
  "AC0_AC",                     //  25: AC0 AC Interrupt
  "ADC0_RESRDY",                //  26: ADC 0 Result Ready
  "ADC0_WCMP",                  //  27: ADC 0 Window Comparator
  "ZCD3_ZCD",                   //  28: Zero Cross Detect 3
  "PORTC_PORT",                 //  29: Interrupt PORT C
  "TCB2_INT",                   //  30: TC B2 Interrupt
  "USART1_RXC",                 //  31: USART 1 Receive Complete
  "USART1_DRE",                 //  32: USART 1 Data Register Empty
  "USART1_TXC",                 //  33: USART 1 Transmit Complete
  "PORTF_PORT",                 //  34: Interrupt PORT F
  "NVMCTRL_EE",                 //  35: NVM EEPROM
};

const char * const vtab_avr64ea32[vts_avr64ea32] = { // AVR64EA32, AVR64EA28
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "RTC_CNT",                    //   4: RTC Counter Interrupt
  "RTC_PIT",                    //   5: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   6: Configurable Custom Logic
  "PORTA_PORT",                 //   7: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCB1_INT",                   //  14: TC B1 Interrupt
  "TWI0_TWIS",                  //  15: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  16: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  17: SPI 0 Interrupt
  "USART0_RXC",                 //  18: USART 0 Receive Complete
  "USART0_DRE",                 //  19: USART 0 Data Register Empty
  "USART0_TXC",                 //  20: USART 0 Transmit Complete
  "PORTD_PORT",                 //  21: Interrupt PORT D
  "AC0_AC",                     //  22: AC0 AC Interrupt
  "ADC0_ERROR",                 //  23: ADC 0 Error
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_SAMPRDY",               //  25: ADC 0 Sample Ready
  "AC1_AC",                     //  26: AC1 AC Interrupt
  "PORTC_PORT",                 //  27: Interrupt PORT C
  "TCB2_INT",                   //  28: TC B2 Interrupt
  "USART1_RXC",                 //  29: USART 1 Receive Complete
  "USART1_DRE",                 //  30: USART 1 Data Register Empty
  "USART1_TXC",                 //  31: USART 1 Transmit Complete
  "PORTF_PORT",                 //  32: Interrupt PORT F
  "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", //  33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready
  "USART2_RXC",                 //  34: USART 2 Receive Complete
  "USART2_DRE",                 //  35: USART 2 Data Register Empty
  "USART2_TXC",                 //  36: USART 2 Transmit Complete
};

const char * const vtab_avr64ea48[vts_avr64ea48] = { // AVR64EA48
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "RTC_CNT",                    //   4: RTC Counter Interrupt
  "RTC_PIT",                    //   5: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   6: Configurable Custom Logic
  "PORTA_PORT",                 //   7: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   8: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   9: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  10: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  11: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  12: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  13: TC B0 Interrupt
  "TCB1_INT",                   //  14: TC B1 Interrupt
  "TWI0_TWIS",                  //  15: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  16: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  17: SPI 0 Interrupt
  "USART0_RXC",                 //  18: USART 0 Receive Complete
  "USART0_DRE",                 //  19: USART 0 Data Register Empty
  "USART0_TXC",                 //  20: USART 0 Transmit Complete
  "PORTD_PORT",                 //  21: Interrupt PORT D
  "AC0_AC",                     //  22: AC0 AC Interrupt
  "ADC0_ERROR",                 //  23: ADC 0 Error
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_SAMPRDY",               //  25: ADC 0 Sample Ready
  "AC1_AC",                     //  26: AC1 AC Interrupt
  "PORTC_PORT",                 //  27: Interrupt PORT C
  "TCB2_INT",                   //  28: TC B2 Interrupt
  "USART1_RXC",                 //  29: USART 1 Receive Complete
  "USART1_DRE",                 //  30: USART 1 Data Register Empty
  "USART1_TXC",                 //  31: USART 1 Transmit Complete
  "PORTF_PORT",                 //  32: Interrupt PORT F
  "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", //  33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready
  "USART2_RXC",                 //  34: USART 2 Receive Complete
  "USART2_DRE",                 //  35: USART 2 Data Register Empty
  "USART2_TXC",                 //  36: USART 2 Transmit Complete
  "TCB3_INT",                   //  37: TC B3 Interrupt
  "TCA1_LUNF/TCA1_OVF",         //  38: TC A1 Low Underflow/TC A1 Overflow
  "TCA1_HUNF",                  //  39: TC A1 High Underflow
  "TCA1_CMP0/TCA1_LCMP0",       //  40: TC A1 Compare 0/TC A1 Low Compare 0
  "TCA1_CMP1/TCA1_LCMP1",       //  41: TC A1 Compare 1/TC A1 Low Compare 1
  "TCA1_CMP2/TCA1_LCMP2",       //  42: TC A1 Compare 2/TC A1 Low Compare 2
  "PORTE_PORT",                 //  43: Interrupt PORT E
  "PORTB_PORT",                 //  44: Interrupt PORT B
};

const char * const vtab_avr128da28[vts_avr128da28] = { // AVR128DA28, AVR64DA28, AVR32DA28
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "TWI0_TWIS",                  //  16: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  17: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  18: SPI 0 Interrupt
  "USART0_RXC",                 //  19: USART 0 Receive Complete
  "USART0_DRE",                 //  20: USART 0 Data Register Empty
  "USART0_TXC",                 //  21: USART 0 Transmit Complete
  "PORTD_PORT",                 //  22: Interrupt PORT D
  "AC0_AC",                     //  23: AC0 AC Interrupt
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_WCMP",                  //  25: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  26: Zero Cross Detect 0
  "PTC_PTC",                    //  27: PTC Interrupt
  "AC1_AC",                     //  28: AC1 AC Interrupt
  "PORTC_PORT",                 //  29: Interrupt PORT C
  "TCB2_INT",                   //  30: TC B2 Interrupt
  "USART1_RXC",                 //  31: USART 1 Receive Complete
  "USART1_DRE",                 //  32: USART 1 Data Register Empty
  "USART1_TXC",                 //  33: USART 1 Transmit Complete
  "PORTF_PORT",                 //  34: Interrupt PORT F
  "NVMCTRL_EE",                 //  35: NVM EEPROM
  "SPI1_INT",                   //  36: SPI 1 Interrupt
  "USART2_RXC",                 //  37: USART 2 Receive Complete
  "USART2_DRE",                 //  38: USART 2 Data Register Empty
  "USART2_TXC",                 //  39: USART 2 Transmit Complete
  "AC2_AC",                     //  40: AC2 AC Interrupt
};

const char * const vtab_avr128db28[vts_avr128db28] = { // AVR128DB28, AVR64DB28, AVR32DB28
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "MVIO_MVIO",                  //   4: Multi-Voltage I/O
  "RTC_CNT",                    //   5: RTC Counter Interrupt
  "RTC_PIT",                    //   6: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   7: Configurable Custom Logic
  "PORTA_PORT",                 //   8: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   9: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //  10: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  11: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  12: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  13: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  14: TC B0 Interrupt
  "TCB1_INT",                   //  15: TC B1 Interrupt
  "TCD0_OVF",                   //  16: TC D0 Overflow
  "TCD0_TRIG",                  //  17: TC D0 Trigger
  "TWI0_TWIS",                  //  18: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  19: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  20: SPI 0 Interrupt
  "USART0_RXC",                 //  21: USART 0 Receive Complete
  "USART0_DRE",                 //  22: USART 0 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "PORTD_PORT",                 //  24: Interrupt PORT D
  "AC0_AC",                     //  25: AC0 AC Interrupt
  "ADC0_RESRDY",                //  26: ADC 0 Result Ready
  "ADC0_WCMP",                  //  27: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  28: Zero Cross Detect 0
  "AC1_AC",                     //  29: AC1 AC Interrupt
  "PORTC_PORT",                 //  30: Interrupt PORT C
  "TCB2_INT",                   //  31: TC B2 Interrupt
  "USART1_RXC",                 //  32: USART 1 Receive Complete
  "USART1_DRE",                 //  33: USART 1 Data Register Empty
  "USART1_TXC",                 //  34: USART 1 Transmit Complete
  "PORTF_PORT",                 //  35: Interrupt PORT F
  "NVMCTRL_EE",                 //  36: NVM EEPROM
  "SPI1_INT",                   //  37: SPI 1 Interrupt
  "USART2_RXC",                 //  38: USART 2 Receive Complete
  "USART2_DRE",                 //  39: USART 2 Data Register Empty
  "USART2_TXC",                 //  40: USART 2 Transmit Complete
  "AC2_AC",                     //  41: AC2 AC Interrupt
};

const char * const vtab_avr128da32[vts_avr128da32] = { // AVR128DA32, AVR64DA32, AVR32DA32
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "TWI0_TWIS",                  //  16: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  17: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  18: SPI 0 Interrupt
  "USART0_RXC",                 //  19: USART 0 Receive Complete
  "USART0_DRE",                 //  20: USART 0 Data Register Empty
  "USART0_TXC",                 //  21: USART 0 Transmit Complete
  "PORTD_PORT",                 //  22: Interrupt PORT D
  "AC0_AC",                     //  23: AC0 AC Interrupt
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_WCMP",                  //  25: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  26: Zero Cross Detect 0
  "PTC_PTC",                    //  27: PTC Interrupt
  "AC1_AC",                     //  28: AC1 AC Interrupt
  "PORTC_PORT",                 //  29: Interrupt PORT C
  "TCB2_INT",                   //  30: TC B2 Interrupt
  "USART1_RXC",                 //  31: USART 1 Receive Complete
  "USART1_DRE",                 //  32: USART 1 Data Register Empty
  "USART1_TXC",                 //  33: USART 1 Transmit Complete
  "PORTF_PORT",                 //  34: Interrupt PORT F
  "NVMCTRL_EE",                 //  35: NVM EEPROM
  "SPI1_INT",                   //  36: SPI 1 Interrupt
  "USART2_RXC",                 //  37: USART 2 Receive Complete
  "USART2_DRE",                 //  38: USART 2 Data Register Empty
  "USART2_TXC",                 //  39: USART 2 Transmit Complete
  "AC2_AC",                     //  40: AC2 AC Interrupt
  "UNUSED",                     //  41: not implemented on this device
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
};

const char * const vtab_avr128db32[vts_avr128db32] = { // AVR128DB32, AVR64DB32, AVR32DB32
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "MVIO_MVIO",                  //   4: Multi-Voltage I/O
  "RTC_CNT",                    //   5: RTC Counter Interrupt
  "RTC_PIT",                    //   6: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   7: Configurable Custom Logic
  "PORTA_PORT",                 //   8: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   9: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //  10: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  11: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  12: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  13: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  14: TC B0 Interrupt
  "TCB1_INT",                   //  15: TC B1 Interrupt
  "TCD0_OVF",                   //  16: TC D0 Overflow
  "TCD0_TRIG",                  //  17: TC D0 Trigger
  "TWI0_TWIS",                  //  18: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  19: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  20: SPI 0 Interrupt
  "USART0_RXC",                 //  21: USART 0 Receive Complete
  "USART0_DRE",                 //  22: USART 0 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "PORTD_PORT",                 //  24: Interrupt PORT D
  "AC0_AC",                     //  25: AC0 AC Interrupt
  "ADC0_RESRDY",                //  26: ADC 0 Result Ready
  "ADC0_WCMP",                  //  27: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  28: Zero Cross Detect 0
  "AC1_AC",                     //  29: AC1 AC Interrupt
  "PORTC_PORT",                 //  30: Interrupt PORT C
  "TCB2_INT",                   //  31: TC B2 Interrupt
  "USART1_RXC",                 //  32: USART 1 Receive Complete
  "USART1_DRE",                 //  33: USART 1 Data Register Empty
  "USART1_TXC",                 //  34: USART 1 Transmit Complete
  "PORTF_PORT",                 //  35: Interrupt PORT F
  "NVMCTRL_EE",                 //  36: NVM EEPROM
  "SPI1_INT",                   //  37: SPI 1 Interrupt
  "USART2_RXC",                 //  38: USART 2 Receive Complete
  "USART2_DRE",                 //  39: USART 2 Data Register Empty
  "USART2_TXC",                 //  40: USART 2 Transmit Complete
  "AC2_AC",                     //  41: AC2 AC Interrupt
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
};

const char * const vtab_avr128da48[vts_avr128da48] = { // AVR128DA48, AVR64DA48, AVR32DA48
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "TWI0_TWIS",                  //  16: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  17: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  18: SPI 0 Interrupt
  "USART0_RXC",                 //  19: USART 0 Receive Complete
  "USART0_DRE",                 //  20: USART 0 Data Register Empty
  "USART0_TXC",                 //  21: USART 0 Transmit Complete
  "PORTD_PORT",                 //  22: Interrupt PORT D
  "AC0_AC",                     //  23: AC0 AC Interrupt
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_WCMP",                  //  25: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  26: Zero Cross Detect 0
  "PTC_PTC",                    //  27: PTC Interrupt
  "AC1_AC",                     //  28: AC1 AC Interrupt
  "PORTC_PORT",                 //  29: Interrupt PORT C
  "TCB2_INT",                   //  30: TC B2 Interrupt
  "USART1_RXC",                 //  31: USART 1 Receive Complete
  "USART1_DRE",                 //  32: USART 1 Data Register Empty
  "USART1_TXC",                 //  33: USART 1 Transmit Complete
  "PORTF_PORT",                 //  34: Interrupt PORT F
  "NVMCTRL_EE",                 //  35: NVM EEPROM
  "SPI1_INT",                   //  36: SPI 1 Interrupt
  "USART2_RXC",                 //  37: USART 2 Receive Complete
  "USART2_DRE",                 //  38: USART 2 Data Register Empty
  "USART2_TXC",                 //  39: USART 2 Transmit Complete
  "AC2_AC",                     //  40: AC2 AC Interrupt
  "TCB3_INT",                   //  41: TC B3 Interrupt
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
  "PORTB_PORT",                 //  44: Interrupt PORT B
  "PORTE_PORT",                 //  45: Interrupt PORT E
  "TCA1_LUNF/TCA1_OVF",         //  46: TC A1 Low Underflow/TC A1 Overflow
  "TCA1_HUNF",                  //  47: TC A1 High Underflow
  "TCA1_CMP0/TCA1_LCMP0",       //  48: TC A1 Compare 0/TC A1 Low Compare 0
  "TCA1_CMP1/TCA1_LCMP1",       //  49: TC A1 Compare 1/TC A1 Low Compare 1
  "TCA1_CMP2/TCA1_LCMP2",       //  50: TC A1 Compare 2/TC A1 Low Compare 2
  "ZCD1_ZCD",                   //  51: Zero Cross Detect 1
  "USART3_RXC",                 //  52: USART 3 Receive Complete
  "USART3_DRE",                 //  53: USART 3 Data Register Empty
  "USART3_TXC",                 //  54: USART 3 Transmit Complete
  "USART4_RXC",                 //  55: USART 4 Receive Complete
  "USART4_DRE",                 //  56: USART 4 Data Register Empty
  "USART4_TXC",                 //  57: USART 4 Transmit Complete
};

const char * const vtab_avr128db48[vts_avr128db48] = { // AVR128DB48, AVR64DB48, AVR32DB48
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "MVIO_MVIO",                  //   4: Multi-Voltage I/O
  "RTC_CNT",                    //   5: RTC Counter Interrupt
  "RTC_PIT",                    //   6: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   7: Configurable Custom Logic
  "PORTA_PORT",                 //   8: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   9: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //  10: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  11: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  12: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  13: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  14: TC B0 Interrupt
  "TCB1_INT",                   //  15: TC B1 Interrupt
  "TCD0_OVF",                   //  16: TC D0 Overflow
  "TCD0_TRIG",                  //  17: TC D0 Trigger
  "TWI0_TWIS",                  //  18: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  19: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  20: SPI 0 Interrupt
  "USART0_RXC",                 //  21: USART 0 Receive Complete
  "USART0_DRE",                 //  22: USART 0 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "PORTD_PORT",                 //  24: Interrupt PORT D
  "AC0_AC",                     //  25: AC0 AC Interrupt
  "ADC0_RESRDY",                //  26: ADC 0 Result Ready
  "ADC0_WCMP",                  //  27: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  28: Zero Cross Detect 0
  "AC1_AC",                     //  29: AC1 AC Interrupt
  "PORTC_PORT",                 //  30: Interrupt PORT C
  "TCB2_INT",                   //  31: TC B2 Interrupt
  "USART1_RXC",                 //  32: USART 1 Receive Complete
  "USART1_DRE",                 //  33: USART 1 Data Register Empty
  "USART1_TXC",                 //  34: USART 1 Transmit Complete
  "PORTF_PORT",                 //  35: Interrupt PORT F
  "NVMCTRL_EE",                 //  36: NVM EEPROM
  "SPI1_INT",                   //  37: SPI 1 Interrupt
  "USART2_RXC",                 //  38: USART 2 Receive Complete
  "USART2_DRE",                 //  39: USART 2 Data Register Empty
  "USART2_TXC",                 //  40: USART 2 Transmit Complete
  "AC2_AC",                     //  41: AC2 AC Interrupt
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
  "TCB3_INT",                   //  44: TC B3 Interrupt
  "PORTB_PORT",                 //  45: Interrupt PORT B
  "PORTE_PORT",                 //  46: Interrupt PORT E
  "TCA1_LUNF/TCA1_OVF",         //  47: TC A1 Low Underflow/TC A1 Overflow
  "TCA1_HUNF",                  //  48: TC A1 High Underflow
  "TCA1_CMP0/TCA1_LCMP0",       //  49: TC A1 Compare 0/TC A1 Low Compare 0
  "TCA1_CMP1/TCA1_LCMP1",       //  50: TC A1 Compare 1/TC A1 Low Compare 1
  "TCA1_CMP2/TCA1_LCMP2",       //  51: TC A1 Compare 2/TC A1 Low Compare 2
  "ZCD1_ZCD",                   //  52: Zero Cross Detect 1
  "USART3_RXC",                 //  53: USART 3 Receive Complete
  "USART3_DRE",                 //  54: USART 3 Data Register Empty
  "USART3_TXC",                 //  55: USART 3 Transmit Complete
  "USART4_RXC",                 //  56: USART 4 Receive Complete
  "USART4_DRE",                 //  57: USART 4 Data Register Empty
  "USART4_TXC",                 //  58: USART 4 Transmit Complete
  "UNUSED",                     //  59: not implemented on this device
  "ZCD2_ZCD",                   //  60: Zero Cross Detect 2
};

const char * const vtab_avr128da64[vts_avr128da64] = { // AVR128DA64, AVR64DA64
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "RTC_CNT",                    //   3: RTC Counter Interrupt
  "RTC_PIT",                    //   4: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   5: Configurable Custom Logic
  "PORTA_PORT",                 //   6: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   7: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //   8: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //   9: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  10: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  11: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  12: TC B0 Interrupt
  "TCB1_INT",                   //  13: TC B1 Interrupt
  "TCD0_OVF",                   //  14: TC D0 Overflow
  "TCD0_TRIG",                  //  15: TC D0 Trigger
  "TWI0_TWIS",                  //  16: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  17: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  18: SPI 0 Interrupt
  "USART0_RXC",                 //  19: USART 0 Receive Complete
  "USART0_DRE",                 //  20: USART 0 Data Register Empty
  "USART0_TXC",                 //  21: USART 0 Transmit Complete
  "PORTD_PORT",                 //  22: Interrupt PORT D
  "AC0_AC",                     //  23: AC0 AC Interrupt
  "ADC0_RESRDY",                //  24: ADC 0 Result Ready
  "ADC0_WCMP",                  //  25: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  26: Zero Cross Detect 0
  "PTC_PTC",                    //  27: PTC Interrupt
  "AC1_AC",                     //  28: AC1 AC Interrupt
  "PORTC_PORT",                 //  29: Interrupt PORT C
  "TCB2_INT",                   //  30: TC B2 Interrupt
  "USART1_RXC",                 //  31: USART 1 Receive Complete
  "USART1_DRE",                 //  32: USART 1 Data Register Empty
  "USART1_TXC",                 //  33: USART 1 Transmit Complete
  "PORTF_PORT",                 //  34: Interrupt PORT F
  "NVMCTRL_EE",                 //  35: NVM EEPROM
  "SPI1_INT",                   //  36: SPI 1 Interrupt
  "USART2_RXC",                 //  37: USART 2 Receive Complete
  "USART2_DRE",                 //  38: USART 2 Data Register Empty
  "USART2_TXC",                 //  39: USART 2 Transmit Complete
  "AC2_AC",                     //  40: AC2 AC Interrupt
  "TCB3_INT",                   //  41: TC B3 Interrupt
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
  "PORTB_PORT",                 //  44: Interrupt PORT B
  "PORTE_PORT",                 //  45: Interrupt PORT E
  "TCA1_LUNF/TCA1_OVF",         //  46: TC A1 Low Underflow/TC A1 Overflow
  "TCA1_HUNF",                  //  47: TC A1 High Underflow
  "TCA1_CMP0/TCA1_LCMP0",       //  48: TC A1 Compare 0/TC A1 Low Compare 0
  "TCA1_CMP1/TCA1_LCMP1",       //  49: TC A1 Compare 1/TC A1 Low Compare 1
  "TCA1_CMP2/TCA1_LCMP2",       //  50: TC A1 Compare 2/TC A1 Low Compare 2
  "ZCD1_ZCD",                   //  51: Zero Cross Detect 1
  "USART3_RXC",                 //  52: USART 3 Receive Complete
  "USART3_DRE",                 //  53: USART 3 Data Register Empty
  "USART3_TXC",                 //  54: USART 3 Transmit Complete
  "USART4_RXC",                 //  55: USART 4 Receive Complete
  "USART4_DRE",                 //  56: USART 4 Data Register Empty
  "USART4_TXC",                 //  57: USART 4 Transmit Complete
  "PORTG_PORT",                 //  58: Interrupt PORT G
  "ZCD2_ZCD",                   //  59: Zero Cross Detect 2
  "TCB4_INT",                   //  60: TC B4 Interrupt
  "USART5_RXC",                 //  61: USART 5 Receive Complete
  "USART5_DRE",                 //  62: USART 5 Data Register Empty
  "USART5_TXC",                 //  63: USART 5 Transmit Complete
};

const char * const vtab_avr128db64[vts_avr128db64] = { // AVR128DB64, AVR64DB64
  "RESET",                      //   0: Reset (various reasons)
  "CRCSCAN_NMI",                //   1: CRCSCAN Non-maskable Interrupt
  "BOD_VLM",                    //   2: Brown-out Detector Voltage Level Monitor
  "CLKCTRL_CFD",                //   3: Clock Failure Detection
  "MVIO_MVIO",                  //   4: Multi-Voltage I/O
  "RTC_CNT",                    //   5: RTC Counter Interrupt
  "RTC_PIT",                    //   6: RTC Periodic Interrupt Timer
  "CCL_CCL",                    //   7: Configurable Custom Logic
  "PORTA_PORT",                 //   8: Interrupt PORT A
  "TCA0_LUNF/TCA0_OVF",         //   9: TC A0 Low Underflow/TC A0 Overflow
  "TCA0_HUNF",                  //  10: TC A0 High Underflow
  "TCA0_CMP0/TCA0_LCMP0",       //  11: TC A0 Compare 0/TC A0 Low Compare 0
  "TCA0_CMP1/TCA0_LCMP1",       //  12: TC A0 Compare 1/TC A0 Low Compare 1
  "TCA0_CMP2/TCA0_LCMP2",       //  13: TC A0 Compare 2/TC A0 Low Compare 2
  "TCB0_INT",                   //  14: TC B0 Interrupt
  "TCB1_INT",                   //  15: TC B1 Interrupt
  "TCD0_OVF",                   //  16: TC D0 Overflow
  "TCD0_TRIG",                  //  17: TC D0 Trigger
  "TWI0_TWIS",                  //  18: 2-Wire Interface 0 Periphery
  "TWI0_TWIM",                  //  19: 2-Wire Interface 0 Controller
  "SPI0_INT",                   //  20: SPI 0 Interrupt
  "USART0_RXC",                 //  21: USART 0 Receive Complete
  "USART0_DRE",                 //  22: USART 0 Data Register Empty
  "USART0_TXC",                 //  23: USART 0 Transmit Complete
  "PORTD_PORT",                 //  24: Interrupt PORT D
  "AC0_AC",                     //  25: AC0 AC Interrupt
  "ADC0_RESRDY",                //  26: ADC 0 Result Ready
  "ADC0_WCMP",                  //  27: ADC 0 Window Comparator
  "ZCD0_ZCD",                   //  28: Zero Cross Detect 0
  "AC1_AC",                     //  29: AC1 AC Interrupt
  "PORTC_PORT",                 //  30: Interrupt PORT C
  "TCB2_INT",                   //  31: TC B2 Interrupt
  "USART1_RXC",                 //  32: USART 1 Receive Complete
  "USART1_DRE",                 //  33: USART 1 Data Register Empty
  "USART1_TXC",                 //  34: USART 1 Transmit Complete
  "PORTF_PORT",                 //  35: Interrupt PORT F
  "NVMCTRL_EE",                 //  36: NVM EEPROM
  "SPI1_INT",                   //  37: SPI 1 Interrupt
  "USART2_RXC",                 //  38: USART 2 Receive Complete
  "USART2_DRE",                 //  39: USART 2 Data Register Empty
  "USART2_TXC",                 //  40: USART 2 Transmit Complete
  "AC2_AC",                     //  41: AC2 AC Interrupt
  "TWI1_TWIS",                  //  42: 2-Wire Interface 1 Periphery
  "TWI1_TWIM",                  //  43: 2-Wire Interface 1 Controller
  "TCB3_INT",                   //  44: TC B3 Interrupt
  "PORTB_PORT",                 //  45: Interrupt PORT B
  "PORTE_PORT",                 //  46: Interrupt PORT E
  "TCA1_LUNF/TCA1_OVF",         //  47: TC A1 Low Underflow/TC A1 Overflow
  "TCA1_HUNF",                  //  48: TC A1 High Underflow
  "TCA1_CMP0/TCA1_LCMP0",       //  49: TC A1 Compare 0/TC A1 Low Compare 0
  "TCA1_CMP1/TCA1_LCMP1",       //  50: TC A1 Compare 1/TC A1 Low Compare 1
  "TCA1_CMP2/TCA1_LCMP2",       //  51: TC A1 Compare 2/TC A1 Low Compare 2
  "ZCD1_ZCD",                   //  52: Zero Cross Detect 1
  "USART3_RXC",                 //  53: USART 3 Receive Complete
  "USART3_DRE",                 //  54: USART 3 Data Register Empty
  "USART3_TXC",                 //  55: USART 3 Transmit Complete
  "USART4_RXC",                 //  56: USART 4 Receive Complete
  "USART4_DRE",                 //  57: USART 4 Data Register Empty
  "USART4_TXC",                 //  58: USART 4 Transmit Complete
  "PORTG_PORT",                 //  59: Interrupt PORT G
  "ZCD2_ZCD",                   //  60: Zero Cross Detect 2
  "TCB4_INT",                   //  61: TC B4 Interrupt
  "USART5_RXC",                 //  62: USART 5 Receive Complete
  "USART5_DRE",                 //  63: USART 5 Data Register Empty
  "USART5_TXC",                 //  64: USART 5 Transmit Complete
};

