403 lines
8.3 KiB
C++
403 lines
8.3 KiB
C++
#include "spi.h"
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#include "rc522.h"
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void Write_MFRC522(uchar addr, uchar val)
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{
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spi::cs_low();
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spi::transfer((addr<<1)&0x7E);
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spi::transfer(val);
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spi::cs_high();
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}
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uchar Read_MFRC522(uchar addr)
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{
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uchar val;
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spi::cs_low();
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//address format: 1XXXXXX0
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spi::transfer(((addr<<1)&0x7E) | 0x80);
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val =spi::transfer(0x00);
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spi::cs_high();
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return val;
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}
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void SetBitMask(uchar reg, uchar mask)
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{
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uchar tmp;
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tmp = Read_MFRC522(reg);
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Write_MFRC522(reg, tmp | mask); // set bit mask
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}
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void ClearBitMask(uchar reg, uchar mask)
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{
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uchar tmp;
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tmp = Read_MFRC522(reg);
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Write_MFRC522(reg, tmp & (~mask)); // clear bit mask
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}
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void AntennaOn(void)
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{
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uchar temp;
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temp = Read_MFRC522(TxControlReg);
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if (!(temp & 0x03))
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{
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SetBitMask(TxControlReg, 0x03);
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}
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}
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void AntennaOff(void)
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{
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ClearBitMask(TxControlReg, 0x03);
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}
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void MFRC522_Reset(void)
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{
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Write_MFRC522(CommandReg, PCD_RESETPHASE);
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}
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void MFRC522_Init(void)
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{
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spi::init();
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NRSTPD_DDR |= (1<<NRSTPD_PIN);
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NRSTPD_PORT |= (1<<NRSTPD_PIN);
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MFRC522_Reset();
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//Timer: TPrescaler*TreloadVal/6.78MHz = 24ms
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Write_MFRC522(TModeReg, 0x8D); //Tauto=1; f(Timer) = 6.78MHz/TPreScaler
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Write_MFRC522(TPrescalerReg, 0x3E); //TModeReg[3..0] + TPrescalerReg
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Write_MFRC522(TReloadRegL, 30);
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Write_MFRC522(TReloadRegH, 0);
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Write_MFRC522(TxAutoReg, 0x40); //100%ASK
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Write_MFRC522(ModeReg, 0x3D); //CRC original value 0x6363 ???
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AntennaOn(); // open antenna
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}
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uchar MFRC522_Request(uchar reqMode, uchar *TagType)
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{
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uchar status;
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uint backBits; // bits of data received
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Write_MFRC522(BitFramingReg, 0x07); //TxLastBists = BitFramingReg[2..0] ???
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TagType[0] = reqMode;
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status = MFRC522_ToCard(PCD_TRANSCEIVE, TagType, 1, TagType, &backBits);
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if ((status != MI_OK) || (backBits != 0x10))
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{
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status = MI_ERR;
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}
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return status;
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}
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uchar MFRC522_ToCard(uchar command, uchar *sendData, uchar sendLen, uchar *backData, uint *backLen)
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{
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uchar status = MI_ERR;
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uchar irqEn = 0x00;
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uchar waitIRq = 0x00;
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uchar lastBits;
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uchar n;
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uint i;
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switch (command)
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{
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case PCD_AUTHENT: // card key authentication
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{
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irqEn = 0x12;
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waitIRq = 0x10;
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break;
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}
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case PCD_TRANSCEIVE: // send data in FIFO
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{
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irqEn = 0x77;
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waitIRq = 0x30;
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break;
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}
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default:
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break;
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}
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Write_MFRC522(CommIEnReg, irqEn|0x80); // permission for interrupt request
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ClearBitMask(CommIrqReg, 0x80); // clear all bits of the interrupt request
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SetBitMask(FIFOLevelReg, 0x80); //FlushBuffer=1, FIFO initialize
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Write_MFRC522(CommandReg, PCD_IDLE); //NO action; clear current command ???
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// write data into FIFO
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for (i=0; i<sendLen; i++)
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{
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Write_MFRC522(FIFODataReg, sendData[i]);
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}
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// execute command
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Write_MFRC522(CommandReg, command);
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if (command == PCD_TRANSCEIVE)
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{
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SetBitMask(BitFramingReg, 0x80); //StartSend=1,transmission of data starts
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}
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// wait for the completion of data transmission
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i = 2000; // adjust i according to clock frequency, max wait time for M1 card operation 25ms ???
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do
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{
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//CommIrqReg[7..0]
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//Set1 TxIRq RxIRq IdleIRq HiAlerIRq LoAlertIRq ErrIRq TimerIRq
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n = Read_MFRC522(CommIrqReg);
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i--;
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}
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while ((i!=0) && !(n&0x01) && !(n&waitIRq));
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ClearBitMask(BitFramingReg, 0x80); //StartSend=0
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if (i != 0)
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{
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if(!(Read_MFRC522(ErrorReg) & 0x1B)) //BufferOvfl Collerr CRCErr ProtecolErr
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{
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status = MI_OK;
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if (n & irqEn & 0x01)
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{
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status = MI_NOTAGERR; //??
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}
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if (command == PCD_TRANSCEIVE)
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{
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n = Read_MFRC522(FIFOLevelReg);
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lastBits = Read_MFRC522(ControlReg) & 0x07;
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if (lastBits)
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{
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*backLen = (n-1)*8 + lastBits;
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}
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else
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{
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*backLen = n*8;
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}
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if (n == 0)
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{
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n = 1;
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}
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if (n > MAX_LEN)
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{
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n = MAX_LEN;
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}
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// read the data received in FIFO
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for (i=0; i<n; i++)
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{
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backData[i] = Read_MFRC522(FIFODataReg);
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}
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}
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}
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else
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{
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status = MI_ERR;
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}
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}
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//SetBitMask(ControlReg,0x80); //timer stops
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//Write_MFRC522(CommandReg, PCD_IDLE);
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return status;
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}
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uchar MFRC522_Anticoll(uchar *serNum)
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{
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uchar status;
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uchar i;
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uchar serNumCheck=0;
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uint unLen;
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Write_MFRC522(BitFramingReg, 0x00); //TxLastBists = BitFramingReg[2..0]
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serNum[0] = PICC_ANTICOLL;
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serNum[1] = 0x20;
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status = MFRC522_ToCard(PCD_TRANSCEIVE, serNum, 2, serNum, &unLen);
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if (status == MI_OK)
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{
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// verify card sequence number
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for (i=0; i<4; i++)
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{
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serNumCheck ^= serNum[i];
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}
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if (serNumCheck != serNum[i])
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{
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status = MI_ERR;
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}
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}
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//SetBitMask(CollReg, 0x80); //ValuesAfterColl=1
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return status;
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}
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void CalulateCRC(uchar *pIndata, uchar len, uchar *pOutData)
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{
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uchar i, n;
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ClearBitMask(DivIrqReg, 0x04); //CRCIrq = 0
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SetBitMask(FIFOLevelReg, 0x80); // clear FIFO pointer
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//Write_MFRC522(CommandReg, PCD_IDLE);
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// write data into FIFO
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for (i=0; i<len; i++)
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{
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Write_MFRC522(FIFODataReg, *(pIndata+i));
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}
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Write_MFRC522(CommandReg, PCD_CALCCRC);
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// wait for completion of CRC calculation
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i = 0xFF;
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do
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{
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n = Read_MFRC522(DivIrqReg);
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i--;
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}
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while ((i!=0) && !(n&0x04)); //CRCIrq = 1
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// read result from CRC calculation
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pOutData[0] = Read_MFRC522(CRCResultRegL);
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pOutData[1] = Read_MFRC522(CRCResultRegM);
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}
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uchar MFRC522_SelectTag(uchar *serNum)
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{
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uchar i;
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uchar status;
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uchar size;
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uint recvBits;
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uchar buffer[9];
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//ClearBitMask(Status2Reg, 0x08); //MFCrypto1On=0
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buffer[0] = PICC_SElECTTAG;
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buffer[1] = 0x70;
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for (i=0; i<5; i++)
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{
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buffer[i+2] = *(serNum+i);
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}
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CalulateCRC(buffer, 7, &buffer[7]); //??
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status = MFRC522_ToCard(PCD_TRANSCEIVE, buffer, 9, buffer, &recvBits);
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if ((status == MI_OK) && (recvBits == 0x18))
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{
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size = buffer[0];
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}
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else
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{
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size = 0;
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}
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return size;
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}
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uchar MFRC522_Auth(uchar authMode, uchar BlockAddr, uchar *Sectorkey, uchar *serNum)
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{
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uchar status;
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uint recvBits;
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uchar i;
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uchar buff[12];
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// Verification instructions + block address + sector password + card sequence number
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buff[0] = authMode;
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buff[1] = BlockAddr;
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for (i=0; i<6; i++)
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{
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buff[i+2] = *(Sectorkey+i);
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}
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for (i=0; i<4; i++)
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{
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buff[i+8] = *(serNum+i);
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}
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status = MFRC522_ToCard(PCD_AUTHENT, buff, 12, buff, &recvBits);
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if ((status != MI_OK) || (!(Read_MFRC522(Status2Reg) & 0x08)))
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{
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status = MI_ERR;
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}
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return status;
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}
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uchar MFRC522_Read(uchar blockAddr, uchar *recvData)
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{
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uchar status;
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uint unLen;
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recvData[0] = PICC_READ;
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recvData[1] = blockAddr;
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CalulateCRC(recvData,2, &recvData[2]);
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status = MFRC522_ToCard(PCD_TRANSCEIVE, recvData, 4, recvData, &unLen);
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if ((status != MI_OK) || (unLen != 0x90))
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{
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status = MI_ERR;
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}
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return status;
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}
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uchar MFRC522_Write(uchar blockAddr, uchar *writeData)
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{
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uchar status;
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uint recvBits;
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uchar i;
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uchar buff[18];
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buff[0] = PICC_WRITE;
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buff[1] = blockAddr;
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CalulateCRC(buff, 2, &buff[2]);
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status = MFRC522_ToCard(PCD_TRANSCEIVE, buff, 4, buff, &recvBits);
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if ((status != MI_OK) || (recvBits != 4) || ((buff[0] & 0x0F) != 0x0A))
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{
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status = MI_ERR;
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}
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if (status == MI_OK)
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{
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for (i=0; i<16; i++) // write 16Byte data into FIFO
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{
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buff[i] = *(writeData+i);
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}
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CalulateCRC(buff, 16, &buff[16]);
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status = MFRC522_ToCard(PCD_TRANSCEIVE, buff, 18, buff, &recvBits);
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if ((status != MI_OK) || (recvBits != 4) || ((buff[0] & 0x0F) != 0x0A))
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{
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status = MI_ERR;
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}
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}
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return status;
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}
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void MFRC522_Halt(void)
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{
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uchar status;
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uint unLen;
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uchar buff[4];
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buff[0] = PICC_HALT;
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buff[1] = 0;
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CalulateCRC(buff, 2, &buff[2]);
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status = MFRC522_ToCard(PCD_TRANSCEIVE, buff, 4, buff,&unLen);
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} |